ANADIGICS ACD2202S8P1

ACD2202
CATV/TV/Video Downconverter
with Dual Synthesizer
Data Sheet - Rev 2.1
FEATURES
•
Integrated Downconverter
•
Integrated Dual Synthesizer
•
256 QAM Compatibility
•
Single +5 V Power Supply Operation
•
Low Power Consumption: <0.6 W
•
Low Noise Figure: 8 dB
•
High Conversion Gain: 10 dB
•
Low Distortion: -53 dBc
•
Three-Wire Interface
•
Small Size
•
-40 °C to +85 °C
APPLICATIONS
•
Set Top Boxes
•
CATV Video Tuners
•
Digital TV Tuners
•
CATV Data Tuners
•
Cable Modems
S8 Package
28 Pin SSOP
PRODUCT DESCRIPTION
The ACD2202 uses both GaAs and Si technology
to provide the downconverter and dual synthesizer
functions in a double conversion tuner gain block,
local oscillator, balanced mixer and dual synthesizer.
The specifications meet the requirements of
CATV/TV/Video and Cable Modem Data applications.
The ACD2202 is supplied in a 28 lead SSOP
package and requires a single +5 V supply voltage.
The IC is well suited for applications where small
size, low cost, low auxiliary parts count and a nocompromise performance is important. It provides
for cost reduction by lowering the component and
packaged IC count and decreasing the amount of
labor-intensive production alignment steps, while
significantly improving performance and reliability.
RFD
VIF+IFOUT+
RFIN+
RFINLow Noise
VGA
VIF+IFOUT-
18 Bit RF2
N Counter
RF2
Phase
Detector
RF2
Charge
Pump
CPD
RF1
Phase
Detector
RF1
Charge
Pump
CPU
15 Bit RF2
R Counter
REFIN
REFOUT
Oscillator
Mixer
15 Bit RF1
R Counter
RFU
Phase Splitter
TCKT
RF2: 64/65
Prescaler
OSC OUT
Clock
Data
Enable
Figure 1: Downconverter Block Diagram
RF1: 64/65
Prescaler
18 Bit RF1
N Counter
22 Bit
Data Registar
Figure 2: Dual Synthesizer Block Diagram
12/2003
ACD2202
1
RFIN+
VIF + IFOUT+
28
2
RFIN-
VIF + IFOUT-
27
3
GND
GND
26
4
ISET
VSUP
25
5
TCKT
OSCOUT
24
6
OSCGND
GND
23
7
OSCGND
GND
22
8
VSS
VSS
21
9
VSS
VSS
20
10
EN
RFD
19
11
DATA
CPD
18
12
CLK
CPU
17
13
REFIN
RFU
16
14
REFOUT
VSYN
15
Figure 3: Pinout
2
Data Sheet - Rev 2.1
12/2003
ACD2202
Table 1: Pin Description
PIN
NAME
DESCRIPTION
PIN
NAME
DESCRIPTION
VIF+IFOUT+
Downconverter
Differential IFOutput
Inductively coupled to
+VDD
27
VIF+IFOUT -
Downconverter
Differential IFOutput
Inductively coupled to
+VDD
Downconverter Ground
(Must be connected)
26
GND
Downconverter Ground
(Must be connected)
ISET
Downconverter Gilbert
Cell Current Source
Resistor
25
VSUP
Oscillator and Phase
Splitter Supply (+VDD)
TCKT
Oscillator Input Port
(Tank circuit connection)
24
OSCOUT
Oscillator Output
(Connected to
Synthesizer RF Input)
6
OSCGND
Oscillator Tank Circuit
Ground (Not to be
connected to any other
circuit ground)
23
GND
Downconverter Ground
(Must be connected)
7
OSCGND
Same as Pin 6
22
GND
Downconverter Ground
(Must be connected)
8
V SS
Synthesizer Ground
(Required)
21
V SS
Synthesizer Ground
(Required)
9
V SS
Synthesizer Ground
(Required)
20
V SS
Synthesizer Ground
(Required)
10
EN
3-Wire Interface Enable
19
RFD
Synthesizer
Downconverter RFInput
11
DATA
3-Wire Interface Data
18
C PD
Synthesizer
Downconverter
Charge Pump Output
12
C LK
3-Wire Interface Clock
17
C PU
Synthesizer Upconverter
Charge Pump Output
13
REFIN
Crystal Reference Input
16
RFU
Synthesizer Upconverter
RFInput
14
REFOUT
Crystal Reference Output
15
VSYN
Synthesizer Supply
(+VDD)
RFIN+
Downconverter
Differential RFInput
2
RFIN-
Downconverter
Differential RFInput
3
GND
4
5
1
28
Data Sheet - Rev 2.1
12/2003
3
ACD2202
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
PARAMETER
MIN
MAX
UNIT
Supply Voltage (pins 25, 27 & 28)
(pin 15)
-
+9
+6.5
VD C
Voltage on pins 10 through 14, 16
through 19 with VSS = 0 V
-0.3
VSYN +0.3
VD C
Input Voltages (pins 1, 2 & 5)
-
0
VD C
Input Power
-
+10
+17
+20
dB m
-55
+150
°C
Soldering Temperature
-
260
°C
Soldering Time
-
4
S ec
Thermal Impedance, θJC
-
40
°C/W
(pins 1 & 2)
(pin 5)
(pins 13, 16 & 19)
Storage Temperature
Stresses in excess of the absolute ratings may cause permanent damage.
Functional operation is not implied under these conditions. Exposure to absolute
ratings for extended periods of time may adversely affect reliability.
Table 3: Operating Ranges
PARAMETER
Downconverter Frequencies
RF Input (RF)
IF Output (IF)
Local Oscillator (LO)
MIN
TYP
MAX
UNIT
900
35
865
-
1200
150
1350
MHz
400
400
2
-
4
-
2100
1400
20
10
MHz
+4.70
+5
+5.25
VD C
-40
-
+85
°C
(1)
Synthesizer Frequencies
Upconverter Synthesizer (RFU)
Downconverter Synthesizer (RFD)
Reference Oscillator (REFIN)
Phase Detector
Supply Voltage: VDD (pins 15, 25, 27, 28)
Ambient Operating Temperature: TA
(2)
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical
specifications.
Notes:
(1) Mixer operation is possible beyond these frequencies with slightly reduced
performance.
(2) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient
Temperature is +25 °C, using the PC Board Layout shown in Figures 23-25.
4
Data Sheet - Rev 2.1
12/2003
ACD2202
Table 4: Electrical Specifications - Downconverter Section
(7)
(TA = 25 °C , VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz)
PARAMETER
MIN
TYP
MAX
UNIT
Conversion Gain (1)
Conversion Gain (2)
8
11
10
13
14
17
dB
SSB Noise Figure (2), (3)
-
4
7
dB
Cross Modulation
-
-56
-53
dB c
-
-
-53
dB c
+12
-
-
dB m
-
-90
-85.5
dBc/Hz
-10
-5
-
dB m
Spurious @ IF Output
LO Signals and Harmonics
Beats Within Output Channel
Other Beats from 2 to 200 MHz
Other Spurious
-
-10
-48
-50
-10
-
dB m
dB c
dB m
dB m
IF Supply Current (pin 27 & 28) (1), (2),(6)
-
50
65
mA
Osc/Phase Splitter Supply Current
(pin 25)
-
30
45
mA
Power Consumption
-
400
550
mW
(2), (4), (6)
3rd Order Intermodulation Distortion
(IMD3) (2), (5), (6)
2-Tone 3rd Order Input Intercept Point
(IIP3) (2), (5), (6)
LO Phase Noise (@ 10 KHz Offset) (1), (2)
LO Output Power (pin 24) (1), (2)
Notes:
(1) As measured in ANADIGICS test fixture with single-ended RF input.
(2) As measured in ANADIGICS test fixture with differential RF inputs.
(3) SSB noise figure will be approximately 3 dB higher with single-ended RF input.
(4) Two tones: 1085 and 1091 MHz, -20 dBm each, 1091 MHz tone AM-modulated
99% at 15 kHz.
(5) Two tones: 1085 and 1091 MHz, -15 dBm each.
(6) R1 = 10 Ohms.
(7) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient
Temperature is +25 °C, using the PC Board Layout shown in Figures 23-25.
Data Sheet - Rev 2.1
12/2003
5
ACD2202
Table 5: Electrical Specifications - Synthesizer Section
(4)
(TA = 25 °C , VDD = +5 VDC)
PARAMETER
MIN
TYP
MAX
UNIT
Prescalar Input Sensitivity
Upconverter: RFU (pin 16) (1)
Downconverter: RFD (pin 19) (2)
Upconverter: RFU (pin 16) (1)
Downconverter: RFD (pin 19) (2)
-7
-13
-6
-11
-
+20
+20
-
Reference Oscillator Sensitivity (pin 13)
-
0.5
-
Vp-p
Charge Pump Output Current (3)
SINK
SOURCE
-
1.25
-1.25
-
mA
Supply Current
-
35
50
mA
Power Consumption
-
165
250
mW
COMMENTS
(over operating frequency)
dB m
TA = +85 °C, VDD = +4.7 V
TA = +85 °C, VDD = +4.7 V
Notes:
(1) Measured at 250 kHz comparison frequency.
(2) Measured at 62.5 kHz comparison frequency.
(3) CPU and CPD = VCC/2.
(4) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient Temperature is +25 °C, using the
PC Board Layout shown in Figures 23-25.
6
Data Sheet - Rev 2.1
12/2003
ACD2202
Table 6: Digital Interface Specifications
(TA = 25 °C, VDD = +5 VDC, ref. Figure 4)
PARAMETER
MIN
TYP
MAX
UNIT
Logic High Input: VH (pins 10, 11, 12)
2.0
-
-
V
Logic Low Input: VL (pins 10, 11, 12)
-
-
0.8
V
Logic Input Current Consumption
(pins 10, 11, 12)
-
-
0.01
mA
Data to Clock Set Up Time: tCS
50
-
-
ns
Data to Clock Hold Time: tCH
10
-
-
ns
Clock Pulse Width High: tCWH
50
-
-
ns
Clock Pulse Width Low: tCWL
50
-
-
ns
Clock to Load Enable Setup Time: tES
50
-
-
ns
Load Enable Pulse Width: tEW
50
-
-
ns
Rise Time: tR
-
10
-
ns
Fall Time: tF
-
10
-
ns
DATA
N20: MSB
(R20: MSB)
N19
N10
(R19)
R10
N9
C2
(R9)
(R8)
(C2)
C1: LSB
(C1: LSB)
CLOCK
tCWL
LE
OR
LE
t CS
t CH
t CWH
t ES
t EW
Figure 4: Serial Data Input Timing
Data Sheet - Rev 2.1
12/2003
7
ACD2202
PERFORMANCE DATA
15.0
5.0
13.8
3.63
14.0
4.6
13.6
3.61
13.0
4.2
13.4
3.59
12.0
3.8
Conversion Gain
13.2
Conversion Gain (dB)
3.65
Noise Figure (dB)
Conversion Gain (dB)
14.0
13.0
4.8
4.9
5.0
5.1
5.2
3.0
25
5.3
35
55
75
85
Figure 8: Typical Phase Noise at 10 kHz Offset
vs. Ambient Temperature
(VDD = +5 V, fLO2 = 1042 MHz)
-90
-84
-91
-86
-92
-93
-88
-90
-92
-94
-94
-95
4.7
4.8
4.9
5.0
5.1
5.2
25
5.3
35
45
Figure 9: Typical Local Oscillator Output Power
vs. Supply Voltage
(TA = +25 °C, fLO2 = 1042 MHz)
-5.0
-5.0
Output Power (dBm)
-4.5
-6.0
65
75
85
Figure 10: Typical Local Oscillator Output Power
vs. Ambient Temperature
(VDD = +5 V, fLO2 = 1042 MHz)
-4.5
-5.5
55
Ambient Temperature (°C)
Supply Voltage (V)
Output Power (dBm)
65
Figure 7: Typical Phase Noise at 10 kHz Offset
vs. Supply Voltage
(TA = +25 °C, fLO2 = 1042 MHz)
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
45
Ambient Temperature (°C)
Supply Voltage (V)
-5.5
-6.0
-6.5
-6.5
-7.0
-7.0
4.7
4.8
4.9
5.0
5.1
5.2
5.3
25
Supply Voltage (V)
8
3.4
Noise Figure
10.0
3.55
4.7
Conversion Gain
11.0
3.57
Noise Figure
Noise Figure (dB)
Figure 6: Typical Conversion Gain and Noise
Figure vs. Ambient Temperature
(VDD = +5 V, fLO2 = 1042 MHz)
Figure 5: Typical Conversion Gain and Noise
Figure vs. Supply Voltage
(TA = +25 °C, fLO2 = 1042 MHz)
Data Sheet - Rev 2.1
12/2003
35
45
55
Ambient Temperature (°C)
65
75
85
ACD2202
Figure 12: Typical Downconverter Prescaler
Sensitivity vs. Local Oscillator Frequency
(TA = +25 °C, VDD = +5 V)
-5
-12
-10
-14
Prescalar Sensitivity (dBm)
Prescalar Sensitivity (dBm)
Figure 11: Typical Upconverter Prescaler
Sensitivity vs. Local Oscillator Frequency
(TA = +25 °C, VDD = +5 V)
-15
-20
-25
-30
-35
500
700
900
1100
1300
1500
1700
1900
-16
-18
-20
-22
-24
400
2100
600
800
LO1 Frequency (MHz)
1400
-16.0
Prescalar Sensitivity (dBm)
-7.0
Prescalar Sensitivity (dBm)
1200
Figure 14: Typical Downconverter Prescaler
Sensitivity vs. Supply Voltage
(TA = +25 °C, fLO2 = 1000 MHz)
Figure 13: Typical Upconverter Prescaler
Sensitivity vs. Supply Voltage
(TA = +25 °C, fLO1 = 2100 MHz)
-7.5
-8.0
-8.5
-9.0
4.7
4.8
4.9
5.0
5.1
5.2
-16.5
-17.0
-17.5
-18.0
5.3
4.7
4.8
4.9
Supply Voltage (V)
5.0
5.1
5.2
5.3
Supply Voltage (V)
Figure 15: Typical Upconverter Prescaler
Sensitivity vs. Ambient Temperature
(VDD = +5 V, fLO1 = 2100 MHz)
Figure 16: Typical Downconverter Prescaler
Sensitivity vs. Ambient Temperature
(VDD = +5 V, fLO2 = 1000 MHz)
-6.0
-15.0
Prescalar Sensitivity (dBm)
Prescalar Sensitivity (dBm)
1000
LO2 Frequency (MHz)
-6.5
-7.0
-7.5
-8.0
-15.5
-16.0
-16.5
-17.0
-17.5
-8.5
25
35
45
55
65
75
85
25
35
45
55
65
75
85
Ambient Temperature (°C)
Ambient Temperature (°C)
Data Sheet - Rev 2.1
12/2003
9
ACD2202
Figure 17: Typical Conversion Gain and Noise
Figure vs. LNA/Mixer Current Control Resistor R1
(TA = +25 °C, VDD = +5 V, fLO2 = 1042 MHz)
15
5.0
Conversion Gain
200
180
13
4.2
12
3.8
11
3.4
10
Current (mA)
4.6
Noise Figure
N o is e F ig u re (d B )
14
C o n v e rs io n G a in (d B )
Figure 18: Typical Total Current Consumption
vs. LNA/Mixer Current Control Resistor R1
(TA = +25 °C, VDD = +5 V)
5
10
15
20
140
120
100
3.0
0
160
80
25
0
5
10
Figure 19: Typical Input IP3
vs. LNA/Mixer Current Control Resistor R1
(TA = +25 °C, VDD = +5 V)
25
-50
Cross Modulation (dBc)
17
IIP3 (dBm)
20
Figure 20: Typical Cross Modulation
vs. LNA/Mixer Current Control Resistor R1
(TA = +25 °C, VDD = +5 V)
19
15
13
11
9
0
5
10
15
20
25
-55
-60
-65
0
R1 Resistor Value ( )
10
15
R1 Resistor Value ( )
R1 Resistor Value ( )
5
10
R1 Resistor Value ( )
Data Sheet - Rev 2.1
12/2003
15
20
ACD2202
LOGIC PROGRAMMING
Synthesizer Register Programming
The ACD2202 includes two PLL synthesizers. Each
synthesizer contains programmable Reference and
Main dividers, which allow a wide range of local
oscillator frequencies. The 22-bit registers that control
the dividers are programmed via a shared three-wire
bus, consisting of Data, Clock and Enable lines.
Table 7: Register Select Bits
S E LE C T
BITS
The data word for each register is entered serially
in order with the most significant bit (MSB) first and
the least significant bit (LSB) last. The rising edge
of the Clock pulse shifts each data value into the
register. The Enable line must be low for the duration
of the data entry, then set high to latch the data into
the register. (See Figure 4.)
S
1
0
0
Reference Divider Register for PLL2
0
1
Main Divider Register for PLL2
1
0
Reference Divider Register for PLL1
1
1
Main Divider Register for PLL1
Table 8: Reference Divider Registers
MSB
21 20
19
18
17
16
15
Program Mode
D
5
S
2
Reference Divider Programming
The reference divider register for each synthesizer
consists of fifteen divider bits, five program mode
bits and the two register select bits, as shown in
Table 8. The fifteen divider bits allow a divide ratio
from 3 to 32767, inclusive, as shown in Table 9.
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table 7 indicates the register select bit settings used
to program each of the available registers.
22
DESTINATION REGISTER FOR
SERIAL DATA
D
4
D
3
D
2
14
13
12
11
10
9
8
LSB
7
6
5
4
3
Reference Divider Divide Ratio, R
D
1
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
2
1
Select
R
4
R
3
R
2
R
1
S
2
S
1
Table 9: Reference Divider R Counter Bits
DIVIDE
RATIO R
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes:
Divide ratios less than 3 are prohibited.
Data Sheet - Rev 2.1
12/2003
11
ACD2202
Main Divider Programming
The main divider register for each synthesizer
consists of seven A counter bits, eleven B counter
bits, two program mode bits and the two register
select bits, as shown in Table 10. The main divider
divide ratio, N, is determined by the values in the A
and B counters. The eleven B Counter bits and
allowed values are shown in Table 11, and the seven
A Counter bits and allowed values are shown in
21
20
19
18
17
Program
Mode
C
2
Pulse Swallow Function
The VCO output frequency for the local oscillator is
computed using the following equation; the
variables are defined in Table 13:
fVCO = N x fOSC/R, where N = [(P x B) + A]
Table 10: Main Divider Registers
MSB
22
Table 12. Note that there are some limitations on
the ranges of the values for each counter.
C
1
16
15
14
13
12
11
10
9
LSB
8
7
B Counter
B
11
B
10
B
9
B
8
B
7
B
6
6
5
4
3
A Counter
B
5
B
4
B
3
B
2
B
1
A
7
A
6
A
5
A
4
A
3
2
1
Select
A
2
A
1
S
2
S
1
Table 11: Main Divider B Counter Bits
VALUE OF B
COUNTER
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
-
-
-
-
-
-
-
-
-
-
-
-
2047
1
1
1
1
1
1
1
1
1
1
1
Notes:
B > A, Divide ratios less than 3 are prohibited.
Table 13: Variable Definitions
Table 12: Main Divider A Counter Bits
VALUE OF A
COUNTER
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
-
-
-
-
-
-
127
1
1
1
1
1
Notes:
B > A, A < P
12
VAR
DEFINITION
fVCO
Desired output frequency of external
voltage controlled oscillator (VCO)
1
B
Divide ratio of B counter (3 to 2047)
-
-
A
Divide ratio of A counter (0 < A < P, A < B)
1
1
fOSC
Frequency of external reference crystal or
oscillator
R
Divide ratio of R counter (3 to 32767)
P
Preset modulus of prescalar (P = 64)
Data Sheet - Rev 2.1
12/2003
ACD2202
Programmable Modes
Each register contains bits set aside for
programming different modes of operation in the
synthesizers. Currently, the only programmable
mode is the polarity of the phase detector in each of
the synthesizers. Bit D1 in each reference divider
register controls this feature. Bits D2 through D5 in
the reference divider registers and bits C1 and C2
in the main divider registers are reserved for future
use, and have no current function. They can be set
either high or low without affecting synthesizer
performance.
Setting Phase Detector Polarity
Table 14 shows how bit D1 of each reference divider
register controls the polarity of the phase detector
associated with each PLL. The correct setting is
determined by using Table 15 and Figure 21.
Figure 21: VCO Characteristics
Table 14: Phase Detector Polarity Bit
S
2
S
1
D
1
0
0
PLL2 Phase Detector Polarity
1
0
PLL1 Phase Detector Polarity
(1)
Table 15: Phase Detector Polarity Selection
D
1
PHASE
DETECTOR
POLARITY
VC O
CHARACTERISTICS
(SEE FIGURE 12)
0
Negative
curve (2)
1
Positive
curve (1)
VCO OUTPUT
FREQUENCY
(2)
VCO INPUT VOLTAGE
Synthesizer Programming Example
The following example for programming the two synthesizers in the ACD2202 details the calculations
used to determine the required value of each bit in all four registers:
Requirements
Desired CATV input channel: “HHH” - 499.25 MHz picture carrier (501 MHz digital channel center frequency)
(Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency)
First IF frequency: 1087.75 MHz
Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz
Phase detector comparison frequency for up converter: 250 KHz
Crystal reference oscillator frequency: 4 MHz
Calculation of Reference Divider Values
The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired
phase detector comparison frequency:
R = fOSC / fPD
For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison
frequency are used to yield RPLL2 = 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter
R counter are RPLL2 = 000000001000000.
Data Sheet - Rev 2.1
12/2003
13
ACD2202
For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison
frequency are used to yield RPLL1 = 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter
are RPLL1 = 000000000010000.
Calculation of Main Divider Values
The values for the A and B counters are determined by the desired VCO output frequency for the local
oscillator and the phase detector comparison frequency:
N = fVCO / f PD
B = trunc(N / P)
A = N - (B x P)
The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example.
The main divider ratio for the down converter, then, is NPLL2 = 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the
ACD2202, BPLL2 = trunc(16672 / 64) = 260, and APLL2 = 16672 - (260 x 64) = 32. These results give bit values
of BPLL2 = 00100000100 and APLL2 = 0100000 for the B and A counters.
The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example.
Therefore, NPLL1 = 1587 MHz / 250 KHz = 6348, BPLL1 = trunc(6348 / 64) = 99, and APLL1 = 6348 - (99 x 64) = 12.
These results give bit values of BPLL1 = 00001100011 and APLL1 = 0001100 for the B and A counters.
Phase Detector Polarity
Assuming the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be
negative, and D1PLL1 = 1. If the VCO for the down converter has a positive slope, the phase detector polarity for
PLL2 should be positive, and D1PLL2 = 0.
In summary, for this example, the four register programming words are shown in Tables 16 and 17:
Table 16: PLL1 and PLL2 Reference Divider Register Bits
for Synthesizer Programming Example
MSB
22
21 20
19
18
17
16
15
14
13
Program Mode
12
11
10
9
8
7
6
LSB
5
4
3
Reference Divider R Counter
2
1
Select
D
5
D
4
D
3
D
2
D
1
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
S
2
S
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
Table 17: PLL1 and PLL2 Main Divider Register Bits
for Synthesizer Programming Example
MSB
22
21
20
19
18
Program
Mode
14
17
16
15
14
13
12
11
10
9
Main Divider B Counter
8
7
LSB
6
5
4
3
Main Divider A Counter
2
1
Select
C
2
C
1
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
A
7
A
6
A
5
A
4
A
3
A
2
A
1
S
2
S
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
Data Sheet - Rev 2.1
12/2003
ACD2202
APPLICATION INFORMATION
VSYN
VSYN
20 k
pins
17,18
pins
16,19
AV~ -1000
VSS
VSS
VSYN
pin 13
pin 1
200 pin 2
VSS
VSYN
300 k
5 k
pin 14
pin 4
5 k
GND
GND
VSS
VSUP
pin 27
10 pin 24
pin 5
5 pF
15 5
GND
pin 28
5 pF
5
GND
10 pF
OSCGND
Figure 22: Equivalent Circuits
Data Sheet - Rev 2.1
12/2003
15
ACD2202
Figure 23: PC Board Layout Top View
Figure 24: PC Board Layout Mid View
RF
RF
AFC
Out
ACD2202
4M Hz Xtal
J1
1
Figure 25: PC Board Layout Bottom View
Figure 26 Evaluation Fixture
Table 18: J1 Header Pinout
Table 19: Fixture Pinout
LO
In
FUNCTION
PIN
FU N C TION
1
Clock
RF
D ownconverter RF Input
2
Data
RF
D ownconverter RF Input
3
Ground
IF
IF Output (Si ngle Ended)
4
Enable
AFC Out
To Upconverter Osci llator
Tuni ng C i rcui t
5
+5 V DC
LO In
Synthesi zer RFU LO Input
6
+30 V DC
PIN
16
IF
Balun
Data Sheet - Rev 2.1
12/2003
Data Sheet - Rev 2.1
12/2003
1
2
3
4
5
6
J1
C4
+30V
C5
R5
C6
R2
+5V
C7
R6
R3
C8
X1
R7
R4
L1
D1
RF
RF
R1
C1
C3
C2
+5V
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C12
REFOUT
REFIN
CLK
DATA
EN
VSS
VSS
OSCGND
OSCGND
TCKT
ISET
GND
RFIN-
RFIN+
R8
C11
ACD2202
VSUP
C10
VSYN
RFU
CPU
CPD
RFD
VSS
VSS
GND
GND
OSC OUT
L2
27
28
C9
15
16
17
18
19
20
21
22
23
24
25
GND 26
VIF + IFOUT-
VIF + IFOUT+
C24
L3
C21
DT1
C13
R9
C20
IF
C14
R10
R12
C17
C22
R11
C16
C23
C15
Q1
LOIN
AFCOUT
+5V
R13
C18
C19
+30V
ACD2202
Figure 27: Evaluation Fixture Schematic
17
ACD2202
Table 20: Evaluation Fixture Parts List
ITEM #
VALUE
SIZE
DESCRIPTION
PART #
QTY
VENDOR
C 1, C 2,
C 20
100pF
0603
Chip-capacitor
GRM39COG101J50V
3
Murata
C3
9pF
0603
Chip-capacitor
GRM39COG090C50V
1
Murata
C 7, C 8
30pF
0603
Chip-capacitor
GRM39COG300J50V
2
Murata
C 12
220uF
PCE2040CT-ND
1
DIGI-KEY
10V VA Capacitor
Series
C9, C11,
C 14, C 21,
C 22
.1uF
0603
Chip-capacitor
GRM39Y5V104Z16V
5
Murata
C 10, C 23
1000pF
0603
Chip-capacitor
GRM39X7R102K50V
2
Murata
C 15, C 17
4700pF
0603
Chip-capacitor
GRM39X7R472K25V
2
Murata
C 16
1uF
0603
Radial-lead
Chip-capacitor
RPE113-X7R-105-K-050
1
Murata
C 18
.01uF
0603
Chip-capacitor
GRM39X7R103K25V
1
Murata
C 19
10uF
35 V
TANT
TE Series Cap. PCS6106CT-ND
1
DIGI-KEY
C 24
15pF
0603
Chip-capacitor
GRM39COG150J50V
1
Murata
C 13
5600pF
0603
Chip-capacitor
GRM39X7R562K50V
1
Murata
33pF
0603
Chip-capacitor
GRM39COG330J50V
3
Murata
R8
51
0603
Chip Resistor
ERJ-3GSYJ510
1
Panasonic
R5
10K
0603
Chip Resistor
ERJ-3GSYJ103
1
Panasonic
R2, R3, R4
2K
0603
Chip Resistor
ERJ-3GSYJ202
3
Panasonic
R12
1K
0603
Chip Resistor
ERJ-3GSYJ102
1
Panasonic
R11
2.7K
0603
Chip Resistor
ERJ-3GSYJ272
1
Panasonic
R7
3K
0603
Chip Resistor
ERJ-3GSYJ302
1
Panasonic
R13
22K
0603
Chip Resistor
ERJ-3GSYJ223
1
Panasonic
R10
8.2K
0603
Chip Resistor
ERJ-3GSYJ822
1
Panasonic
R1
10
0603
Chip Resistor
ERJ-3GSYJ100
1
Panasonic
C 4, C 5,
C6
18
Data Sheet - Rev 2.1
12/2003
ACD2202
Table 20: Evaluation Fixture Parts List continued
ITEM #
VALUE
SIZE
DESCRIPTION
PART #
QTY
VENDOR
R6, R9
0
0603
Chip Resistor
ZC0603
2
RCD
L1
5.6nH
0805
Inductor
0805CS-050X-BC
1
Coilcraft
L2
68nH
0805
Inductor
0805CS-680X-BC
1
Coilcraft
L3
270nH
0805
Inductor
0805CS-271X-BC
1
Coilcraft
D1
1S V 245
Varactor diode
1SV245
1
Toshiba
DT1
4:1
Transformer
ETC4-1-2
1
M/A-COM, Inc.
North America
Q1
30V
SMD
Transistor NPN
Darl.
FMMTA13CT-ND
1
DIGI-KEY
X1
4MHZ
Crystal
SE2618CT-ND
1
DIGI-KEY
SOT-23
Data Sheet - Rev 2.1
12/2003
19
ACD2202
PACKAGE OUTLINE
Figure 28: S8 Package Outline - 28 Pin SSOP
20
Data Sheet - Rev 2.1
12/2003
ACD2202
NOTES
Data Sheet - Rev 2.1
12/2003
21
ACD2202
NOTES
22
Data Sheet - Rev 2.1
12/2003
ACD2202
NOTES
Data Sheet - Rev 2.1
12/2003
23
ACD2202
ORDERING INFORMATION
ORDER NUMBER
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
A C D 2202S 8P 1
-40°C to +85°C
28 Pin SSOP
Tape & Reel, 3500 pieces per reel
A C D 2202S 8P 0
-40°C to +85°C
28 Pin SSOP
Tubes, 50 pieces per tube
COMPONENT PACKAGING
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: [email protected]
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
24
Data Sheet - Rev 2.1
12/2003