ACPL-782T
Automotive Isolation Amplifier
with R2Coupler™ Isolation
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-782T isolation amplifier was designed for
voltage and current sensing in electronic motor drives
and battery system monitoring. In a typical implementation, and motor currents flow through an external resistor
and the resulting analog voltage drop is sensed by the
ACPL-782T. A differential output voltage is created on the
other side of the ACPL-782T optical isolation barrier. This
differential output voltage is proportional to the motor
current and can be converted to a single-ended signal
by using an op-amp as shown in the recommended application circuit. Since common-mode voltage swings
of several hundred volts in tens of nanoseconds are
common in modern switching inverter motor drives, the
ACPL-782T was designed to ignore very high commonmode transient slew rates (of at least 10 kV/Ps).
x
x
x
x
x
x
x
x
The high CMR capability of the ACPL-782T isolation
amplifier provides the precision and stability needed to accurately monitor motor current and DC rail voltage in high
noise motor control environments, providing for smoother
control (less“torque ripple”) in various types of motor control
applications.
The product can also be used for general analog signal
isolation applications requiring high accuracy, stability,
and linearity under similarly severe noise conditions. The
ACPL-782T utilizes sigma delta (6') analog-to-digital
converter technology, chopper stabilized amplifiers, and
a fully differential circuit topology.
Together, these features deliver unequaled isolationmode noise rejection, as well as excellent offset and
gain accuracy and stability over time and temperature.
This performance is delivered in a compact, auto-insertable, industry standard 8-pin DIP package that meets
worldwide regulatory safety standards. (A gull-wing
surface mount option -300E is also available).
Avago R2Coupler isolation products provide the reinforced insulation and reliability needed for critical in automotive and high temperature industrial applications.
x
x
x
x
±2% Gain Tolerance @ 25°C
15 kV/Ps Common-Mode Rejection at VCM = 1000V
30ppm/°C Gain Drift vs. Temperature
0.3 mV Input Offset Voltage
100 kHz Bandwidth
0.004% Nonlinearity
Compact, Auto-Insertable Standard 8-pin DIP Package
Worldwide Safety Approval:
– UL 1577 (3750 VRMS/1 min.) and
– CSA
– IEC 60747-5-5, DIN EN 60747-5-2(VDE 0884 Teil 2)
Qualified to AEC-Q100 Test Guidelines
Automotive Operating Temperature -40 to 125°C
Advanced Sigma-Delta (6') A/D Converter Technology
Fully Differential Circuit Topology
Applications
x Automotive Motor Inverter Current/Voltage Sensing
x Automotive AC/DC and DC/DC converter Current/
Voltage sensing
x Automotive Battery ECU
x Automotive Motor Phase Current Sensing
x Isolation Interface for Temperature Sensing
x General Purpose Current Sensing and Monitoring
Functional Diagram
VDD1 1
IDD1
IDD2
8 VDD2
VIN+ 2
+
+
7 VOUT+
VIN- 3
-
-
6 VOUT-
GND1 4
SHIELD
5 GND2
The connection of a 0.1 PF bypass capacitor between
pins 1 and 4, pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Part Number
Option
(RoHS Compliant)
Package
Surface Mount
Gullwing
300mil DIP-8
X
X
X
X
Tape & Reel
-000E
ACPL-782T
-300E
-500E
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example:
ACPL-782T-500E to order product of gullwing SMT DIP-8 package in Tape and Reel packaging with RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
ACPL-782T-000E Standard DIP Package
9.80 ± 0.25
(0.386 ± 0.010)
8
1
1.19 (0.047) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
7
2
6
Dimensions in millimeters and (inches).
5
A 782T
DATE CODE
YYWW
EE
EXTENDED DATE CODE
3
Note:
Floating lead protrusion is 0.5 mm (20 mils) max.
4
7.62 ± 0.25
(0.300 ± 0.010)
1.78 (0.070) MAX.
6.35 ± 0.25
(0.250 ± 0.010)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
2
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
5° TYP.
0.20 (0.008)
0.33 (0.013)
Gull Wing Surface Mount Option 300E and 500E
LAND PATTERN RECOMMENDATION
9.80 ± 0.25
(0.386 ± 0.010)
8
6
7
1.016 (0.040)
5
A 782T
6.350 ± 0.25
(0.250 ± 0.010)
YYWW
EE
1
2
3
10.9 (0.430)
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
0.20 (0.008)
0.33 (0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
2.54
(0.100)
BSC
0.635 ± 0.130
(0.025 ± 0.005)
12° NOM.
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
Dimensions in millimeters (inches).
Tolerances (unless otherwise specified): xx.xx = 0.01
xx.xxx = 0.005
Note: Floating lead protrusion is 0.5 mm (20 mils) max.
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-782T-000E is approved by the following organizations:
UL
IEC/DIN
UL 1577, component recognition program up to VISO =
3750 VRMS
IEC 60747-5-5
DIN EN 60747-5-2(VDE 0884 Teil 2)
CSA
Approved under CSA Component AcceptanceNotice #5,
File CA 88324.
3
IEC 60747-5-5, DIN EN 60747-5-2(VDE 0884 Teil 2) Insulation Characteristics
Description
Symbol
Characteristic
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage 300 Vrms
for rated mains voltage 450 Vrms
for rated mains voltage 600 Vrms
I-IV
I-III
I-II
Climatic Classification
55/125/21
Pollution Degree (DIN VDE 0110/1.89)
2
Unit
Maximum Working Insulation Voltage
VIORM
891
VPEAK
Input to Output Test Voltage, Method b[2] VIORM x 1.875 = VPR,
100% Production Test with tm = 1 sec, Partial discharge < 5 pC
VPR
1670
VPEAK
Input to Output Test Voltage, Method a[2] VIORM x 1.6 = VPR,
Type and Sample Test, tm = 60 sec, Partial discharge < 5 pC
VPR
1426
VPEAK
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
6000
VPEAK
Safety-limiting values—maximum values allowed in the event of a failure.
Case Temperature
Input Current[3]
Output Power[3]
TS
IS,INPUT
PS,OUTPUT
175
400
600
°C
mA
mW
Insulation Resistance at TS , VIO = 500 V
RS
>109
:
Notes:
1. Insulation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits within the
application. Surface Mount Classification is Class A in accordance with CECC00802.
2. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC
60747-5-5/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles.
3. Refer to the following figure for dependence of PS and IS on ambient temperature.
OUTPUT POWER - PS, INPUT CURRENT - IS
800
4
PS (mW)
IS (mA)
700
600
500
400
300
200
100
0
0
25
50
75
100 125 150
TA - CASE TEMPERATURE - °C
175
200
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External
Air Gap (Clearance)
L(101)
7.4
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External
Tracking (Creepage)
L(102)
8.0
mm
Measured from input terminals to output terminals,
shortest distance path along body.
0.5
mm
Through insulation distance conductor to conductor,
usually the straight line distance thickness between
the emitter and detector.
>175
Volts
DIN IEC 112/VDE 0303 Part 1
Minimum Internal
Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative
Tracking Index)
CTI
Isolation Group
(DIN VDE0109)
IIIa
Material Group (DIN VDE 0110)
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
130
°C
Operating Temperature
TA
-40
125
°C
Supply Voltage
VDD1, VDD2
0
5.5
Volts
Steady-state Input Voltage
VIN+, VIN-
-2.0
VDD1 + 0.5
Volts
2 second Transient Input Voltage
-6.0
Output Voltage
Volts
-0.5
VOUT
Solder Reflow Temperature Profile
VDD2 + 0.5
Volts
See Package Outline Drawings Section
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Ambient Operating Temperature
TA
-40
125
°C
Power Supply Voltage
VDD1, VDD2
4.5
5.5
Volts
Input Voltage (Accurate & Linear)
VIN+, VIN-
-200
200
mV
Input Voltage (Functional)
VIN+, VIN-
-2
2
V
5
Notes
1
DC Electrical Specifications
Unless otherwise noted, all typical and figures are at the nominal operating conditions of VIN+ = 0, VIN- = 0 V, VDD1 = VDD2
= 5 V and TA = 25°C; all Min. /Max. Specifications are within the Recommended Operating Conditions.
Parameter
Symbol
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Input Offset Voltage
VOS
-2.0
0.3
2.0
mV
TA=25°C
1,2
4.0
mV
-40°C < TA < +125°C,
-4.5V < (VDD1, VDD2) < 5.5V
3.0
10.0
PV/°C
8.00
8.16
V/V
-4.0
Magnitude of Input
Offset Change vs.
Temperature
|'VOS/'TA|
Gain
G
Magnitude of VOUT
Gain Change vs.
Temperature
|'G/
G/'TA|
30
VOUT 200 mV
Nonlinearity
NL200
0.0037
Magnitude of VOUT
200mV Nonlinearity
Change vs. Temperature
|'NL200/'T|
0.0002
VOUT 100 mV
Nonlinearity
NL100
0.0027
Maximum Input
Voltage before
VOUT Clipping
|VIN+|MAX
308.0
Input Supply Current
IDD1
10.86
16.0
mA
VIN+ = 400 mV
Output Supply Current
IDD2
11.56
20.0
mA
VIN+ = -400 mV
Input Current
IIN+
Magnitude of Input
Bias Current vs.
Temperature coefficient
7.84
0.35
%
0.2
%
0.45
nA/°C
Output Low Voltage
VOL
1.29
V
Output High Voltage
VOH
3.80
V
Output Common-Mode
Voltage
VOCM
Output Short-Circuit
Current
|IOSC|
18.6
mA
Equivalent Input Impedance
RIN
500
k:
VOUT Output Resistance
ROUT
15
:
Input DC Common-Mode
Rejection Ratio
CMRRIN
76
dB
6
4,5,6
3
4
-200 mV < VIN+ < 200 mV
7,8
-100 mV < VIN+ < 100mV
mV
|'IIN/'T|
2.545
2
5
%/°C
PA
2.2
3
PPM/°C
-0.5
-5
-200 mV < VIN+ < 200 mV,
TA = 25°C,
Note
2.8
6
9
10
7
8
11
9
10
V
11
12
AC Electrical Specifications
Unless otherwise noted, all typicals and figures are at the nominal operating conditions of VIN+ = 0, VIN- = 0 V, VDD1 =
VDD2 = 5 V and TA = 25°C; all Min./Max. specifications are within the Recommended Operating Conditions.
Parameter
Symbol
Min.
Typ.*
VOUT Bandwidth
(-3 dB) sine wave.
BW
50
VOUT Noise
Units
Test Conditions
Fig.
100
kHz
VIN+ = 200mVpk-pk
12,13
NOUT
6
mVRMS
VIN+ = 0.0 V
VIN to VOUT Signal
Delay (50 – 10%)
tPD10
2.03
3.3
Ps
Measured at output of
MC34081on Figure 15.
VIN to VOUT Signal
Delay (50 – 50%)
tPD50
3.47
5.6
Ps
VIN+ = 0 mV to 150mV step.
VIN to VOUT Signal
Delay (50 – 90%)
tPD90
4.99
9.9
Ps
VOUT Rise/ Fall Time
(10 – 90%)
tR/F
2.96
6.6
Ps
Common Mode
Transient Immunity
CMTI
Power Supply
Rejection
PSR
10.0
Max.
Note
13
4,15
15.0
kV/Ps
VCM = 1 kV, TA = 25°C
16
14
170
mVRMS
With recommended
application circuit.
Units
Test Conditions
VRMS
RH < 50%,
t = 1 min. TA = 25°C
16,17
15
Package Characteristics
Parameter
Symbol
Min.
Input-Output
Momentary Withstand
Voltage
VISO
3750
Resistance
(Input-Output)
RI-O
>109
:
VI-O = 500 VDC
18
Capacitance
(Input-Output)
CI-O
1.2
pF
ƒ = 1 MHz
18
7
Typ.*
Max.
Fig.
Note
Notes:
General Note: Typical values represent the mean value of all
characterization units at the nominal operating conditions. Typical drift
specifications are determined by calculating the rate of change of the
specified parameter versus the drift parameter (at nominal operating
conditions) for each characterization unit, and then averaging the
individual unit rates. The corresponding drift figures are normalized to
the nominal operating conditions and show how much drift occurs as
the par-ticular drift parameter is varied from its nominal value, with all
other parameters held at their nominal operating values. Note that the
typical drift specifications in the tables below may differ from the slopes
of the mean curves shown in the corresponding figures.
1. Avago Technologies recommends operation with VIN- = 0 V (tied to
GND1). Limiting VIN+ to 100 mV will improve DC nonlinearity and
nonlinearity drift. If VIN- is brought above VDD1 – 2 V, an internal test
mode may be activated. This test mode is for testing LED coupling
and is not intended for customer use.
2. This is the Absolute Value of Input Offset Change vs. Temperature.
3. Gain is defined as the slope of the best-fit line of differential output
voltage (VOUT+–VOUT-) vs. differential input voltage (VIN+–VIN-) over
the specified input range.
4. This is the Absolute Value of Gain Change vs. Temperature in PPM
level.
5. Nonlinearity is defined as half of the peak-to-peak output deviation
from the best-fit gain line, expressed as a percentage of the full-scale
differential output voltage.
6. NL100 is the nonlinearity specified over an input voltage range of
±100 mV.
7. The input supply current decreases as the differential input voltage
(VIN+–VIN-) decreases.
8. The maximum specified output supply current occurs when the
differential input voltage (VIN+–VIN-) = -200 mV, the maximum
recommended operating input voltage. However, the output supply
current will continue to rise for differential input voltages up to
approximately -300 mV, beyond which the output supply current
remains constant.
9. Because of the switched-capacitor nature of the input sigma-delta
converter, time-averaged values are shown.
10. When the differential input signal exceeds approximately 308 mV,
the outputs will limit at the typical values shown.
11. Short circuit current is the amount of output current generated when
either output is shorted to VDD2 or ground.
8
12. CMRR is defined as the ratio of the differential signal gain (signal
applied differentially between pins 2 and 3) to the common-mode
gain (input pins tied together and the signal applied to both inputs
at the same time), expressed in dB.
13. Output noise comes from two primary sources: chopper noise and
sigma-delta quantization noise. Chopper noise results from chopper
stabilization of the output op-amps. It occurs at a specific frequency
(typically 400 kHz at room temperature), and is not attenuated by
the internal output filter. A filter circuit can be easily added to the
external post-amplifier to reduce the total RMS output noise. The
internal output filter does eliminate most, but not all, of the sigmadelta quantization noise. The magnitude of the output quantization
noise is very small at lower frequencies (below 10kHz) and increases
with increasing frequency.
14. CMTI (Common Mode Transient Immunity or CMR, Common Mode
Rejection) is tested by applying an exponentially rising/falling
voltage step on pin 4 (GND1) with respect to pin 5 (GND2). The
rise time of the test waveform is set to approximately 50 ns. The
amplitude of the step is adjusted until the differential output (VOUT+–
VOUT-) exhibits more than a 200 mV deviation from the average
output voltage for more than 1Ps. The ACPL-782T will continue to
function if more than 10 kV/Ps common mode slopes are applied, as
long as the breakdown voltage limitations are observed.
15. Datasheet value is the differential amplitude of the transient at the
output of the ACPL-782T when a 1 Vpk-pk, 1 MHz square wave with 40
ns rise and fall times is applied to both VDD1 and VDD2.
16. In accordance with UL 1577, each optocoupler is proof tested by
applying an insulation test voltage ≥4500 VRMS for 1 second (leakage
detection current limit, II-O ≤ 5 PA). This test is performed before the
100% production test for partial discharge (method b) shown in IEC
60747-5-5/DIN EN 60747-5-2 Insulation Characteristic Table.
17. The Input-Output Momentary Withstand Voltage is a dielectric
voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refers to
the IEC 60747-5-5/DIN EN 60747-5-2 insulation characteristics table
and your equipment level safety specification.
18. This is a two-terminal measurement: pins 1–4 are shorted together
and pins 5–8 are shorted together.
VDD1
VDD2
+15 V
0.1 PF
1
8
0.1 PF
2
10 K
7
+
ACPL-782T
0.1 PF
3
6
4
5
VOUT
10 K
-
0.47
PF
AD624CD
GAIN = 100
0.1 PF
0.47
PF
-15 V
Figure 1. Input Offset Voltage Test Circuit.
0.39
VOS - INPUT OFFSET VOLTAGE - mV
VOS - INPUT OFFSET VOLTAGE - mV
0.8
0.7
0.6
0.5
0.4
0.3
0.2
-55
35
5
65
TA - TEMPERATURE - °C
-25
95
125
8.035
G - GAIN - V/V
8.03
8.025
8.02
8.015
-55
-35
-15
5
25
45 65
TA - TEMPERATURE - °C
Figure 4. Gain vs. Temperature.
9
vs. VDD2
0.37
0.36
0.35
0.34
0.33
4.5
4.75
5.25
5.0
VDD - SUPPLY VOLTAGE - V
Figure 3. Input Offset Voltage vs. Supply.
Figure 2. Input Offset Voltage vs. Temperature.
8.01
vs. VDD1
0.38
85
105 125
5.5
VDD2
VDD1
+15 V
+15 V
0.1 PF
1
8
0.1 PF
404
VIN
0.1 PF
0.1 PF
2
7
10 K
+
ACPL-782T
13.2
3
6
4
5
+
VOUT
10 K
-
0.01 PF
0.47
PF
-
AD624CD
GAIN = 4
AD624CD
GAIN = 10
0.1 PF
0.47
PF
0.1 PF
-15 V
-15 V
10 K
0.47
PF
Figure 5. Gain and Nonlinearity Test Circuit.
0.03
8.032
0.025
NL - NONLINEARITY - %
G - GAIN - V/V
8.03
8.028
8.026
vs. VDD1
4.5
4.75
5.0
5.25
VDD - SUPPLY VOLTAGE - V
0.01
0
-55
5.5
Figure 6. Gain vs. Supply.
-25
95
125
VO - OUTPUT VOLTAGE - V
4.2
0.004
0.003
vs. VDD1
3.4
2.6
1.8
VOP
VOR
vs. VDD2
0.002
4.5
4.75
5.0
5.25
VDD - SUPPLY VOLTAGE - V
Figure 8. Nonlinearity vs. Supply.
10
5
65
35
TA - TEMPERATURE - °C
Figure 7. Nonlinearity vs. Temperature.
0.005
NL - NONLINEARITY - %
0.015
0.005
vs. VDD2
8.024
0.02
5.5
1.0
-0.5
-0.3
-0.1
0.1
VIN - INPUT VOLTAGE - V
Figure 9. Output Voltage vs. Input Voltage.
0.3
0.5
0
IIN - INPUT CURRENT - PA
IDD - SUPPLY CURRENT - mA
13
10
7
IDD1
IDD2
4
-0.5
-0.1
0.1
VIN - INPUT VOLTAGE - V
0.3
0.5
-4
-0.4
0
-0.2
0.2
VIN - INPUT VOLTAGE - V
0.4
Figure 11. Input Current vs. Input Voltage.
50
0
PHASE - DEGREES
0
GAIN - dB
-3
-0.6
1
-1
-2
-3
-50
-100
-150
-200
-250
-300
-4
10
1000
10000
FREQUENCY (Hz)
100
100000
10
Figure 12. Gain vs. Frequency.
4.7
Tpd 10
Tpd 50
Tpd 90
Trise
3.9
3.1
2.3
1.5
-55
-25
100
Figure 13. Phase vs. Frequency.
5.5
PD - PROPAGATION DELAY - PS
-2
-5
-0.3
Figure 10. Supply Current vs. Input Voltage.
35
5
65
TA - TEMPERATURE - °C
Figure 14. Propagation Delay vs. Temperature.
11
-1
95
125
10000
1000
FREQUENCY (Hz)
100000
0.6
10 K
VDD2
VDD1
+15 V
0.1 PF
1
0.1 PF
8
0.1 PF
2
VIN
2K
7
ACPL-782T
0.01 PF
3
6
4
5
VOUT
2K
+
MC34081
0.1 PF
10 K
-15 V
VIN IMPEDANCE LESS THAN 10 W.
Figure 15. Propagation Delay Test Circuits.
10 K
150 pF
VDD2
78L05
+15 V
IN OUT
0.1
PF
0.1
PF
1
0.1 PF
8
0.1 PF
2
2K
7
ACPL-782T
9V
3
6
4
5
VCM
Figure 16. CMTI Test Circuits.
12
VOUT
+
MC34081
0.1 PF
10 K
150
pF
PULSE GEN.
+
2K
-15 V
Application Information
Power Supplies and Bypassing
The recommended supply connections are shown in
Figure 17. A floating power supply (which in many
applications could be the same supply that is used to drive
the high-side power transistor) is regulated to 5 V using a
simple zener diode (D1); the value of resistor R4 should
be chosen to supply sufficient current from the existing
floating supply. The voltage from the current sensing
resistor (Rsense) is applied to the input of the ACPL-782T
through an RC anti-aliasing filter (R2 and C2). Although the
application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance.
An inexpensive 78L05 three-terminal regulator can also
be used to reduce the floating supply voltage to 5 V. To
help attenuate high-frequency power supply noise or
ripple, a resistor or inductor can be used in series with the
input of the regulator to form a low-pass filter with the
regulator’s input bypass capacitor.
As shown in Figure 18, 0.1 PF bypass capacitors (C1, C2)
should be located as close as possible to the pins of the
ACPL-782T. The bypass capacitors are required because
of the high-speed digital nature of the signals inside the
ACPL-782T. A 0.01μF bypass capacitor (C2) is also recommended at the input due to the switched-capacitor
nature of the input circuit. The input bypass capacitor
also forms part of the anti-aliasing filter, which is recommended to prevent high-frequency noise from aliasing
down to lower frequencies and interfering with the
input signal. The input filter also performs an important
reliability function—it reduces transient spikes from ESD
events flowing through the current sensing resistor.
The power supply for the ACPL -782T is most often obtained
from the same supply used to power the power transistor gate drive circuit. If a dedicated supply is required, in
many cases it is possible to add an additional winding on
an existing transformer. Otherwise, some sort of simple
isolated supply can be used, such as a line powered transformer or a high-frequency DC-DC converter.
+
HV+
GATE DRIVE
CIRCUIT
FLOATING
POWER
SUPPLY
***
-
D1
5.1 V
C1
0.1 μF
R2
39 :
MOTOR
***
+ R1 RSENSE
***
HV-
Figure 17. Recommended Supply and Sense Resistor Connections.
13
C2
0.01 μF
ACPL-782T
POSITIVE
FLOATING
SUPPLY
HV+
C5
150 pF
GATE DRIVE
CIRCUIT
R3
***
10.0 K
U1
78L05
IN
+5 V
C1
C2
0.1
μF
0.1
μF
R5
68
***
+
-
1
8
C8
0.1 μF
2
7
C4
0.1 μF
C3
0.01
μF
MOTOR
+15 V
OUT
U2
3
R1
-
2.00 K
U3
+ MC34081
R2
6
2.00 K
4
C7
5
C6
150 pF
RSENSE
ACPL-782T
R4
10.0 K
0.1 μF
-15 V
***
HV-
Figure 18. Recommended Application Circuit.
PC Board Layout
The design of the printed circuit board (PCB) should follow
good layout practices, such as keeping bypass capacitors
close to the supply pins, keeping output signals away from
input signals, the use of ground and power planes, etc. In
addition, the layout of the PCB can also affect the isolation
transient immunity (CMTI) of the ACPL-782T, due primarily
to stray capacitive coupling between the input and the
output circuits. To obtain optimal CMTI performance, the
layout of the PC board should minimize any stray coupling
by maintaining the maximum possible distance between
the input and output sides of the circuit and ensuring that
any ground or power plane on the PC board does not pass
directly below or extend much wider than the body of the
ACPL-782T.
14
C2
R5
C4
C3
TO VDD1
TO RSENSE+
TO RSENSEFigure 19. Example Printed Circuit Board Layout.
TO VDD2
VOUT+
VOUT-
VOUT
Current Sensing Resistors
The current sensing resistor should have low resistance (to
minimize power dissipation), low inductance (to minimize
di/dt induced voltage spikes which could adversely
affect operation), and reasonable tolerance (to maintain
overall circuit accuracy). Choosing a particular value for
the resistor is usually a compromise between minimizing power dissipation and maximizing accuracy. Smaller
sense resistance decreases power dissipation, while larger
sense resistance can improve circuit accuracy by utilizing
the full input range of the ACPL -782T.
The first step in selecting a sense resistor is determining
how much current the resistor will be sensing. The graph in
Figure 20 shows the RMS current in each phase of a threephase induction motor as a function of average motor
output power (in horsepower, hp) and motor drive supply
voltage. The maximum value of the sense resistor is determined by the current being measured and the maximum
recommended input voltage of the isolation amplifier. The
maximum sense resistance can be calculated by taking
the maximum recommended input voltage and dividing
by the peak current that the sense resistor should see
during normal operation. For example, if a motor will have
a maximum RMS current of 10 A and can experience up
to 50% overloads during normal operation, then the peak
current is 21.1 A (=10 x 1.414 x 1.5). Assuming a maximum
input voltage of 200 mV, the maximum value of sense resistance in this case would be about 10 m:.
The maximum average power dissipation in the sense
resistor can also be easily calculated by multiplying the
sense resistance times the square of the maximum RMS
current, which is about 1 W in the previous example. If the
power dissipation in the sense resistor is too high, the resistance can be decreased below the maximum value to
decrease power dissipation. The minimum value of the
sense resistor is limited by precision and accuracy require-
MOTOR OUTPUT POWER - HORSEPOWER
40
440 V
380 V
220 V
120 V
35
30
25
20
15
10
5
0
0
5
20
10
25
15
MOTOR PHASE CURRENT - A (rms)
30
35
Figure 20. Motor Output Horsepower vs. Motor Phase Current and Supply
Voltage.
15
ments of the design. As the resistance value is reduced,
the output voltage across the resistor is also reduced,
which means that the offset and noise, which are fixed,
become a larger percentage of the signal amplitude. The
selected value of the sense resistor will fall somewhere
between the minimum and maximum values, depending
on the particular requirements of a specific design.
When sensing currents large enough to cause significant
heating of the sense resistor, the temperature coefficient
(tempco) of the resistor can introduce nonlinearity due to
the signal dependent temperature rise of the resistor. The
effect increases as the resistor-to-ambient thermal resistance increases. This effect can be minimized by reducing
the thermal resistance of the current sensing resistor or
by using a resistor with a lower tempco. Lowering the
thermal resistance can be accomplished by repositioning the current sensing resistor on the PC board, by using
larger PC board traces to carry away more heat, or by
using a heat sink.
For a two-terminal current sensing resistor, as the value of
resistance decreases, the resistance of the leads become a
significant percentage of the total resistance. This has two
primary effects on resistor accuracy. First, the effective
resistance of the sense resistor can become dependent
on factors such as how long the leads are, how they are
bent, how far they are inserted into the board, and how far
solder wicks up the leads during assembly (these issues
will be discussed in more detail shortly). Second, the leads
are typically made from a material, such as copper, which
has a much higher tempco than the material from which
the resistive element itself is made, resulting in a higher
tempco overall.
Both of these effects are eliminated when a four-terminal
current sensing resistor is used. A four- terminal resistor
has two additional terminals that are Kelvin-connected
directly across the resistive element itself; these two
terminals are used to monitor the voltage across the
resistive element while the other two terminals are used
to carry the load current. Because of the Kelvin connection, any voltage drops across the leads carrying the load
current should have no impact on the measured voltage.
When laying out a PC board for the current sensing resistors,
a couple of points should be kept in mind. The Kelvin connections to the resistor should be brought together under
the body of the resistor and then run very close to each
other to the input of the ACPL-782T; this minimizes the
loop area of the connection and reduces the possibility of
stray magnetic fields from interfering with the measured
signal. If the sense resistor is not located on the same PC
board as the ACPL-782T circuit, a tightly twisted pair of
wires can accomplish the same thing.
supply current to the gate drive power supply in order to
eliminate potential ground loop problems. The only direct
connection between the ACPL-782T circuit and the gate
drive circuit should be the positive power supply line.
Also, multiple layers of the PC board can be used to
increase current carrying capacity. Numerous platedthrough vias should surround each non-Kelvin terminal of
the sense resistor to help distribute the current between
the layers of the PC board. The PC board should use 2 or
4 oz. copper for the layers, resulting in a current carrying
capacity in excess of 20 A.
Output Side
The op-amp used in the external post-amplifier circuit
should be of sufficiently high precision so that it does not
contribute a significant amount of offset or offset drift
relative to the contribution from the isolation amplifier.
Generally, op-amps with bipolar input stages exhibit
better offset performance than op-amps with JFET or
MOSFET input stages.
Note: Please refer to Avago Technologies Application Note 1078 for
additional information on using Isolation Amplifiers.
Sense Resistor Connections
The recommended method for connecting the ACPL-782T
to the current sensing resistor is shown in Figure 18. VIN+
(pin 2 of the APCL-782T) is connected to the positive
terminal of the sense resistor, while VIN- (pin 3) is shorted
to GND1 (pin 4), with the power-supply return path functioning as the sense line to the negative terminal of the
current sense resistor. This allows a single pair of wires
or PC board traces to connect the ACPL-782T circuit to
the sense resistor. By referencing the input circuit to
the negative side of the sense resistor, any load current
induced noise transients on the resistor are seen as a
common-mode signal and will not interfere with the current-sense signal. This is important because the large load
currents flowing through the motor drive, along with the
parasitic inductances inherent in the wiring of the circuit,
can generate both noise spikes and offsets that are relatively large compared to the small voltages that are being
measured across the current sensing resistor.
In addition, the op-amp should also have enough
bandwidth and slew rate so that it does not adversely
affect the response speed of the overall circuit. The postamplifier circuit includes a pair of capacitors (C5 and C6)
that form a single-pole low-pass filter; these capacitors
allow the bandwidth of the post-amp to be adjusted
independently of the gain and are useful for reducing
the output noise from the isolation amplifier. Many
different op-amps could be used in the circuit, including:
TL032A, TL052A, and TLC277 (Texas Instruments), LF412A
(National Semiconductor).
The gain-setting resistors in the post-amp should have a
tolerance of 1% or better to ensure adequate CMRR and
adequate gain tolerance for the overall circuit. Resistor
networks can be used that have much better ratio
tolerances than can be achieved using discrete resistors.
A resistor network also reduces the total number of
components for the circuit as well as the required board
space.
If the same power supply is used both for the gate
drive circuit and for the current sensing circuit, it is
very important that the connection from GND1 of the
ACPL-782T to the sense resistor be the only return path for
150 pF
Note for the Voltage Divider:
V (Line) x [ Rb / (Ra+Rb) ] <= 200 mV
Line 1
+ SUPPLY
78L05
IN
OUT
Ra
0.1 PF
39 :
Rb
10.0 k:
+5 V
+15 V
+5 V
0.1 PF
ACPL-782T
1
8
2
0.01
PF 3
7
4
5
0.1 PF
0.1 PF
2.0 k:
6
2.00 k:
8
6
-
5
+
4
7
0.1 PF
150 pF
10.0 k:
-15 V
Line 2
Figure 21. Recommended circuit for voltage sensing application.
16
TL032A
VOUT
Voltage sensing for DC rail measurement
Dividing error when 1% resistors are used(%)
ACPL-782T is a suitable device to measure the DC rail
voltage over different potentials. In a DC rail voltage
sensing application, the Line1 and Line2 in Figure 21 are
the DC lines to be measured.
Dividing ratio error due to the tolerances of the resistors
From a differential calculation, the error in the voltage
divider of Ra and Rb is expressed as
'A/A = Ra/(Ra + Rb) * ('Rb/Rb – 'Ra/Ra)
(1)
Where A is the ratio of the resistor divider consisting of Ra
and Rb.
Since the errors of the resistors, 'Rb/Rb and 'Ra/Ra are
independent to each other, we need to take absolute
values in equation (1) to know the maximum possible
gain error of the divider and it gives
'A/A = Ra/(Ra + Rb) * ( |'Rb/Rb| + |'Ra/Ra|) (2)
DividerError (%)
2
1.5
1
0.5
0
0.5
0.6
0.7
0.8
Ra/(Ra+Rb)
0.9
1.0
Figure 22: Divider Error % Vs Resistors Divider
Figure 22 is the plot of the equation (2) when the resistors
have 1% tolerance expressing the relationship between
the ratio of Ra to (Ra+Rb) and the possible maximum error
of the dividing ratio.
150 pF
+ SUPPLY
Semitec
EC2F103A2-40113
Thermistor
IGBT attaching type
TH
0.1 PF
R1
78L05
+5 V
IN
OUT
ACPL-782T
0.1 PF 1
8
2
7
3
6
39:
4
R2
5
10.0 k:
+5 V
+15 V
0.1 PF
0.1 PF
2.0 k:
2.0
k:
6
-
8
7
+
5 4
TL032A
1 PF
RL = R1//(R2+R3)
R3
0.1 PF
150 pF
10.0 k:
-15 V
Note on the thermistor and the RL:
Vdd x [RL/(Rth + RL)] x [ R3/(R2 + R3)] <= 200 mV, assuming R2+R3 >> R1
Rth: Resistance of thermistor
RL: Linearizing resistor value = R1//(R2+R3)
Figure 23. Recommended circuit for temperature sensing application.
17
VOUT
Isolated Temperature Sensing using Thermistor
Thermistor is widely used to measure temperatures in
most systems application. A galvanic isolation between
the potential of the Thermistor and that of the analogto-digital is often required when they are mounted in
locations such as high voltage potential, electrically noisy
environments, poorly grounded environments, where
lack of isolation causes either safety or EMI issues.
RL = R1//(R2+R3)=R1(R2+R3)/(R1+R2+R3)
R2 and R3 divides the voltage across RL so that the voltage
fed into ACPL-782T does not exceed +200 mV. The high
impedance characteristic of the input terminals of ACPL782T helps in determining those resistors value since one
can select relatively high resistance of R2 and R3 and R1
can be determined easily.
For product information and a complete list of distributors, please go to our web site:
If R2+R3 >> R1, RL ~ R1
Dividing ratio ~ R3/(R2+R3)
As can be seen from the circuit, one might eliminate R1
and RL~(R2+R3) in this case.
An application example with a Thermistor designed for
measuring IGBT’s surface temperatures is shown in Figure
23. Where TH is the thermistor and the RL is a resistor for
linearization. Suitable RL value is determined from the
Thermistor characteristic and the temperature range to
measure. Please note that the RL value is the compound
value of R1, R2 and R3.
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Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-1565EN - March 23, 2011