AD AD5231BRU50

FEATURES
Nonvolatile Memory1 Preset Maintains Wiper Settings
1024-Position Resolution
Full Monotonic Operation
10 k, 50 k, and 100 k Terminal Resistance
Permanent Memory Write-Protection
Wiper Settings Read Back
Linear Increment/Decrement
Log Taper Increment/Decrement
Push Button Increment/Decrement Compatible
SPI Compatible Serial Interface with Readback Function
3 V to 5 V Single Supply or 2.5 V Dual Supply
28 Bytes User Nonvolatile Memory for Constant Storage
100 Year Typical Data Retention TA = 55C
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
Low Resolution DAC Replacement
GENERAL DESCRIPTION
The AD5231 provides nonvolatile memory digitally controlled
potentiometers2 with 1024-position resolution. These devices
perform the same electronic adjustment function as a mechanical
potentiometer. The AD5231’s versatile programming via a standard 3-wire serial interface allows 16 modes of operation and
adjustment, including scratch pad programming, memory storing and retrieving, increment/decrement, log taper adjustment,
wiper setting read back, and extra user-defined EEMEM.
In the scratch pad programming mode, a specific setting can be
programmed directly to the RDAC2 register, which sets the resistance at terminals W-A and W-B. The RDAC register can also
be loaded with a value previously stored in the EEMEM1 register. The value in the EEMEM can be changed or protected.
When changes are made to the RDAC register, the value of the
new setting can be saved into the EEMEM. Thereafter, such value
will be transferred automatically to the RDAC register during
system power ON. It is enabled by the internal preset strobe.
EEMEM can also be retrieved through direct programming and
external preset pin control.
FUNCTIONAL BLOCK DIAGRAM
AD5231
CS
ADDR
DECODE
CLK
VDD
RDAC
RDAC
REGISTER
A
SDI
SDI
SERIAL
INTERFACE
GND
SDO
SDO
WP
W
EEMEM1
DIGITAL
REGISTER
EEMEM
CONTROL
RDY
B
2
O1
DIGITAL
OUTPUT
BUFFER
O2
EEMEM2
VSS
28 BYTES
USER EEMEM
PR
100
RWA(D), RWB(D) – Percent of Nominal – % RAB
a
Nonvolatile Memory,
1024-Position Digital Potentiometers
AD5231*
RWA
RWB
75
50
25
0
0
256
512
768
1023
CODE – Decimal
Figure 1. RWA(D) and RWB(D) vs. Decimal Code
Other operations include linear step increment and decrement
commands such that the setting in the RDAC register can be
moved UP or DOWN, one step at a time. For logarithmic changes
in wiper setting, a left/right bit shift command adjusts the level
in ± 6 dB steps.
The AD5231 is available in thin TSSOP-16 package. All parts
are guaranteed to operate over the extended industrial temperature range of –40°C to +85°C.
NOTES
1
The terms Nonvolatile Memory and EEMEM are used interchangeably.
2
The terms Digital Potentiometer and RDAC are used interchangeably.
*Patent pending
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD5231–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10 k, 50 k, 100 k VERSIONS
(VDD = 3 V 10% or 5 V 10% and VSS = 0 V, VA = +VDD, VB = 0 V, –40C < TA < +85C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
DC CHARACTERISTICS
RHEOSTAT MODE
Resistor Differential Nonlinearity 2
Resistor Integral Nonlinearity 2
Nominal Resistor Tolerance
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
RWB
RAB/T
RW
RWB, VA = NC, Monotonic
RWB, VA = NC
D = 3FFH
–1
–0.2
–40
DC CHARACTERISTICS
POTENTIOMETER DIVIDER MODE
Resolution
Differential Nonlinearity3
Integral Nonlinearity3
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Terminal Voltage Range4
Capacitance5 A, B
N
DNL
INL
VW/T
VWFSE
VWZSE
VA, B, W
CA, B
Capacitance5 W
CW
Common-Mode Leakage Current 5, 6
ICM
DIGITAL INPUTS and OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Logic High
VIH
VIL
VIH
VIL
VIH
Input Logic Low
VIL
Output Logic High (SDO, RDY)
Output Logic Low
Input Current
Input Capacitance5
Output Current5
VOH
VOL
IIL
CIL
IO1, IO2
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Programming Mode Current
Read Mode Current7
Negative Supply Current
Power Dissipation8
Power Supply Sensitivity 5 IO IOL
DYNAMIC CHARACTERISTICS 5, 9
Bandwidth
Total Harmonic Distortion
Total Harmonic Distortion
VDD
VDD/VSS
IDD
IDD(PG)
IDD(XFR)
ISS
PDISS
PSS
BW
THDW
THDW
Code = Half-Scale
Code = Full-Scale
Code = Zero-Scale
± 1/2
600
15
IW = 100 µA, VDD = 5.5 V,
Code = Half-Scale
IW = 100 µA, VDD = 3 V,
Code = Half-Scale
Monotonic, TA = 25°C
Monotonic, TA = –40°C or +85°C
Typ1
10
–1
–1
–0.4
± 1/2
–3 dB, R = 10 kΩ/50 kΩ/100 kΩ
VA = 1 VRMS, VB = 0 V, f = 1 kHz,
RAB = 10 kΩ
VA = 1 VRMS, VB = 0 V, f = 1 kHz,
RAB = 50 kΩ, 100 kΩ
–2–
LSB
% FS
%
ppm/°C
Ω
100
Ω
+1
+1.25
+0.4
0
+1.5
VDD
V
pF
50
pF
1
2.4
0.8
2.1
0.6
2.0
µA
V
V
V
V
V
0.5
4.9
0.4
± 2.5
4
50
7
2.7
± 2.25
0.3
Bits
LSB
LSB
% FS
ppm/°C
% FS
% FS
50
0.01
VDD = 5 V, VSS = 0 V, TA = 25°C
VDD = 2.5 V, VSS = 0 V, TA = 25°C
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND,
VDD = +2.5 V, VSS = –2.5 V
VIH = VDD or VIL = GND
VDD = 5 V ± 10%
+1.8
+0.2
+20
15
–3
0
VSS
VSS = 0 V
Unit
50
f = 1 MHz, Measured to GND,
Code = Half-Scale
f = 1 MHz, Measured to GND,
Code = Half-Scale
VW = VDD/2
With Respect to GND, V DD = 5 V
With Respect to GND, V DD = 5 V
With Respect to GND, V DD = 3 V
With Respect to GND, V DD = 3 V
With Respect to GND,
VDD = +2.5 V, VSS = –2.5 V
With Respect to GND,
VDD = +2.5 V, VSS = –2.5 V
RPULL-UP = 2.2 kΩ to 5 V
IOL = 1.6 mA, VLOGIC = 5 V
VIN = 0 V or VDD
Max
2.7
40
3
0.5
0.018
0.002
5.5
± 2.75
10
V
V
V
µA
pF
mA
mA
9
V
V
µA
mA
mA
10
0.05
0.01
µA
mW
%/%
370/85/44
kHz
0.022
%
0.045
%
REV. 0
AD5231
Parameter
Symbol
Conditions
VW Settling Time
tS
Resistor Noise Voltage
eN_WB
VA = VDD, VB = 0 V,
VW = 0.50% Error Band,
Code 000H to 200H
For RAB = 10 kΩ/50 kΩ/100 kΩ
Min
RWB = 5 kΩ, f = 1 kHz
Typ1
Max
Unit
1.2/3.7/7
µs
9
nV/√Hz
NOTES
1
Typicals represent average readings at 25C and VDD = 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. I W ~ 50 µA @ VDD = +2.7 V and IW ~ 400 µA @ VDD = +5 V for the RAB = 10 kΩ
version, IW ~ 50 A for the RAB = 50 kΩ and I W ~ 25 A for the RAB = 100 kΩ version. See test circuit Figure 12.
3
INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = V SS. DNL
specification limits of –1 LSB minimum are Guaranteed Monotonic operating conditions. See test circuit Figure 13.
4
Resistor terminals A, B, and W have no limitations on polarity with respect to each other. Dual Supply Operat ion enables ground-referenced bipolar signal adjustment.
5
Guaranteed by design and not subject to production test.
6
Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of V DD/2.
7
Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 19.
8
PDISS is calculated from (I DD VDD) + (ISS VSS).
9
All dynamic characteristics use V DD = +2.5 V and V SS = –2.5 V.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS 10 k, 50 k, 100 k VERSIONS
(VDD = 3 V to 5.5 V and –40C < TA < +85C, unless otherwise noted.)
Parameter
Symbol
INTERFACE TIMING
CHARACTERISTICS2, 3
Clock Cycle Time (tCYC)
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay 4
CLK to SDO Data Hold Time
CS High Pulsewidth5
CS High to CS High5
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Read/Store to Nonvolatile EEMEM 6
CS Rise to Clock Rise/Fall Setup
Preset Pulsewidth (Asynchronous)
Preset Response Time to RDY High
t1
t2
t3
t 4, t 5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
tPRW
tPRESP
Conditions
Min
Clock Level High or Low
From Positive CLK Transition
From Positive CLK Transition
20
10
1
10
5
5
RP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
Typ1
40
50
50
0
10
4
0
0.1
Applies to Command 2H, 3H, 9H
Not Shown in Timing Diagram
PR Pulsed Low to Refreshed
Wiper Positions
FLASH/EE MEMORY RELIABILITY
Endurance7
Data Retention8
Max
10
50
0.15
25
Unit
ns
ns
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
tCYC
ns
ms
ms
ms
ms
70
µs
100
K Cycles
Years
100
NOTES
1
Typicals represent average readings at 25C and VDD = 5 V.
2
Guaranteed by design and not subject to production test.
3
See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using both V DD = 3 V and 5 V.
4
Propagation delay depends on value of V DD, RPULL_UP, and CL. See applications text.
5
Valid for commands that do not activate the RDY pin.
6
RDY pin low only for commands 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_8 ~ 1 s; CMD_9,10 ~0.12 s; CMD_2,3 ~20 s. Device operation at T A = –40C
and VDD < +3 V extends the save time to 35 s.
7
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40 C, +25C, and +85C; typical endurance at 25C is 700,000 cycles.
8
Retention lifetime equivalent at junction temperature (T J) = 55C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
will derate with junction temperature as shown in Figure 20 in the Flash/EE Memory Description section of this data sheet. The AD5231 contains 9,646 transistors.
Die size: 69 mil 115 mil, 7,993 sq. mil.
Specifications subject to change without notice.
REV. 0
–3–
AD5231
CPHA = 1
CS
t12
t13
t3
t1
t2
CLK
CPOL = 1
t5
t17
t4
t10
t8
SDO
t11
t9
MSB
*
LSB OUT
t7
t6
SDI
MSB
LSB
t14
t15
t16
RDY
*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2a. CPHA = 1 Timing Diagram
CS
CPHA = 0
t12
t1
t3
t2
t13
t5
CLK
CPOL = 0
t17
t4
t8
t10
t11
t9
SDO
MSB OUT
LSB
*
t7
t6
SDI
LSB
MSB IN
t14
t15
t16
RDY
*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2b. CPHA = 0 Timing Diagram
–4–
REV. 0
AD5231
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VA, VB, VW to GND . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
A–B, A–W, B–W
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 2 mA
Digital Inputs and Output Voltage to GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Operating Temperature Range3 . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ Max) . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Thermal Resistance Junction-to-Ambient JA,
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
Thermal Resistance Junction-to-Case JC,
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
Package Power Dissipation = (TJ Max – TA)/JA
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.
3
Includes programming of nonvolatile memory
ORDERING GUIDE
Model
RAB Temperature Package
Package
(k) Range (C)
Description Option
Ordering
Quantity
Top Mark*
AD5231BRU10
AD5231BRU10-REEL7
AD5231BRU50
AD5231BRU50-REEL7
AD5231BRU100
AD5231BRU100-REEL7
10
10
50
50
100
100
96
1,000
96
1,000
96
1,000
5231B10
5231B10
5231B50
5231B50
5231BC
5231BC
–40 to +85
–40 to +85
–40 to +85
–40 to +85
–40 to +85
–40 to +85
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
*Line 1 contains ADI logo symbol and the date code YYWW; line 2 contains detail model number listed in this column.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5231 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
WARNING!
ESD SENSITIVE DEVICE
AD5231
PIN CONFIGURATION
O1 1
16 O2
CLK 2
15 RDY
14 CS
SDI 3
AD5231
13 PR
TOP VIEW
GND 5 (Not to Scale) 12 WP
SDO 4
VSS 6
11 VDD
T 7
10 A
B 8
9
W
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
O1
Nonvolatile Digital Output #1. ADDR(O1) = 1H, data bit position D0
2
CLK
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
3
SDI
Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
4
SDO
Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10
activate the SDO output. (See Instruction operation Truth Table, Table III.) Other commands shift out
the previously loaded SDI bit pattern delayed by 24 clock pulses. This allows daisy-chain operation of
multiple packages.
5
GND
Ground Pin, Logic Ground Reference
6
VSS
Negative Supply. Connect to zero volts for single supply applications.
7
T
Used as digital input during factory test mode. Connect to VDD or VSS.
8
B
B Terminal of RDAC
9
W
Wiper Terminal of RDAC. ADDR(RDAC1) = 0H.
10
A
A Terminal of RDAC1
11
VDD
Positive Power Supply Pin
12
WP
Write Protect Pin. When active low, WP prevents any changes to the present contents except PR and
cmd 1 and 8 will refresh the RDAC register from EEMEM. Execute on NOP instruction before returning
to WP high.
13
PR
Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM
register. Factory default loads midscale 51210 until EEMEM loaded with a new value by the user (PR is
activated at the logic high transition).
14
CS
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
15
RDY
Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10, and PR.
16
O2
Nonvolatile Digital Output #2. ADDR(O2) = 1H, data bit position D1.
–6–
REV. 0
Typical Performance Characteristics— AD5231
1.5
2.0
VDD = 5V, VSS = 0V
TA = +85C
1.5
1.0
TA = –40C
0.5
R-DNL – LSB
INL ERROR – LSB
1.0
0.5
TA = +25C
0
0
TA = +85C T
A = +25C
–0.5
TA = –40C
–1.0
–0.5
–1.5
–1.0
0
128
256
384
512
640
768
896
–2.0
1024
0
128
256
384
512
640
CODE – Decimal
CODE – Decimal
VDD = 5.5V, V SS = 0V
VDD = 5V, V SS = 0V
RHEOSTAT MODE TEMPCO – ppm/C
1.5
1.0
DNL ERROR – LSB
1024
3000
2.0
TA = –40C
0.5
0
TA = +85C
–0.5
TA = +25C
–1.0
–1.5
TA = –40 C TO +85 C
2500
2000
1500
1000
500
0
0
–2.0
0
128
256
384
512
640
768
896
1024
128
256
CODE – Decimal
384
512
640
768
896
1024
CODE – Decimal
TPC 5. RWB/T vs. Code, RAB = 10 kΩ
TPC 2. DNL vs. Code, TA = –40°C, +25°C, +85°C Overlay,
RAB = 10 kΩ
1.0
100
POTENTIOMETER MODE TEMPCO – ppm/C
VDD = 5V, VSS = 0V
0.5
TA = +85C
R-INL – LSB
896
TPC 4. R-DNL vs. Code, TA = –40°C, +25°C, +85°C
Overlay, RAB = 10 kΩ
TPC 1. INL vs. Code, TA = –40°C, +25°C, +85°C Overlay,
RAB = 10 kΩ
0
TA = +25C
–0.5
TA = –40C
–1.0
VDD = 5.5V, V SS = 0V
TA = –40C TO +85 C
80
VB = 0V
VA = 2.00V
60
40
20
0
–20
0
128
256
384
512
640
768
896
1024
0
CODE – Decimal
128
256
384
512
640
768
896
CODE – Decimal
TPC 3. R-INL vs. Code, TA = –40°C, +25°C, +85°C
Overlay, RAB = 10 kΩ
REV. 0
768
TPC 6. RWB/T vs. Code, RAB = 10 kΩ
–7–
1024
AD5231
2
60
f–3dB = 370kHz, R AB = 10k
VDD = 2.7V, V SS = 0V
TA = 25C
0
50
–2
–4
GAIN – dB
RW – 40
30
f–3dB = 44kHz, R = 100k
–6
f–3dB = 85kHz, RAB = 50k
–8
–10
20
–12
10
VA = 1mV rms
VDD / V SS = 2.5V
D = MIDSCALE
–14
–16
1k
0
0
128
256
384
512
640
768
896
1024
100k
10k
FREQUENCY – Hz
CODE – Decimal
TPC 7. Wiper-On Resistance vs. Code
1M
TPC 10. –3 Bandwidth vs. Resistance. Test Circuit in
Figure 16.
0.12
4
VDD/V SS = 2.5V
VA = 1V rms
0.10
IDD @ V DD/V SS = 5V/0V
THD + NOISE – %
CURRENT – A
3
2
1
ISS @ V DD/V SS = 5V/0V
0
0.08
0.06
RAB = 10k
0.04
50k
0.02
IDD @ V DD/V SS = 2.7V/0V
100k
ISS @ V DD/V SS = 2.7V/0V
–1
–40
–20
0
20
40
60
80
0.00
0.01
100
0.1
TPC 8. IDD vs. Temperature, RAB = 10 kΩ
10
100
TPC 11. Total Harmonic Distortion vs. Frequency
0.25
0
VDD = 5V
VSS = 0V
–5
0.20
0.15
GAIN – dB
IDD – mA
1
FREQUENCY – kHz
TEMPERATURE – C
FULL-SCALE
0.10
–10
100H
–15
80H
–20
40H
–25
20H
–30
–35
ZERO-SCALE
CODE = 200H
10H
08H
–40
0.05
MIDSCALE
–45
04H 02H 01H
–50
1k
0.00
0
2
4
6
8
10
12
10k
100k
1M
10M
FREQUENCY– Hz
CLOCK FREQUENCY – MHz
TPC 9. IDD vs. Clock Frequency, RAB = 10 kΩ
TPC 12. Gain vs. Frequency vs. Code, RAB = 10 kΩ.
Test Circuit in Figure 18
–8–
REV. 0
AD5231
0
CODE = 200H
–10
100H
80H
GAIN – dB
100
VDD
90
–20
40H
20H
–30
VW
10H
EXPECTED
VALUE
08H
–40
MIDSCALE
04H
10
02H
–50
0.5V/DIV
100s/DIV
0%
01H
–60
1k
10k
100k
1M
FREQUENCY – Hz
TPC 13. Gain vs. Frequency vs. Code, RAB = 50 kΩ.
Test Circuit in Figure 18
TPC 16. Power-On Reset, VDD = 2.25 V,
Code = 1010101010B
2.55
0
VDD/V SS = 5V/0V
CODE = 200H TO 1FFH
CODE = 200H
–10
100H
2.53
80H
40H
VOUT – V
GAIN – dB
–20
20H
–30
10H
2.51
RAB = 10k
RAB = 50k
RAB = 100k
2.49
08H
–40
04H
2.47
02H
–50
01H
2.45
–60
1k
10k
100k
0
1M
5
10
15
20
25
TIME – s
FREQUENCY – Hz
TPC 14. Gain vs. Frequency vs. Code, RAB = 100 kΩ.
Test Circuit in Figure 18
TPC 17. Midscale Glitch Energy, Code 200H to 1FFH
80
RAB = 100k
70
5V/DIV
RAB = 50k
CS
PSRR – dB
60
RAB = 10k
50
CLK
40
30
5V/DIV
SDI
5V/DIV
20
10
IDD
20mA/DIV
VDD = +5.0V 100mV AC
VSS = 0V, VA = 5V, VB = 0V
MEASURED AT VW WITH CODE = 200 H
0
100
1k
10k
100k
FREQUENCY – Hz
4ms/DIV
1M
10M
TPC 15. PSRR vs. Frequency
REV. 0
TPC 18. IDD vs. Time (Save) Program Mode
–9–
AD5231
100
VA = VB = OPEN
TA = 25C
THEORETICAL – IWB_MAX – mA
5V/DIV
CS
CLK
5V/DIV
SDI
5V/DIV
IDD*
2mA/DIV
10
RAB = 10k
1
RAB = 50k
0.1
RAB = 100k
4ms/DIV
0.01
* SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION
IF INSTRUCTION #0 (NOP) IS EXECUTED IMMEDIATELY AFTER
INSTRUCTION #1 (READ EEMEM)
0
128
256
384
512
640
768
896
1024
CODE – Decimal
TPC 19. IDD vs. Time (Read) Program Mode
TPC 20. IWB_MAX vs. Code
OPERATIONAL OVERVIEW
Scratch Pad and EEMEM Programming
The AD5231 digital potentiometer is designed to operate as a
true variable resistor replacement device for analog signals that
remain within the terminal voltage range of VSS < VTERM < VDD.
The basic voltage range is limited to a |VDD – VSS| < 5.5 V. The
digital potentiometer wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratch pad register allowing as many value changes as necessary to place the
potentiometer wiper in the correct position. The scratch pad
register can be programmed with any position value using the
standard SPI serial interface mode by loading the complete representative data word. Once a desirable position is found this value
can be saved into an EEMEM register. Thereafter the wiper
position will always be set at that position for any future ONOFF-ON power supply sequence. The EEMEM save process
takes approximately 25 ms, during this time the shift register is
locked preventing any changes from taking place. The RDY pin
indicates the completion of this EEMEM save.
The scratch pad register (RDAC register) directly controls the
position of the digital potentiometer wiper. When the scratch
pad register is loaded with all zeros, the wiper will be connected
to the B-Terminal of the variable resistor. When the scratch pad
register is loaded with midscale code (1/2 of full-scale position),
the wiper will be connected to the middle of the variable resistor.
And when the scratch pad is loaded with full-scale code, all ones,
the wiper will connect to the A-Terminal. Since the scratch pad
register is a standard logic register, there is no restriction on the
number of changes allowed. The EEMEM registers have a program
erase/write cycle limitation described in the Flash/EEMEM
Reliability section.
There are 16 instructions that facilitate users’ programming
needs. Refer to Table III. The instructions are:
1. Do Nothing
2. Restore EEMEM Setting to RDAC
3. Save RDAC Setting to EEMEM
4. Save RDAC Setting or User Data to EEMEM
5. Decrement 6 dB
6. Decrement 6 dB
7. Decrement One Step
8. Decrement One Step
9. Reset EEMEM setting to RDAC
10. Read EEMEM to SDO
11. Read Wiper Setting to SDO
12. Write Data to RDAC
13. Increment 6 dB
14. Increment 6 dB
15. Increment One Step
16. Increment One Step
Basic Operation
The basic mode of setting the variable resistor wiper position
(programming the scratch pad register) is accomplished by
loading the serial data input register with the command instruction #11, which includes the desired wiper position data. When
the desired wiper position is found, the user would load the
serial data input register with the command instruction #2,
which makes a copy of the desired wiper position data into the
nonvolatile EEMEM register. After 25 ms the wiper position
will be permanently stored in the nonvolatile EEMEM location.
Table I provides an application-programming example listing
the sequence of serial data input (SDI) words and the serial data
output appearing at the SDO Pin in hexadecimal format.
Table I. Set and Save RDAC Data to EEMEM Register
SDI
SDO
Action
B00100H
XXXXXXH
Loads data 100H into RDAC
register, Wiper W moves to 1/4
full-scale position.
Saves copy of RDAC register
contents into EEMEM register.
20XXXXH B00100H
At system power ON, the scratch pad register is automatically
refreshed with the value last saved in the EEMEM register. The
factory preset EEMEM value is midscale but thereafter, the
EEMEM value can be changed by user.
–10–
REV. 0
AD5231
During operation, the scratch pad (wiper) register can also be
refreshed with the current content of the nonvolatile EEMEM
register under hardware control by pulsing the PR Pin without
activating instruction 1 or 8. Beware that the PR pulse first sets
the wiper at midscale when brought to logic zero, and then on
the positive transition to logic high, it reloads the RDAC wiper
register with the contents of EEMEM. Many additional advanced
programming commands are available to simplify the variable
resistor adjustment process, See Table III. For example, the
wiper position can be changed one step at a time by using the
Increment/Decrement instruction or by 6 dB at a time with the
Shift Left/Right instruction command. Once an Increment, Decrement, or Shift command has been loaded into the shift register,
subsequent CS strobes will repeat this command. This is useful
for push button control applications. See the advanced control
modes section following the Instruction Operation Truth Table. A
serial data output SDO Pin is available for daisy-chaining and
for readout of the internal register contents. The serial input
data register uses a 24-bit [instruction/address/data] WORD format.
VDD
LOGIC
PINS
INPUT
300
GND
Figure 4a. Equivalent ESD Digital Input Protection
VDD
INPUT
300
WP
EEMEM Protection
Write protect (WP) disables any changes of the scratch pad
register contents regardless of the software commands, except
that the EEMEM setting can be refreshed and overwritten WP
by using commands 1, 8, and PR pulse. Therefore, the writeprotect (WP) Pin provides a hardware EEMEM protection
feature. To disable WP, it is recommended to execute a NOP
command before returning WP to logic high.
Digital Input/Output Configuration
All digital inputs are ESD-protected high-input impedance that
can be driven directly from most digital sources. Active at logic
low, PR and WP must be biased to VDD if they are not used. No
internal pull-up resistors are present on any digital input pins.
The SDO and RDY Pins are open-drain digital outputs where
pull-up resistors are needed only if using these functions. A
resistor value in the range of 1 kΩ to 10 kΩ is a proper choice
which balances the power and switching speed trade off.
The equivalent serial data input and output logic is shown in
Figure 3. The open drain output SDO is disabled whenever chip
select CS is logic high. ESD protection of the digital inputs is
shown in Figures 4a and 4b.
PR
VALID
COMMAND
COUNTER
WP
COMMAND
PROCESSOR
AND ADDRESS
DECODE
5V
SERIAL
REGISTER
SDO
CS
SDI
Figure 4b. Equivalent WP Input Protection
Serial Data Interface
The AD5231 contains a four-wire SPI compatible digital interface (SDI, SDO, CS, and CLK). The AD5231 uses a 24-bit
serial data word loaded MSB first. The format of the SPI compatible word is shown in Table II. The chip select CS Pin needs
to be held low until the complete data word is loaded into the
SDI Pin. When CS returns high the serial data word is decoded
according to the instructions in Table III. The Command Bits
(Cx) control the operation of the digital potentiometer. The
Address Bits (Ax) determine which register is activated. The
Data Bits (Dx) are the values that are loaded into the decoded
register. Table V provides an address map of the EEMEM
locations. The last instruction executed prior to a period of no
programming activity should be the No Operation (NOP) instruction. This will place the internal logic circuitry in a minimum power
dissipation state.
The SPI interface can be used in two slave modes CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
the control bits, that dictate SPI timing in these MicroConverters®
and microprocessors: ADuC812/ADuC824, M68HC11, and
MC68HC16R1/916R1.
Daisy-Chain Operation
RPULLUP
CLK
GND
GND
AD5231
Figure 3. Equivalent Digital Input-Output Logic
The Serial Data Output Pin (SDO) serves two purposes. It can
be used to readout the contents of the wiper setting and EEMEM
values using instructions 10 and 9, respectively. The remaining
instructions (#0–#8, #11–#15) are valid for daisy-chaining
multiple devices in simultaneous operations. Daisy-chaining
minimizes the number of port pins required from the controlling IC
(see Figure 5). The SDO Pin contains an open drain N-Ch FET
that requires a pull-up resistor, if this function is used. As shown
in Figure 5, users need to tie the SDO Pin of one package to the
MicroConverter is a registered trademark of Analog Devices Inc.
REV. 0
–11–
AD5231
SDI Pin of the next package. Users may need to increase the clock
period because the pull-up resistor and the capacitive loading at
the SDO-SDI interface may require additional time delay between
subsequent packages. When two AD5231s are daisy-chained, 48
bits of data are required. The first 24 bits go to U2 and the second
24 bits go to U1. The 24 bits are formatted to contain the 4-bit
instruction, followed by the 4-bit address, 6-bit don’t care, then
the 10 bits of data. (The don’t care can be used to store user
information. See section Using Additional Internal Nonvolatile
EEMEM). The CS should be kept low until all 48 bits are clocked
into their respective serial registers. The CS is then pulled high to
complete the operation.
+V
AD5231
C
SDI
U1
CS
AD5231
RP
2k
SDO
CLK
SDI
CS
A, B, and W (see Figure 6), it is important to power VDD/VSS first
before applying any voltage to terminals A, B, and W. Otherwise,
the diode will be forward-biased such that VDD/VSS will be powered
unintentionally and may affect the rest of the user’s circuit. The
ideal power-up sequence is in the following order: GND, VDD, VSS,
Digital Inputs, and V A/B/W. The order of powering VA, VB, VW,
and digital inputs are not important as long as they are powered
after VDD/VSS.
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD/VSS are powered, the power-on reset
remains effective, which retrieves EEMEM saved value to
RDAC register.
Latched Digital Outputs
A pair of digital outputs, O1 and O2, is available on the AD5231
that provide a nonvolatile logic 0 or logic 1 setting. O1 and O2 are
standard CMOS logic outputs (shown in Figure 7). These outputs
are ideal to replace functions often provided by DIP switches. In
addition, they can be used to drive other standard CMOS logic
controlled parts that need an occasional setting change.
SDO
U2
Power-Up Sequence
Since there are diodes to limit the voltage compliance at terminals
CLK
Figure 5. Daisy Chain Configuration using SDO
VDD
Terminal Voltage Operation Range
The AD5231 positive VDD and negative VSS power supply
OUTPUTS
defines the boundary conditions for proper 3 terminal digital
potentiometer operation. Supply signals present on terminals A,
B, and W that exceed VDD or VSS will be clamped by the internal
forward biased diodes (see Figure 6).
The ground pin of the AD5231 device is primarily used as a
digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the AD5231
must be referenced to the device ground pin (GND), and satisfy
the logic level defined in the specification table of this data
sheet. An internal level-shift circuit ensures that the commonmode voltage range of the three terminals extends from VSS to
VDD, regardless of the digital input level.
O1 AND O2
PINS
GND
Figure 7. Logic Outputs O1 and O2
VDD
A
W
B
VSS
Figure 6. Maximum Terminal Voltages Set by VDD and VSS
–12–
REV. 0
AD5231
Table II. AD5231 24-Bit Serial Data Word
MSB Instruction Byte 0
Data Byte 1
Data Byte 0
LSB
RDAC
C3 C2 C1 C0 0 0 0 A0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D D D D D D D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
15 14 13 12 11 10
Command bits are C0 to C3. Address bits are A3 to A0. Data bits D0 to D9 are applicable to RDAC; D0 to D15 are applicable to EEMEM. Command
instruction codes are defined in Table III.
Table III. Instruction/Operation Truth Table 1, 2, 3
Instruction
Number
Instruction Byte 0
B23 ••••••••••••••••••••••• B16
C3 C2 C1 C0 A3 A2 A1 A0
Data Byte 1
B15 ••••• B8
X ••• D9 D8
Data Byte 0
B7 ••• B0
D7 ••• D0
0
1
0 0 0 0 X X X X
0 0 0 1 0 0 0 A0
X ••• X X
X ••• X X
X ••• X
X ••• X
2
0 0 1 0 0 0 0 A0
X ••• X X
X ••• X
34
0 0 1 1 A3 A2 A1 A0
D15 ••• D8
D7 ••• D0
45
0 1 0 0 0 0 0 A0
X ••• X X
X ••• X
55
65
0 1 0 1 X X X X
0 1 1 0 0 0 0 A0
X ••• X X
X ••• X X
X ••• X
X ••• X
75
8
0 1 1 1 X X X X
1 0 0 0 X X X X
X ••• X X
X ••• X X
X ••• X
X ••• X
9
1 0 0 1 A3 A2 A1 A0
X ••• X X
X ••• X
10
1 0 1 0 0 0 0 A0
X ••• X X
X ••• X
11
1 0 1 1 0 0 0 A0
X ••• D9, D8
D7 ••• D0
125
1 1 0 0 0 0 0 A0
X ••• X X
X ••• X
135
145
1 1 0 1 X X X X
1 1 1 0 0 0 0 A0
X ••• X X
X ••• X X
X ••• X
X ••• X
155
1 1 1 1 X X X X
X ••• X X
X ••• X
Operation
NOP: Do nothing. See Table XI
Write content of EEMEM to RDAC Register.
This command leaves device in the Read Program power state. To return part to the idle
state, perform NOP instruction #0. See Table XI
SAVE WIPER SETTING: Write contents of
RDAC to EEMEM. See Table X
Write contents of Serial Register Data Bytes 0
and 1 (total 16-bit) to EEMEM(ADDR).
See Table XIII
Decrement 6 dB: Right Shift contents of
RDAC, stops at all “Zeros.”
Same as instruction 4
Decrement content of RDAC Register by “One,”
stops at all “Zeros.”
Same as instruction 6
RESET: Load RDAC with its corresponding
EEMEM previously saved value.
Write content of EEMEM(ADDR) to Serial
Register Data Bytes 0 and 1. SDO activated.
See Table XIV
Write content of RDAC to Serial Register Data
Bytes 0 and 1. SDO activated. See Table XV
Write content of Serial Register Data Bytes 0
and 1 (total 10-bit) to RDAC Register.
See Table IX
Increment 6 dB: Left Shift content of RDAC,
stops at all “Ones.” See Table XII
Same as instruction 12
Increment content of RDAC Register by “One,”
stops at all “Ones.” See Table X.
Same as instruction 14
NOTES
1
The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception, any instruction following instruction #9 or #10,
the selected internal register data will be present in Data Bytes 0 and 1. The instruction following #9 and #10 must also be a full 24-bit data word to completely clock
out the contents of the serial register.
2
The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding nonvolatile EEMEM register.
3
Execution of the above operations takes place when the CS strobe returns to logic high.
4
Instruction #3 write two data bytes (16-Bit data) to EEMEM. In the case of 0 addresses, only the last 10 bits are valid for wiper position setting.
5
The increment, decrement, and shift commands ignore the contents of the shift register Data Bytes 0 and 1.
REV. 0
–13–
AD5231
ADVANCED CONTROL MODES
Table IV. Detail Left and Right Shift Functions for 6 dB Step
Increment and Decrement
The AD5231 digital potentiometer contains a set of user programming features to address the wide applications available to
these universal adjustment devices. Key programming features
include:
• Scratch Pad Programming to any desirable values
• Nonvolatile memory storage of the present scratch pad
RDAC register value into the EEMEM register
• Increment and Decrement instructions for RDAC wiper
register
• Left and right Bit Shift of RDAC wiper register to achieve
6 dB level changes
• 28 extra bytes of user-addressable nonvolatile memory
Left Shift
00 0000 0000
00 0000 0001
00 0000 0010
Left Shift
(+6 dB/step) 00 0000 0100
00 0000 1000
00 0001 0000
00 0010 0000
00 0100 0000
00 1000 0000
01 0000 0000
10 0000 0000
11 1111 1111
11 1111 1111
Linear Increment and Decrement Commands
Logarithmic Taper Mode Adjustment (6 dB/step)
Four programming instructions produce logarithmic taper
increment and decrement wiper. These settings are activated by
the 6 dB increment and 6 dB decrement instructions #12, #13,
#4, and #5, respectively. For example, starting at zero scale,
executing 11 times the increment instruction #12 will move the
wiper in +6 dB per step from the 0% to full scale RAB. The +6 dB
increment instruction doubles the value of the RDAC register
content each time the command is executed. When the wiper
position is near the maximum setting, the last +6 dB increment
instruction will cause the wiper to go to the full-scale 1023 code
position. Further +6 dB per increment instruction will no longer
change the wiper position beyond its full scale.
6 dB step increment and decrement are achieved by shifting the bit
internally to the left and right, respectively. The following information explains the nonideal ± 6 dB step adjustment at certain
conditions. Table IV illustrates the operation of the shifting
function on the RDAC register data bits. Each line going down
the table represents a successive shift operation. Note that the left
shift #12 and #13 commands were modified such that if the data
in the RDAC register is equal to zero, and the data is left shifted,
the RDAC register is then set to code 1. Similarly, if the data in
the RDAC register is greater than or equal to midscale, and the
data is left shifted, then the data in the RDAC register is automatically set to full-scale. This makes the left shift function as ideal a
logarithmic adjustment as possible.
The right shift #4 and #5 commands will be ideal only if the LSB
is zero (i.e., ideal logarithmic—no error). If the LSB is a 1, the right
shift function generates a linear half LSB error, which translates to
a numbers of bits dependent logarithmic error as shown in Figure
8. The plot shows the error of the odd numbers of bits for AD5231.
11 1111 1111
01 1111 1111
00 1111 1111
00 0111 1111
00 0011 1111
00 0001 1111
00 0000 1111
00 0000 0111
00 0000 0011
00 0000 0001
00 0000 0000
00 0000 0000
00 0000 0000
Right Shift
(–6 dB/step)
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
Right Shift #4 and #5 command execution contains an error
only for odd numbers of bits. Even numbers of bits are ideal.
The graph in Figure 8 shows plots of Log_Error [i.e., 20 log10
(error/code)] AD5231. For example, code 3 Log_Error = 20 log10 (0.5/3) = –15.56 dB, which is the worst case. The plot of
Log_Error is more significant at the lower codes.
0
–20
dB
The increment and decrement commands (#14, #15, #6, #7)
are useful for linear step adjustment applications. These commands
simplify microcontroller software coding by allowing the controller
to just send an increment or decrement command to the device.
For increment command, executing instruction #14 with proper
address will automatically move the wiper to the next resistance
segment position. Instruction #15 performs the same function
except address does not need to be specified.
Right Shift
–40
–60
–80
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
CODE – From 1 to 1023 by 2.0 103
Figure 8. Plot of Log_Error Conformance for Odd
Numbers of Bits Only (Even Numbers of Bits are Ideal)
Using Additional Internal Nonvolatile EEMEM
The AD5231 contains additional internal user storage registers
(EEMEM) for saving constants and other 16-bit data. Table V
provides an address map of the internal storage registers shown
in the functional block diagram as EEMEM1, EEMEM2, and
28 bytes (14 addresses 2 bytes each) of User EEMEM.
–14–
Table V. EEMEM Address Map
Address
EEMEM For
0000
0001
0010
0011
RDAC1, 2
O1 and O23
USER14
USER2
:
:
1110
1111
USER13
USER14
REV. 0
AD5231
RDAC STRUCTURE
The patent pending RDAC contains multiple strings of equal
resistor segments, with an array of analog switches, that act as
the wiper connection. The number of positions is the resolution
of the device. The AD5231 has 1024 connection points allowing
it to provide better than 0.1% set-ability resolution. Figure 9
shows an equivalent structure of the connections between the
three terminals of the RDAC. The SWA and SWB will always be
ON, while one of the switches SW(0) to SW(2N–1) will be ON
one at a time depending on the resistance position decoded
from the data bits. Since the switch is not ideal, there is a 15 Ω
wiper resistance, RW. Wiper resistance is a function of supply
voltage and temperature. The lower the supply voltage, or the
higher the temperature, the higher the resulting wiper resistance.
Users should be aware of the wiper resistance dynamics if accurate prediction of the output resistance is needed.
part. For VDD = 5 V, the wiper first connection starts at the B
terminal for data 000H. RWB(0) is 15 Ω because of the wiper
resistance and it is independent of the nominal resistance. The
second connection is the first tap point where RWB(1) becomes
9.7 Ω + 15 Ω = 27.4 Ω for data 001H. The third connection is
the next tap point representing RWB(2) = 19.4 + 15 = 34.4 Ω for
data 002H and so on. Each LSB data value increase moves the
wiper up the resistor ladder until the last tap point is reached at
RWB(1023) = 10005 Ω. See Figure 9 for a simplified diagram of
the equivalent RDAC circuit. When RWB is used, the A–terminal
can be left floating or tied to the wiper.
100
RWA
RWA(D), RWB(D) – % of Nominal RAB
NOTES
1
RDAC data stored in EEMEM location is transferred to the RDAC Register at
Power ON, or when instructions #1, #8, and PR are executed.
2
Execution of instruction #1 leaves the device in the Read Mode power consumption state. After the last instruction #1 is executed, the user should perform
a NOP, instruction #0 to return the device to the low power idling state.
3
O1 and O2 data stored in EEMEM locations are transferred to their corresponding
Digital Register at Power ON, or when instructions #1 and #8 are executed.
4
USER <data> are internal nonvolatile EEMEM registers available to store and
retrieve constants and other 16-bit information using #3 and #9, respectively.
RWB
75
50
25
0
0
SWA
256
512
CODE – Decimal
768
1023
A
Figure 10. RWA(D) and RWB(D) vs. Decimal Code
SW(2N–1)
RDAC
WIPER
REGISTER
AND
DECODER
RS = RAB
RS
The general equation, which determines the programmed output
resistance between W and B, is:
W
D
(1)
× R AB + RW
1024
Where D is the decimal equivalent of the data contained in the
RDAC register, RAB is the Nominal Resistance between terminals
A-and-B, and RW is the wiper resistance.
SW(2N– 2)
RS
SW(1)
RS
SW(0)
RWB ( D) =
For example, the following output resistance values will be set
for the following RDAC latch codes with VDD = 5 V (applies to
RAB = 10 kΩ Digital Potentiometers):
/ 2N
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
SWB
B
Table VII. RWB at Selected Codes for RAB = 10 kΩ
Figure 9. Equivalent RDAC Structure (Patent Pending)
Table VI. Nominal Individual Segment Resistor (R S)
Device
Resolution
10 k
Version
50 k
Version
100 k
Version
10-Bit
9.8 Ω
48.8 Ω
97.6 Ω
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A-andB, RAB is available with 10 kΩ, 50 kΩ, and 100 kΩ with 1024
positions (10-bit resolution). The final digit(s) of the part number
determine the nominal resistance value, e.g., 10 kΩ = 10; 50 kΩ = 50;
100 kΩ = C.
The 10-bit data word in the RDAC latch is decoded to select one
of the 1024 possible settings. The following discussion describes
the calculation of resistance RWB at different codes of a 10 kΩ
REV. 0
D(DEC) RWB(D) (Ω) Output State
1023
512
1
0
10,005
50015
24.7
15
Full-Scale
MidScale
1 LSB
Zero-Scale (Wiper Contact Resistor)
Note that in the zero-scale condition a finite wiper resistance of
15 Ω is present. Care should be taken to limit the current flow
between W and B in this state to no more than 20 mA to avoid
degradation or possible destruction of the internal switches.
Like the mechanical potentiometer the RDAC replaces, the
AD5231 parts are totally symmetrical. The resistance between the
wiper W and terminal A also produces a digitally controlled
complementary resistance RWA. Figure 10 shows the symmetrical
programmability of the various terminal connections. When RWA
is used, the B-terminal can be let floating or tied to the wiper.
Setting the resistance value for RWA starts at a maximum value of
resistance and decreases as the data loaded in the latch is increased
in value. The general transfer equation for this operation is:
–15–
AD5231
1024 – D
(2)
× R AB + RW
1024
For example, the following output resistance values will be set
for the following RDAC latch codes with VDD = 5 V (applies to
RAB = 10 kΩ Digital Potentiometers):
RWA ( D) =
Table VIII. RWA(D) at Selected Codes for RAB = 10 kΩ
D(DEC)
RWA(D) (Ω)
Output State
1023
512
1
0
24.7
5015
10005
10015
Full-Scale
MidScale
1 LSB
Zero-Scale
The typical distribution of RAB from device-to device matches tightly
when they are processed at the same batch. When devices are processed at different time, device-to device matching becomes process
lot dependent and exhibits a –40% to +20% variation. The change
in RAB with temperature has a 600 ppm/°C temperature coefficient.
Table X. Incrementing RDAC Followed by Storing the Wiper
Setting to EEMEM
SDI
SDO
B00100H
XXXXXXH
Loads data 100H into RDAC
register, Wiper W moves to 1/4
full-scale position.
Increments RDAC register by one
E0XXXXH B00100H
to 101H.
E0XXXXH E0XXXXH
Increments RDAC register by one
to 102H.
Continue until desired wiper position is reached.
Saves RDAC register data into
20XXXXH XXXXXXH
EEMEM.
Optionally tie WP to GND to protect EEMEM values.
Table XI. Restoring EEMEM Value to RDAC Register
EEMEM value for RDAC can be restored by Power On, or
Strobing PR pin, or Programming shown below.
SDI
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer can be configured to generate an
output voltage at the wiper terminal which is proportional to the
input voltages applied to terminals A and B. For example connecting A-terminal to 5 V and B-terminal to ground produces
an output voltage at the wiper which can be any value starting at
0 V up to 5 V. Each LSB of voltage is equal to the voltage applied
across terminal AB divided by the 2N position resolution of the
potentiometer divider.
Since AD5231 can also be supplied by dual supplies, the general
equation defining the output voltage at VW with respect to ground
for any given input voltages applied to terminals A and B is:
D
(3)
× VAB + VB
1024
Equation 3 assumes VW is buffered so that the effect of wiper
resistance is nulled. Operation of the digital potentiometer in the
divider mode results in more accurate operation over temperature.
Here the output voltage is dependent on the ratio of the internal
resistors and not the absolute value, therefore, the drift improves
to 15 ppm/°C. There is no voltage polarity restriction between
terminals A, B, and W as long as the terminal voltage (V TERM)
stays within VSS < VTERM < VDD.
Action
SDO
10XXXXH XXXXXXH
00XXXXH 10XXXXH
8XXXXXH 00XXXXH
Action
Restores EEMEM value to RDAC
register.
NOP. Recommended step to
minimize power consumption.
Reset EEMEM value to RDAC
register.
Table XII. Using Left Shift by One to Increment +6 dB Step
SDI
SDO
C0XXXXH XXXXXXH
Action
Moves wiper to double the present
data contained in RDAC register.
VW ( D) =
Table XIII. Storing Additional User Data in EEMEM
SDI
SDO
Action
32AAAAH
XXXXXXH
335555H
32AAAAH
Stores data AAAAH into spare
EEMEM location USER1. (Allowable
to address in 14 locations with
maximum 16 bits of Data.)
Stores data 5555H into spare EEMEM
location USER2.
(Allowable to address in 14 locations
with maximum 16 bits of Data.)
PROGRAMMING EXAMPLES
The following programming examples illustrate typical sequence of
events for various features of the AD5231. Users should refer to
Table III for the instructions and data word format. The Instruction
numbers, addresses, and data appearing at SDI and SDO Pins are
based in hexadecimal in the following examples.
Table IX. Scratch Pad Programming
SDI
SDO
Action
B00100H
XXXXXXH
Loads data 100H into RDAC
register, Wiper W moves to 1/4
full-scale position.
Table XIV. Reading Back Data From Various Memory Locations
SDI
SDO
92XXXXH XXXXXXH
00XXXXH 92AAAAH
–16–
Action
Prepares data read from USER1
location.
NOP instruction #0 sends 24-bit
word out of SDO where the last 16
bits contain the contents of USER1
location. NOP command ensures
device returns to idle power dissipation state.
REV. 0
AD5231
Table XV. Reading Back Wiper Settings
A
DUT B
5V
SDI
SDO
Action
B00200H
XXXXXXH
C0XXXXH B00200H
Sets RDAC to midscale.
Doubles RDAC from midscale to
full-scale. (Left shift instructions)
Prepares reading wiper setting from
RDAC register.
Readback full-scale value from
RDAC register.
A0XXXXH C0XXXXH
XXXXXXH A003FFH
W
VIN
VOUT
OP279
OFFSET
GND
OFFSET BIAS
Figure 15. Inverting Gain Test Circuit
5V
OP279
VIN
TEST CIRCUITS
VOUT
W
Figures 11 to 19 define the test conditions used in the product
specifications table.
OFFSET
GND
A
DUT
B
OFFSET BIAS
NC
DUT
A
W
IW
Figure 16. Noninverting Gain Test Circuit
B
W
VIN
NC = NO CONNECT
DUT
2.5V
–15V
0.1V
ISW
CODE = H
W
RSW =
DUT
B
VOUT
Figure 17. Gain vs. Frequency Test Circuit
V+ = V DD
1LSB = V+/2N
A
V+
OP42
B
OFFSET
GND
Figure 11. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
DUT
+15V
A
VMS
VMS
W
+
B
Figure 12. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
W
VMS2
Figure 18. Incremental ON Resistance Test Circuit
RW = [V MS1 – V MS2] / IW
Figure 13. Wiper Resistance Test Circuit
V+ = V DD 10%
~
B
PSRR (dB) = 20 LOG
W
VMS
PSS (%/%) =
(
VMS
A
VSS GND
B
ICM
W
VCM
VDD
Figure 19. Common-Mode Leakage Current Test Circuit
)
VMS%
VDD%
Figure 14. Power Supply Sensitivity Test Circuit
(PSS, PSRR)
REV. 0
VDD
DUT
NC
NC = NO CONNECT
VA
V+
VBIAS
NC
VMS1
A
0.1V
VW
B
VDD
_
A = NC
IW
DUT
A
ISW
–17–
AD5231
FLASH/EEMEM RELIABILITY
The Flash/EE Memory array on the AD5231 is fully qualified for two
key Flash/EE memory characteristics, namely Flash/EE Memory
Cycling Endurance and Flash/EE Memory Data Retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many Program, Read, and Erase cycles. In real
terms, a single endurance cycle is composed of four independent,
sequential events. These events are defined as:
APPLICATIONS
Bipolar Operation From Dual Supplies
The AD5231 can be operated from dual supplies ± 2.5 V, which
enables control of ground referenced ac signals or bipolar operation.
AC signal, as high as VDD/VSS, can be applied directly across
terminals A-B with output taking from terminal W. (See Figure
21 for a typical circuit connection.)
+2.5V
• Initial Page Erase Sequence
VDD
• Read/Verify Sequence
C
• Byte Program Sequence
GND
CS
CLK
SDI
SS
SCLK
MOSI
• Second Read/Verify Sequence
GND
As indicated in the specification pages of this data sheet, the AD5231
Flash/EE Memory Endurance qualification has been carried out in
accordance with JEDEC Specification A117 over the industrial
temperature range of –40°C to +85°C. The results allow the
specification of a minimum endurance figure over supply and
temperature of 100,000 cycles, with an endurance figure of
700,000 cycles being typical of operation at 25°C.
1.25V p-p
2.5V p-p
B
AD5231
VSS
D = MIDSCALE
–2.5V
Figure 21. Bipolar Operation from Dual Supplies
High Voltage Operation
Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. Again, the AD5231 has been
qualified in accordance with the formal JEDEC Retention Lifetime
Specification (A117) at a specific junction temperature (TJ = 55°C).
As part of this qualification procedure, the Flash/EE memory is
cycled to its specified endurance limit described above, before data
retention is characterized. This means that the Flash/EE memory
is guaranteed to retain its data for its full specified retention lifetime
every time the Flash/EE memory is reprogrammed. It should also
be noted that retention lifetime, based on an activation energy of
0.6 eV, will derate with TJ as shown in Figure 20. For example, the
data is retained for 100 years at 55°C operation, but reduces to
15 years at 85°C operation. Beyond such limit, the part must be
reprogrammed so that the data can be restored.
The Digital Potentiometer can be placed directly in the feedback or
input path of an op amp for gain control, provided that the voltage
across terminals A-B, W-A, or W-B does not exceed |5 V|. When
high voltage gain is needed, users should set a fixed gain in an op
amp operated at +15 V, and let the digital potentiometer control
the adjustable input. Figure 22 shows a simple implementation.
R
2R
15V
5V
A
AD5231
–
V+
A1
W
+
VO
V–
0 TO 15V
B
Figure 22. 15 V Voltage Span Control
Bipolar Programmable Gain Amplifier
300
There are several ways to achieve bipolar gain. Figure 23 shows one
versatile implementation. Digital potentiometer U1 sets the
adjustment range, the wiper voltage V W2 can therefore be
programmed between Vi and –KVi at a given U2 setting. For linear
adjustment, configure A2 as a noninverting amplifier and the transfer function becomes:
250
RETENTION – Years
A
W
During reliability qualification Flash/EE memory is cycled from
000H to 3FFH until a first fail is recorded signifying the endurance
limit of the on-chip Flash/EE memory.
200
ADI TYPICAL
PERFORMANCE
AT TJ = 55C
150
VO 

R2   D2
= 1+
×
× (1 + K ) – K 


Vi
R1
 1024

100
(4)
where:
K is the ratio of RWB/RWA which is set by U1.
D = Decimal Equivalent of the Input Code
50
0
40
VDD
50
60
70
80
90
TJ JUNCTION TEMPERATURE – C
100
110
Figure 20. Flash/EE Memory Data Retention
–18–
REV. 0
AD5231
Programmable Voltage Reference
VDD
For programmable voltage divider mode operation (Figure 25)
it is common to buffer the output of the digital potentiometer
unless the load is much larger than the source resistance RWB. In
addition, the current handling of the digital potentiometer is
limited by its maximum operating voltage, power dissipation, and
the maximum current handling of the internal switches at a
given resistance (see TPC 20). As a result, the added buffer can
be used to deliver the current needed to the load as long as it is
within its current handling capability.
U2
V+
AD5231
OP2177
W
B
A
VO
V–
R2
A2
B
A
Vi
VSS
–kVi
W
U1
VDD
R1
V+
AD5231
OP2177
V–
A
5V
VSS
Figure 23. Bipolar Programmable Gain Amplifier
1
VIN VOUT
In the simpler (and much more usual) case where K = 1, a pair
of matched resistors can replace U1. Equation 4 simplifies to:
2
(5)
D
R1 = , R2 = 0
R1 = R2 R2 = 9 R1
0
256
512
768
1023
–1
–0.5
0
0.5
0.992
–2
–1
0
1
1.984
–10
–5
0
5
9.92
(6)
AD5231
V+
U1
AD8552
V–
A
A2
R
TRIM
GND
–2.5VREF
–5V
VO
W
P1
RBIAS
LD
V+
N1
A1
V–
IBIAS
A1 = AD8601, AD8605, AD8541
P1 = FDP360P, NDS9430
N1 = FDV301N, 2N7002
Figure 26. Boosted Voltage Source
In this circuit, the inverting input of the op amp forces the
VBIAS to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the
P-Ch FET P1. The N-Ch FET N1 simplifies the op amp driving
requirement. Resistor R1 is needed to prevent P1 for not turning
off once it is on. The choice of R1 is a balance between the power
loss of this resistor and the output turn off time. N1 can be any
general purpose signal FET; on the other hand, P1 is driven in
the saturation state and therefore its power handling must be
adequate to dissipate (VS – VBIAS) IBIAS power. This circuit
can source maximum of 100 mA at 5 V supply. Higher current
can be achieved with P1 in larger package. Note a single N-Ch
FET can replace P1, N1, and R1 altogether. However, the output
swing will be limited unless separate power supplies are used.
For precision application, a voltage reference such as ADR423,
ADR292, and AD1584, can be applied at the input of the digital
potentiometer.
V+
AD8552
V–
A1
–5V
Figure 24. 10-Bit Bipolar DAC
REV. 0
R1
10k
SIGNAL CC
A
+5V
ADR421
VBIAS
AD5231
 2D2

VO = 
– 1 × V REF
1024


+5V
VO
V–
AD1582
VS
5V
If the circuit is changed in Figure 23 with the input taking from a
voltage reference and configure A2 as a buffer, a 10-bit bipolar DAC
can be realized. Compared to the conventional DAC, this circuit
offers comparable resolution but not the precision because of the wiper
resistance effects. Degradation of the nonlinearity and temperature
coefficient are prominent near both ends of the adjustment range.
On the other hand, this circuit offers a unique nonvolatile memory
feature which in some cases outweigh the shortfall of nonprecision.
The output of this circuit is:
+2.5VREF
AD8601
Programmable Voltage Source with Boosted Output
10-Bit Bipolar DAC
VIN VOUT
V+
B
Figure 25. Programmable Voltage Reference
B
B
W
For applications such as laser diode driver or turnable laser,
requiring high current adjustment a boosted voltage source can
be considered (see Figure 26).
Table XVI. Result of Bipolar Gain Amplifier
R
A
A1
Table XVI shows the result of adjusting D with A2 configured as
a unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 1024-step resolution.
+5V
5V
3
GND
VO 
R2   2 D 2 
= 1+
–1
×

VI
R1   1024 
W
AD5231
U1
–19–
AD5231
R2B in theory can be made as small as needed to achieve the
current needed within A2 output current driving capability. In
this circuit OP2177 delivers ± 5 mA in both directions and the
voltage compliance approaches 15 V. It can be shown that the
output impedance is:
Programmable 4 mA to 20 mA Current Source
A programmable 4 mA to 20 mA current source can be implemented with the circuit shown in Figure 27.
+5V
2
U1
VIN
3
SLEEP VOUT
6
ZO =
0 TO (2.048 + VL)
B
REF191
C1
GND
1F
RS
102
+5V
V+
–
AD5231
OP1177
Resistance Scaling
U2
V–
+
–2.048V TO VL
(9)
ZO can be infinite if resistors R1 and R2 match precisely with R1
and R2A + R2B respectively. On the other hand, ZO can be negative if the resistors are not matched. As a result, C1 and C2, in
the range of 1 pF to 10 pF, are needed to prevent the oscillation.
W
A
4
R1
 R1 × R2'

– 1

 R1' × R2 
VL
RL
100
–5V
IL
Figure 27. Programmable 4 mA to 20 mA Current Source
REF191 is a unique low supply headroom precision reference
that can deliver the 20 mA needed at 2.048 V. The load current
is simply the voltage across terminals B-to-W of the digital
potentiometer divided by RS:
AD5231 offers 10 kΩ, 50 kΩ, and 100 kΩ nominal resistance. For
users who need lower resistance but want to maintain the numbers
of step adjustment, they can parallel multiple devices. For example,
Figure 29 shows a simple scheme of paralleling two AD5231. In
order to adjust half of the resistance linearly per step, users need to
program both devices coherently with the same settings and tie
the terminals as shown.
A1
V
× D
I L =  REF

RS


(7)
B1
A2
W1
LD
The circuit is simple, but be aware that there are two issues. First,
dual supply op amps are ideal because the ground potential of
REF191 can swing from –2.048 V at zero scale to VL at full scale
of the potentiometer setting. Although the circuit works under
single supply, the programmable resolution of the system will be
reduced. Second, the voltage compliance at VL is limited to 2.5 V or
equivalently a 125 Ω load. Should higher voltage compliance be
needed, users may consider digital potentiometers AD5260, AD5280,
and AD7376. Figure 28 below shows an alternate circuit for high
voltage compliance.
Figure 29. Reduce Resistance by Half with Linear
Adjustment Characteristics
In voltage divider mode, a much lower resistance can be achieved
by paralleling a discrete resistor as shown in Figure 30. The equivalent resistance become:
RWBeq =
D
( R1 / / R2) + RW
1024
For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be a
solution. If the resistors are matched, the load current is:
R2
× VW
(11)
A
( R2 A + R2 B)
R1
R2 B
(10)
D 
RWA = 1 –
( R1 / / R2) + RW
eq
 1024 
Programmable Bidirectional Current Source
IL =
W2
B2
R1
W
(8)
B R2 << R1
Figure 30. Lowering the Nominal Resistance
R1
150k
R2
15k
+15V
–
+2.5V
A
AD5231
B W
–2.5V
+
V+
OP2177
– V–
A1
–15V
C1
10pF
V+
OP2177
+ V– A2
+15V
Figures 29 and 30 show that the digital potentiometers change
steps linearly. On the other hand, log taper adjustment is usually
preferred in applications like audio control. Figure 31 shows
another way of resistance scaling. In this configuration, the
smaller the R2 with respect to R1, the more the pseudo log
taper characteristic behaves.
C2
10pF
R2B
50
–15V
R1
150k
R2A
14.95k
VL
RL
500
IL
Figure 28. Programmable Bidirectional Current Source
–20–
REV. 0
AD5231
A
B
Listing I. Macro Model Net List for RDAC
VO
R1
W
.PARAM D = 1024, RDAC = 10E3
R2
*
.SUBCKT DPOT (A, W, B)
Figure 31. Resistor Scaling with Pseudo Log Adjustment Characteristics
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external load dominates
the ac characteristics of the RDACs. Configured as a potentiometer divider the –3 dB bandwidth of the AD5231BRU10 (10 kΩ
resistor) measures 370 kHz at half scale. TPC 10 provides the large
signal BODE plot characteristics. A parasitic simulation mode is
shown in Figure 32. Listing I provides a macro model net list for
the 10 kΩ RDAC:
*
CA
A
0
50E-12
RAW
A
W
{(1-D/1024)*RDAC+15}
CW
W
0
50E-12
RBW
W
B
{D/1024*RDAC+15}
CB
B
0
50E-12
*
.ENDS DPOT
RDAC
10k
A
B
CA
50pF
CB
50pF
CW
50pF
W
Figure 32. RDAC Circuit Simulation Model for
RDAC = 10 kΩ
REV. 0
–21–
AD5231
DIGITAL POTENTIOMETER FAMILY SELECTION GUIDE
Number
Part
of VRs per
Number Package
Terminal
Voltage
Range (V)
Interface
Data
Control
Nominal
Resistance
(k)
Resolution
(Number
of Wiper
Positions)
Power
Supply
Current
(IDD) (A) Packages
AD5201
1
± 3, +5.5
3-Wire
10, 50
33
40
µSOIC-10
Full ac Specs,
Dual Supply,
Power-On Reset,
Low Cost
AD5220
1
5.5
UP/
DOWN
10, 50, 100
128
40
PDIP, SO-8,
µSOIC-8
No Rollover,
Power-On Reset
AD7376
1
± 15, +28
3-Wire
10, 50, 100,
1000
128
100
PDIP-14,
SOL-16,
TSSOP-14
Single 28 V
or Dual ± 15 V
Supply Operation
AD5200
1
± 3, +5.5
3-Wire
10, 50
256
40
µSOIC-10
Full ac Specs,
Dual Supply,
Power-On Reset
AD8400
1
5.5
3-Wire
1, 10, 50, 100
256
5
SO-8
Full ac Specs
AD5260
1
± 5, +15
3-Wire
20, 50, 200
256
60
TSSOP-14
5 V to 15 V or ± 5 V
Operation,
TC < 50 ppm/°C
AD5241
1
± 3, +5.5
2-Wire
10, 100, 1000
256
50
SO-14,
TSSOP-14
I2C Compatible,
TC < 50 ppm/°C
AD5231
1
± 2.75, +5.5
3-Wire
10, 50, 100
1024
20
TSSOP-16
Nonvolatile
Memory, Direct
Program, I/D, ± 6 dB
Settability
AD5222
2
± 3, +5.5
UP/
DOWN
10, 50, 100,
1000
128
80
SO-14,
TSSOP-14
AD8402
2
5.5
3-Wire
1, 10, 50, 100
256
5
PDIP, SO-14,
TSSOP-14
No Rollover, Stereo
Power-On Reset,
TC < 50 ppm/°C
Full ac Specs, nA
Shutdown Current
AD5207
2
± 3, +5.5
3-Wire
10, 50, 100
256
40
TSSOP-14
Full ac Specs, Dual
Supply, Power-On
Reset, SDO
AD5232
2
± 2.75, +5.5
3-Wire
10, 50, 100
256
20
TSSOP-16
Nonvolatile Memory,
Direct Program, I/D,
± 6 dB Settability
AD5235
2
± 2.75, +5.5
3-Wire
25, 250
1024
20
TSSOP-16
Nonvolatile Memory,
Direct Program,
TC < 50 ppm/°C
AD5242
2
± 3, +5.5
2-Wire
10, 100, 1000
256
50
SO-16,
TSSOP-16
I2C Compatible,
TC < 50 ppm/°C
AD5262
2
± 5, +15
3-Wire
20, 50, 200
256
60
TSSOP-16
5 V to 15 V or ± 5 V
Operation,
TC < 50 ppm/°C
AD5203
4
5.5
3-Wire
10, 100
64
5
PDIP,
SOL-24,
TSSOP-24
Full ac Specs, nA
Shutdown Current
AD5233
4
± 2.75, +5.5
3-Wire
10, 50, 100
64
20
TSSOP-24
Nonvolatile Memory,
Direct Program, I/D,
± 6 dB settability
AD5204
4
± 3, +5.5
3-Wire
10, 50, 100
256
60
PDIP,
SOL-24,
TSSOP-24
Full ac Specs,
Dual Supply,
Power-On Reset
AD8403
4
5.5
3-Wire
1, 10, 50, 100
256
5
PDIP,
SOL-24,
TSSOP-24
Full ac Specs, nA
Shutdown Current
AD5206
6
± 3, +5.5
3-Wire
10, 50, 100
256
60
PDIP,
SOL-24,
TSSOP-24
Full AC specs,
Dual Supply,
Power-On Reset
–22–
Comments
REV. 0
AD5231
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. 0
0.0433 (1.10)
MAX
8
0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0
BSC
0.0075 (0.19) 0.0035 (0.090)
–23–
0.028 (0.70)
0.020 (0.50)
–24–
PRINTED IN U.S.A.
C02739–.8–10/01(0)