2-Channel, 2.35 V to 5.25 V 250 kSPS, 10-/12-Bit ADCs AD7911/AD7921 FUNCTIONAL BLOCK DIAGRAM FEATURES VDD Fast throughput rate: 250 kSPS Specified for VDD of 2.35 V to 5.25 V Low power: 4 mW typ at 250 kSPS with 3 V supplies 13.5 mW typ at 250 kSPS with 5 V supplies Wide input bandwidth: 71 dB minimum SNR at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface: SPI®/QSPI™/MICROWIRE™/DSP compatible Standby mode: 1 µA maximum 8-lead TSOT package 8-lead MSOP package VIN0 MUX VIN1 SCLK CS CONTROL LOGIC DOUT DIN 04350-0-001 AD7911/AD7921 GND APPLICATIONS Figure 1. Battery-powered systems: Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors GENERAL DESCRIPTION 1 The AD7911/AD7921 are 10-bit and 12-bit, high speed, low power, 2-channel successive approximation ADCs, respectively. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates of up to 250 kSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 6 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is also initiated at this point. There are no pipeline delays associated with the part. The channel to be converted is selected through the DIN pin, and the mode of operation is controlled by CS. The serial data stream from the DOUT pin has a channel identifier bit, which provides information about the converted channel. 1 10-/12-BIT SUCCESSIVE APPROXIMATION ADC T/H The AD7911/AD7921 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the part is taken internally from VDD, thereby allowing the widest dynamic input range to the ADC. The analog input range for the part, therefore, is 0 to VDD. The conversion rate is determined by the SCLK signal. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 2-channel, 250 kSPS, 10-/12-bit ADCs in TSOT package. Low power consumption. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock; conversion time is reduced when the serial clock speed is increased. The parts also feature a power-down mode to maximize power efficiency at lower throughput rates. Average power consumption is reduced when the powerdown mode is used while not converting. Current consumption is 1 µA maximum and 50 nA typically when in power-down mode. Reference derived from the power supply. No pipeline delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. Protected by U.S. Patent Number 6,681,332. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD7911/AD7921 TABLE OF CONTENTS Specifications..................................................................................... 3 Analog Input ............................................................................... 16 AD7911 Specifications................................................................. 3 Digital Inputs .............................................................................. 17 AD7921 Specifications................................................................. 5 DIN Input .................................................................................... 17 Timing Specifications .................................................................. 7 DOUT Output ............................................................................ 17 Timing Diagrams.......................................................................... 7 Modes of Operation ....................................................................... 18 Timing Examples.......................................................................... 8 Normal Mode.............................................................................. 18 Absolute Maximum Ratings............................................................ 9 Power-Down Mode .................................................................... 18 ESD Caution.................................................................................. 9 Power-Up Time .......................................................................... 19 Pin Configurations and Function Descriptions ......................... 10 Power vs. Throughput Rate....................................................... 20 Terminology .................................................................................... 11 Serial Interface ................................................................................ 21 Typical Performance Characteristics ........................................... 13 Microprocessor Interfacing....................................................... 22 Circuit Information ........................................................................ 15 Application Hints ........................................................................... 24 Converter Operation.................................................................. 15 Grounding and Layout .............................................................. 24 ADC Transfer Function............................................................. 15 Outline Dimensions ....................................................................... 25 Typical Connection Diagram ................................................... 16 Ordering Guide .......................................................................... 25 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7911/AD7921 SPECIFICATIONS AD7911 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C. VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Signal-to- Noise and Distortion (SINAD)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Offset Error2 Offset Error Match2, 3 Gain Error2 Gain Error Match2, 3 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Current, IIN, DIN Pin Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding A Grade1 Unit 61 −71 −72 dB min dB max dB max −82 −83 10 30 −90 8.5 1.5 dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ 10 ±0.5 ±0.5 ±0.5 ±0.3 ±0.5 ±0.3 ±0.5 Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max 0 to VDD ±0.3 20 V µA max pF typ 0.7 (VDD) 2 0.3 0.2 (VDD) 0.8 ±0.3 ±0.3 ±0.3 5 V min V min V max V max V max µA max µA max µA max pF max VDD − 0.2 0.2 ±0.3 5 V min V max µA max pF max Straight (natural) binary See notes at end of table. Rev. 0 | Page 3 of 28 Test Conditions/Comments fIN = 100 kHz sine wave fa = 100.73 kHz, fb = 90.7 kHz fa = 100.73 kHz, fb = 90.7 kHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 10 bits 2.35 V ≤ VDD ≤ 2.7 V 2.7 V < VDD ≤ 5.25 V VDD = 2.35 V 2.35 V < VDD ≤ 2.7 V 2.7 V < VDD ≤ 5.25 V VIN = 0 V or VDD ISOURCE = 200 µA, VDD = 2.35 V to 5.25 V ISINK = 200 µA AD7911/AD7921 Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation4 Normal Mode (Operational) Full Power-Down A Grade1 Unit Test Conditions/Comments 2.8 290 250 µs max ns max kSPS max 14 SCLK cycles with SCLK at 5 MHz 2.35/5.25 V min/max 3 1.5 4 2 1 0.38 0.2 mA typ mA typ mA max mA max µA max mA typ mA typ Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = 2.35 V to 3.6 V, SCLK on or off VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS SCLK on or off, typically 50 nA VDD = 5 V, fSCLK = 5 MHz, fSAMPLE = 25 kSPS VDD = 3 V, fSCLK = 5 MHz, fSAMPLE = 25 kSPS 20 6 5 mW max mW max µW max VDD = 5 V, fSAMPLE = 250 kSPS VDD = 3 V, fSAMPLE = 250 kSPS VDD = 5 V 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section. 2 Rev. 0 | Page 4 of 28 AD7911/AD7921 AD7921 SPECIFICATIONS Temperature range for A Grade from −40°C to +85°C. VDD = 2.35 V to 5.25 V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise and Distortion (SINAD)2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Term Aperture Delay Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Offset Error2 Offset Error Match2, 3 Gain Error2 Gain Error Match2, 3 Total Unadjusted Error (TUE)2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Current, IIN, DIN Pin Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding A Grade1 Unit 70 72 71 72.5 −81 −84 dB min dB typ dB min dB typ dB typ dB typ −84 −86 10 30 −90 8.5 1.5 dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ 12 ±1.5 −0.9/+1.5 ±1.5 ±0.5 ±0.5 ±2 ±0.3 ±1 ±1.5 Bits LSB max LSB max LSB max LSB typ LSB max LSB max LSB typ LSB max LSB max 0 to VDD ±0.3 20 V µA max pF typ 0.7 (VDD) 2 0.3 0.2 (VDD) 0.8 ±0.3 ±0.3 ±0.3 5 V min V min V max V max V max µA max µA max µA max pF max VDD − 0.2 0.2 ±0.3 5 V min V max µA max pF max Straight (natural) binary See notes at end of table. Rev. 0 | Page 5 of 28 Test Conditions/Comments fIN = 100 kHz sine wave fa = 100.73 kHz, fb = 90.72 kHz fa = 100.73 kHz, fb = 90.72 kHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 12 bits 2.35 V ≤ VDD ≤ 2.7 V 2.7 V < VDD ≤ 5.25 V VDD = 2.35 V 2.35 V < VDD ≤ 2.7 V 2.7 V < VDD ≤ 5.25 V VIN = 0 V or VDD ISOURCE = 200 µA; VDD = 2.35 V to 5.25 V ISINK = 200 µA AD7911/AD7921 Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode (Static) Full Power-Down Mode (Dynamic) Power Dissipation4 Normal Mode (Operational) Full Power-Down A Grade1 Unit Test Conditions/Comments 3.2 290 250 µs max ns max kSPS max 16 SCLK cycles with SCLK at 5 MHz 2.35/5.25 V min/max 3 1.5 4 2 1 0.4 0.22 mA typ mA typ mA max mA max µA max mA typ mA typ Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = 2.35 V to 3.6 V, SCLK on or off VDD = 4.75 V to 5.25 V, fSAMPLE = 250 kSPS VDD = 2.35 V to 3.6 V, fSAMPLE = 250 kSPS SCLK on or off, typically 50 nA VDD = 5 V, fSCLK = 5 MHz, fSAMPLE = 25 kSPS VDD = 3 V, fSCLK = 5 MHz, fSAMPLE = 25 kSPS 20 6 5 3 mW max mW max µW max µW max VDD = 5 V, fSAMPLE = 250 kSPS VDD = 3 V, fSAMPLE = 250 kSPS VDD = 5 V VDD = 3 V 1 Operational from VDD = 2 V, with VIH = 1.9 V minimum and VIL = 0.1 V maximum. See the Terminology section. 3 Guaranteed by characterization. 4 See the Power vs. Throughput Rate section. 2 Rev. 0 | Page 6 of 28 See the Serial Interface section AD7911/AD7921 TIMING SPECIFICATIONS Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter fSCLK1 tCONVERT tQUIET t1 t2 t33 t43 t5 t6 t74 t8 t9 t105 tPOWER-UP6 Limit at TMIN, TMAX 10 5 16 × tSCLK 14 × tSCLK 30 15 10 30 45 0.4 tSCLK 0.4 tSCLK 10 5 6 30 10 1 Unit kHz min2 MHz max Description AD7921 AD7911 Minimum quiet time required between bus relinquish and start of next conversion Minimum CS pulse width CS to SCLK setup time Delay from CS until DOUT three-state is disabled DOUT access time after SCLK falling edge SCLK low pulse width SCLK high pulse width SCLK to DOUT valid hold time DIN setup time prior to SCLK falling edge DIN hold time after SCLK falling edge SCLK falling edge to DOUT three-state SCLK falling edge to DOUT three-state Power-up time from full power-down ns min ns min ns min ns max ns max ns min ns min ns min ns min ns min ns max ns min µs max 1 Mark/space ratio for SCLK input is 40/60 to 60/40. Minimum fSCLK at which specifications are guaranteed. 3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage. 4 Measured with a 50 pF load capacitor. 5 T10 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 See the Power-Up Time section. 2 TIMING DIAGRAMS 200µA t7 IOL SCLK 1.6V CL 50pF 200µA IOH 04350-0-004 VIH DOUT 04350-0-002 TO OUTPUT PIN VIL Figure 4. Hold Time after SCLK Falling Edge Figure 2. Load Circuit for Digital Output Timing Specifications t10 t4 SCLK VIL 1.6V DOUT Figure 3. Access Time after SCLK Falling Edge Figure 5. SCLK Falling Edge to DOUT Three-State Rev. 0 | Page 7 of 28 04350-0-005 VIH DOUT 04350-0-003 SCLK AD7911/AD7921 TIMING EXAMPLES Timing Example 2 Figure 6 and Figure 7 show some of the timing parameters from the Timing Specifications section. The AD7921 can also operate with slower clock frequencies. As shown in Figure 7, when fSCLK = 2 MHz and the throughput rate is 100 KSPS, the cycle time is Timing Example 1 t2 + 12.5(1/fSCLK) + tACQ = 10 µs As shown in Figure 7, when fSCLK = 5 MHz and the throughput is 250 kSPS, the cycle time is With t2 = 10 ns minimum, then tACQ is 3.74 µs, which satisfies the requirement of 290 ns for tACQ. t2 + 12.5(1/fSCLK) + tACQ = 4 µs In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where t10 = 30 ns maximum. This allows a value of 2.46 µs for tQUIET, satisfying the minimum requirement of 30 ns. With t2 = 10 ns minimum, then tACQ is 1.49 µs, which satisfies the requirement of 290 ns for tACQ. In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where t10 = 30 ns maximum. This allows a value of 960 ns for tQUIET, satisfying the minimum requirement of 30 ns. In this example, as with other slower clock values, the signal might already be acquired before the conversion is complete, but it is still necessary to leave 30 ns minimum tQUIET between conversions. In this example, the signal should be fully acquired at approximately point C in Figure 7. t1 CS tCONVERT 1 SCLK 2 3 4 Z DOUT ZERO CHN X X 13 14 15 16 t5 t7 DB11 t8 THREE-STATE X 5 t4 t3 DIN B t6 DB10 DB2 t10 DB1 DB0 THREE-STATE t9 CHN X X X X X tQUIET X 04350-0-006 t2 Figure 6. AD7921 Serial Interface Timing Diagram CS SCLK 1 2 3 4 5 B 13 C 14 15 16 t10 tQUIET tACQUISITION 12.5(1/fSCLK) 1/THROUGHPUT Figure 7. Serial Interface Timing Example Rev. 0 | Page 8 of 28 04350-0-007 tCONVERT t2 AD7911/AD7921 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin except Supplies1 Operating Temperature Range Commercial (A Grade) Storage Temperature Range Junction Temperature TSOT Package θJA Thermal Impedance MSOP Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature Soldering Reflow (10 s to 30 s) ESD 1 Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −40°C to +85°C −65°C to +150°C 150°C 207°C/W 205.9°C/W 43.74°C/W 235 (0/+5)°C 2 kV Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 9 of 28 AD7911/AD7921 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SCLK 2 CS 3 DOUT 4 AD7911/ AD7921 8-LEAD MSOP 8 VIN1 DOUT 1 7 VIN0 CS 2 6 GND SCLK 3 DIN 4 TOP VIEW (Not to Scale) 5 VDD 04350-0-008 1 Figure 8. 8-Lead TSOT Pin Configuration AD7911/ AD7921 8 VDD 7 GND VIN0 TOP VIEW (Not to Scale) 5 VIN1 6 04350-0-034 8-LEAD TSOT DIN Figure 9. 8-Lead MSOP Pin Configuration Table 5. Pin Function Descriptions TSOT Pin No. 1 MSOP Pin No. 4 Mnemonic DIN 2 3 SCLK 3 2 CS 4 1 DOUT 5 6 8 7 VDD GND 7, 8 6, 5 VIN0, VIN1 Function Data In. Logic input. The channel to be converted is provided on this input and is clocked into an internal register on the falling edge of SCLK. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7911/AD7921’s conversion process. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7911/AD7921 and framing the serial data transfer. Data Out. Logic output. The conversion result from the AD7911/AD7921 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK signal. For the AD7921, the data stream consists of two leading zeros; the channel identifier bit, which identifies the channel that the conversion result corresponds to; followed by an invalid bit that matches up to the channel identifier bit; followed by the 12 bits of conversion data, with MSB first. For the AD7911, the data stream consists of two leading zeros; the channel identifier bit, which identifies the channel that the conversion result corresponds to; followed by an invalid bit that matches up to the channel identifier bit; followed by the 10 bits of conversion data, with MSB first and two trailing zeros. Power Supply Input. The VDD range for the AD7911/AD7921 is from 2.35 V to 5.25 V. Analog Ground. Ground reference point for all circuitry on the AD7911/AD7921. All analog input signals should be referred to this GND voltage. Analog Inputs. These two single-ended analog input channels are multiplexed into the on-chip trackand-hold amplifier. The analog input channel to be converted is selected by writing to the third MSB on the DIN pin. The input range is 0 to VDD. Rev. 0 | Page 10 of 28 AD7911/AD7921 TERMINOLOGY Integral Nonlinearity Signal-to-Noise and Distortion Ratio (SINAD) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7911/ AD7921, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. The measured ratio of signal-to-noise and distortion at the output of the A/D converter. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fs/2), including harmonics but excluding dc. Differential Nonlinearity Signal-to-Noise Ratio (SNR) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. The measured ratio of signal to noise at the output to the A/D converter. The signal is the rms value of the sine wave input. Noise is the rms quantization error within the Nyquist bandwidth (fs/2). The rms value of a sine wave is one-half its peak-to-peak value divided by √2, and the rms value for the quantization noise is q/√12. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. For an ideal N-bit converter, the SNR is defined as Offset Error The deviation of the first code transition (00…000) to (00…001) from the ideal, that is, AGND + 1 LSB. Offset Error Match The difference in offset error between any two channels. SNR = 6.02 N + 1.76 dB Gain Error The deviation of the last code transition (111…110) to (111…111) from the ideal, that is, VREF − 1 LSB after the offset error has been adjusted out. Therefore, for a 12-bit converter, SNR is 74 dB; for a 10-bit converter, SNR is 62 dB. The difference in gain error between any two channels. However, various error sources in the ADC cause the measured SNR to be less than the theoretical value. These errors occur due to integral and differential nonlinearities, internal ac noise sources, and so on. Total Unadjusted Error Total Harmonic Distortion (THD) A comprehensive specification that includes gain error, linearity error, and offset error. The ratio of the rms sum of harmonics to the fundamental, which is defined as Gain Error Match Channel-to-Channel Isolation THD (dB) = 20 log V 2 2 + V3 2 + V 4 2 + V 5 2 + V6 2 V1 A measure of the level of crosstalk between channels. It is measured by applying a full-scale sine wave signal of 20 kHz to 500 kHz to the nonselected input channel and determining how much that signal is attenuated in the selected channel with a 10 kHz signal. The figure is given worst case across both channels for the AD7911/AD7921. V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Track-and-Hold Acquisition Time Peak Harmonic or Spurious Noise The time required for the output of the track-and-hold amplifier to reach its final value within ±1 LSB after the end of conversion. The track-and-hold amplifier returns to track mode at the end of conversion. See the Serial Interface section for more details. The ratio of the rms value of the next largest component in the ADC output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. where: Rev. 0 | Page 11 of 28 AD7911/AD7921 Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7911/AD7921 are tested using the CCIF standard, where two input frequencies are used (see fa and fb in the Specifications section). In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second-order and thirdorder terms are specified separately. The calculation of the intermodulation distortion is as in the THD specification, where it is defined as the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB. Rev. 0 | Page 12 of 28 AD7911/AD7921 TYPICAL PERFORMANCE CHARACTERISTICS Figure 10 and Figure 11 show typical FFT plots for the AD7921 and AD7911, respectively, at a 250 kSPS sample rate and 100 kHz input frequency. Figure 14 and Figure 15 show INL and DNL performance for the AD7921. Figure 12 shows the SINAD ratio performance versus the input frequency for various supply voltages while sampling at 250 kSPS with a SCLK frequency of 5 MHz for the AD7921. Figure 16 shows a graph of the total harmonic distortion versus the analog input frequency for different source impedances when using a supply voltage of 3.6 V and a sampling rate of 250 kSPS. See the Analog Input section. Figure 13 shows the SNR ratio performance versus the input frequency for various supply voltages while sampling at 250 kSPS with an SCLK frequency of 5 MHz for the AD7921. Figure 17 shows a graph of the total harmonic distortion versus the analog input frequency for various supply voltages while sampling at 250 kSPS with an SCLK frequency of 5 MHz. Figure 18 shows the shutdown current versus the voltage supply for different operating temperatures. 5 –70.5 8192 POINT FFT VDD = 2.7V FSAMP = 250kSPS FIN = 100kHz SNR = 73.13dB SINAD = 72.73dB THD = –83.30dB SFDR = –86.15dB VDD = 4.75V –55 –72.0 VDD = 2.35V –72.5 –75 VDD = 3.6V –73.5 04350-0-009 –95 –115 20 40 60 80 FREQUENCY (kHz) 100 Figure 10. AD7921 Dynamic Performance at 250 kSPS 5 1k –72.0 –72.2 VDD = 2.35V –72.4 SNR (dB) –72.6 –55 –72.8 VDD = 5.25V VDD = 4.75V –73.0 –75 –73.2 –95 04350-0-010 SNR (dB) –35 100 FREQUENCY (kHz) Figure 12. AD7921 SINAD vs. Input Frequency at 250 kSPS 8192 POINT FFT VDD DD = 2.7V FSAMP SAMP = 250kSPS FIN IN = 100kHz 61.75dB SNR = 73.13dB 61.74dB SINAD = 72.73dB THD = –83.30dB –86.24dB –84.46dB SFDR = –86.15dB –15 VDD = 2.7V –74.0 10 120 04350-0-011 –73.0 0 VDD = 5.25V –71.5 –115 0 20 40 60 80 FREQUENCY (kHz) 100 VDD = 3.6V 04350-0-012 SNR (dB) –35 –71.0 SINAD (dB) –15 –73.4 VDD = 2.7V –73.6 10 120 Figure 11. AD7911 Dynamic Performance at 250 kSPS 100 FREQUENCY (kHz) Figure 13. AD7921 SNR vs. Input Frequency at 250 kSPS Rev. 0 | Page 13 of 28 1k AD7911/AD7921 1.0 –74 VDD = 2.7V FSAMP = 250kSPS TEMPERATURE = 25°C 0.8 0.6 VDD = 4.75V –78 0.4 0.2 THD (dB) INL ERROR (LSB) VDD = 5.25V –76 0 –0.2 –80 VDD = 2.7V –82 VDD = 2.35V –0.4 –84 –0.6 –1.0 0 512 1024 1536 2048 CODE 2560 3072 3584 VDD = 3.6V –88 10 4096 Figure 14. AD7921 INL Performance 1k 180 VDD = 2.7V FSAMP = 250kSPS TEMPERATURE = 25°C 0.8 160 SHUTDOWN CURRENT (nA) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 140 TEMPERATURE = +85°C 120 100 80 60 40 04350-0-014 TEMPERATURE = +25°C –0.8 –1.0 0 512 1024 1536 2048 CODE 2560 3072 3584 20 TEMPERATURE = –40°C 0 2.0 4096 Figure 15. AD7921 DNL Performance VDD = 3.6V –35 RIN = 1kΩ –45 –55 RIN = 500Ω RIN = 100Ω RIN = 50Ω 04350-0-015 –75 –85 –95 10 RIN = 0Ω RIN = 10Ω 100 FREQUENCY (kHz) 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 Figure 18. Shutdown Current vs. Supply Voltage –25 –65 04350-0-017 DNL ERROR (LSB) 100 FREQUENCY (kHz) Figure 17. THD vs. Analog Input Frequency for Various Supply Voltages 1.0 THD (dB) 04350-0-016 –86 04350-0-013 –0.8 1k Figure 16. THD vs. Analog Input Frequency for Various Source Impedances Rev. 0 | Page 14 of 28 5.5 AD7911/AD7921 CIRCUIT INFORMATION The AD7911/AD7921 feature a power-down option that allows power saving between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. CONVERTER OPERATION The AD7911/AD7921 are 10-/12-bit successive approximation ADCs based around a charge redistribution DAC. Figure 19 and Figure 20 show simplified schematics of the ADC. Figure 19 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on the selected VIN channel. CHARGE REDISTRIBUTION DAC ACQUISITION PHASE VDD/2 COMPARATOR AGND 04350-0-019 COMPARATOR Figure 20. ADC Conversion Phase ADC TRANSFER FUNCTION The output coding of the AD7911/AD7921 is straight binary. The designed code transitions occur at the successive integer LSB values, that is, 1 LSB, 2 LSB, and so on. The LSB size is VDD/4096 for the AD7921 and VDD/1024 for the AD7911. The ideal transfer characteristic for the AD7911/AD7921 is shown in Figure 21. 111...111 111...110 111...000 011...111 1LSB = VDD/4096 (AD7921) 1LSB = VDD/1024 (AD7911) 000...010 000...001 000...000 0V 1LSB SW2 CONTROL LOGIC SW2 VDD/2 CONTROL LOGIC +VDD – 1LSB ANALOG INPUT 04350-0-018 VIN1 SW1 B CONVERSION PHASE AGND SAMPLING CAPACITOR A SW1 B VIN1 CHARGE REDISTRIBUTION DAC VIN0 SAMPLING CAPACITOR A VIN0 Figure 19. ADC Acquisition Phase Rev. 0 | Page 15 of 28 Figure 21. AD7911/AD7921 Transfer Characteristic 04350-0-020 The AD7911/AD7921 provide the user with an on-chip trackand-hold, an ADC, and a serial interface, all housed in a tiny 8lead TSOT package or an 8-lead MSOP package, which offer the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the parts, controls the transfer of data written to the ADC, and provides the clock source for the successive approximation ADC. The analog input range is 0 to VDD. An external reference is not required for the ADC, and neither is there a reference on-chip. The reference for the AD7911/AD7921 is derived from the power supply and, therefore, gives the widest dynamic input range. When the ADC starts a conversion (see Figure 20), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 21 shows the ADC transfer function. ADC CODE The AD7911/AD7921 are fast, 2-channel, 10-/12-bit, single supply, analog-to-digital converters (ADCs), respectively. The parts can be operated from a 2.35 V to 5.25 V supply. When operated from either a 5 V supply or a 3 V supply, the AD7911/AD7921 are capable of throughput rates of 250 kSPS when provided with a 5 MHz clock. AD7911/AD7921 Figure 22 shows a typical connection diagram for the AD7911/ AD7921. VREF is taken internally from VDD and as such VDD should be well decoupled. This provides an analog input range of 0 V to VDD. The conversion result is output in a 16-bit word with two leading zeros, followed by the channel identifier bit that identifies the channel converted, followed by an invalid bit that matches up to the channel converted, followed by the MSB of the 12-bit or 10-bit result. For the AD7911, the 10-bit result is followed by two trailing zeros. See the Serial Interface section. Alternatively, because the supply current required by the AD7911/AD7921 is so low, a precision reference can be used as the supply source to the AD7911/AD7921. A REF19x voltage reference (REF195 for 5 V or REF193 for 3 V) can be used to supply the required voltage to the ADC (see Figure 22). This configuration is especially useful, if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V (for example, 15 V). The REF19x outputs a steady voltage to the AD7911/AD7921. If the low dropout REF193 is used, the current it needs to supply to the AD7911/ AD7921 is typically 1.5 mA. When the ADC is converting at a rate of 250 kSPS, the REF193 needs to supply a maximum of 2 mA to the AD7911/AD7921. The load regulation of the REF193 is typically 10 ppm/mA (REF193, VS = 5 V), which results in an error of 20 ppm (60 µV) for the 2 mA drawn from it. This corresponds to a 0.082 LSB error for the AD7921 with VDD = 3 V from the REF193 and a 0.061 LSB error for the AD7911. For applications where power consumption is a concern, the power-down mode of the ADC and the sleep mode of the REF19x reference should be used to improve power performance. See the Modes of Operation section. 3V 1.5mA 0.1µF 5V SUPPLY REF193 1µF TANT 10µF 0.1µF 680nF VDD VIN0 VIN1 GND AD7911/ AD7921 SCLK CS DIN DOUT µC/µP 04350-0-021 0V TO VDD INPUT SERIAL INTERFACE Figure 22. REF193 as Power Supply to AD7911/AD7921 Table 6 provides some typical performance data with various references used as a VDD source and a 50 kHz input tone under the same setup conditions. Table 6. AD7921 Performance for Various Voltage References IC Reference Tied to VDD AD780 at 3 V REF193 ADR433 AD780 at 2.5 V REF192 ADR421 AD7921 SNR Performance (dB) −73 −72.42 −72.9 −72.86 −72.27 −72.75 ANALOG INPUT Figure 23 shows an equivalent circuit of the analog input structure of the AD7911/AD7921. The two diodes, D1 and D2, provide ESD protection for the analog input. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV, because this would cause these diodes to become forward biased and start conducting current into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the part is 10 mA. VDD D1 R1 VIN C1 6pF C2 20pF D2 CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED 04350-0-022 TYPICAL CONNECTION DIAGRAM Figure 23. Equivalent Analog Input Circuit The capacitor C1 in Figure 23 is typically about 6 pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a trackand-hold switch and also includes the on resistance of the input multiplexer. This resistor is typically about 100 Ω. The capacitor C2 is the ADC sampling capacitor and has a capacitance of 20 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended using a band-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances can significantly affect the ac performance of the ADC. This might necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Rev. 0 | Page 16 of 28 AD7911/AD7921 Table 7 provides some typical performance data with various op amps used as the input buffer, and a 50 kHz input tone under the same setup conditions. Table 7. AD7921 Performance for Various Input Buffers AD7921 SNR Performance (dB) 50 kHz Input , VDD = 3.6 V The channel to be converted on in the next conversion is selected by writing to the DIN pin. Data on the DIN pin is loaded into the AD7911/AD7921 on the falling edge of SCLK. The data is transferred into the part on the DIN pin at the same time that the conversion result is read from the part. Only the third bit of the DIN word is used; the rest are ignored by the ADC. The third MSB is the channel identifier bit, which identifies the channel to be converted on in the next conversion, VIN0 (CHN = 0) or VIN1 (CHN = 1). −72.68 −72.88 MSB X When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades (see Figure 16). DIGITAL INPUTS The digital inputs applied to the AD7911/AD7921 are not limited by the maximum ratings that limit the analog input. Instead, the digital inputs applied can go to 7 V and are not restricted by the VDD + 0.3 V limit as on the analog input. For example, if the AD7911/AD7921 are operated with a VDD of 3 V, then 5 V logic levels could be used on the digital inputs. However, it is important to note that the data output on DOUT still has 3 V logic levels when VDD = 3 V. Another advantage of SCLK, DIN, and CS not being restricted by the VDD + 0.3 V limit is that power supply sequencing issues are avoided. If CS, DIN, or SCLK are applied before VDD, then there is no risk of latch-up as there would be on the analog inputs, if a signal greater than 0.3 V were applied prior to VDD. LSB X CHN X DON'T CARE Figure 24. AD7911/AD7921 DIN Word DOUT OUTPUT The conversion result from the AD7911/AD7921 is provided on this output as a serial data stream. The bits are clocked out on the SCLK falling edge at the same time that the conversion is taking place. The serial data stream for the AD7921 consists of two leading zeros followed by the bit that identifies the channel converted, an invalid bit that matches up to the channel identifier bit, and the 12-bit conversion result with MSB provided first. For the AD7911, the serial data stream consists of two leading zeros followed by the bit that identifies the channel converted, an invalid bit that matches up to the channel identifier bit, and the 10-bit conversion result with MSB provided first, followed by two trailing zeros. MSB LSB 0 0 CHN X 0 0 CHN X CONVERSION RESULT 0 0 CONVERSION RESULT Figure 25. AD7911/AD7921 DOUT Word Rev. 0 | Page 17 of 28 AD7911 AD7921 04350-0-024 −72.79 −72.35 −72.2 04350-0-023 Op Amp in the Input Buffer Single op amps AD8038 AD8510 AD8021 Dual op amps AD712 AD8022 DIN INPUT AD7911/AD7921 MODES OF OPERATION The two modes of operation of the AD7911/AD7921 are normal mode and power-down mode. The mode of operation is selected by controlling the logic state of the CS signal. The point at which CS is pulled high after the conversion has been initiated determines whether the AD7911/AD7921 enter powerdown mode. Similarly, if already in power-down mode, CS can control whether the device returns to normal operation or remains in power-down mode. Power-down mode is designed to provide flexible power management options and to optimize the ratio of power dissipation to throughput rate for different application requirements. POWER-DOWN MODE Power-down mode is intended for use in applications where slower throughput rates are required. Either the ADC is powered down between each conversion, or a series of conversions can be performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7911/AD7921 are in power-down mode, all analog circuitry is powered down. To enter power-down mode, the conversion process must be interrupted by bringing CS high any time after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 27. Once CS has been brought high in this window of SCLKs, then the part enters power-down mode, the conversion that was initiated by the falling edge of CS is terminated, and DOUT goes back into three-state. If CS is brought high before the second SCLK falling edge, then the part remains in normal mode and does not power down. This helps to avoid accidental power-down due to glitches on the CS line. NORMAL MODE Normal mode is intended for the fastest throughput rate performance. The user does not have to worry about any power-up time, because the AD7911/AD7921 remain fully powered all the time. Figure 26 shows the operation of the AD7911/AD7921 in this mode. The conversion is initiated on the falling edge of CS, as described in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge but before the end of tCONVERT, the part remains poweredup, but the conversion is terminated and DOUT goes back into three-state. For the AD7911/AD7921, a minimum of 14 and 16 serial clock cycles, respectively, are needed to complete the conversion and access the complete conversion result. CS can idle high until the next conversion or can idle low until CS returns high sometime prior to the next conversion (effectively idling CS low). Once a data transfer is complete (DOUT has returned to three-state), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. To exit this mode of operation and power the AD7911/AD7921 up again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up once 16 SCLKs have elapsed and valid data results from the next conversion, as shown in Figure 28. If CS is brought high before the 10th falling edge of SCLK, then the AD7911/AD7921 go back into powerdown mode. This helps to avoid accidental power-up due to glitches on the CS line or an inadvertent burst of 8 SCLK cycles while CS is low. Therefore, although the device might begin to power up on the falling edge of CS, it powers down again on the rising edge of CS, as long as this occurs before the 10th SCLK falling edge. AD7911/AD7921 CS 1 10 12 14 16 1 10 12 14 16 DIN DOUT CHANNEL FOR NEXT CONVERSION CHANNEL FOR NEXT CONVERSION CONVERSION RESULT CONVERSION RESULT Figure 26. Normal Mode Operation Rev. 0 | Page 18 of 28 04350-0-025 SCLK AD7911/AD7921 CS 1 2 10 16 SCLK INVALID DATA DOUT INVALID DATA THREE-STATE 04350-0-026 THREE-STATE DIN Figure 27. Entering Power- Down Mode THE PART BEGINS TO POWER UP THE PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED THE PART GOES INTO TRACK CS 1 A5 10 16 1 16 DIN DOUT CHANNEL FOR NEXT CONVERSION CHANNEL FOR NEXT CONVERSION INVALID DATA CONVERSION RESULT 04350-0-027 SCLK Figure 28. Exiting Power-Down Mode POWER-UP TIME The power-up time of the AD7911/AD7921 is 1 µs, which means that with any frequency of SCLK up to 5 MHz, one dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully powered up and the input signal is acquired properly. The quiet time, tQUIET, must still be allowed from the point at which the bus goes back into three-state after the dummy conversion to the next falling edge of CS. When running at a 250 kSPS throughput rate, the AD7911/AD7921 power up and acquire a signal within ±1 LSB in one dummy cycle. When powering up from power-down mode with a dummy cycle, as in Figure 28, the track-and-hold that was in hold mode while the part was powered down returns to track mode on the fifth SCLK falling edge that the part receives after the falling edge of CS. This is shown as point A in Figure 28. At this point, the part starts to acquire the signal on the channel selected in the current dummy conversion. Although at any SCLK frequency one dummy cycle is sufficient to power up the device and acquire VIN, it does not necessarily mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire VIN fully. 1µs is sufficient to power up the device and acquire the input signal. For example, if a 5 MHz SCLK frequency was applied to the ADC, the cycle time would be 3.2 µs. In one dummy cycle, 3.2 µs, the part would be powered up and VIN acquired fully. However, after 1 µs with a 5 MHz SCLK, only 5 SCLK cycles would have elapsed. At this stage, the ADC would be fully powered up. In this case, CS can be brought high after the 10th SCLK falling edge and brought low again after a time, tQUIET, to initiate the conversion. When power supplies are first applied to the AD7911/AD7921, the ADC can power up in either power-down mode or normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. Likewise, if the user wants to keep the part in power-down mode while not in use and to power up in power-down mode, then the dummy cycle can be used to ensure that the device is in power-down mode by executing a cycle such as that shown in Figure 27. Once supplies are applied to the AD7911/AD7921, the powerup time is the same as when powering up from the power-down mode. It takes the part approximately 1 µs to power up fully in normal mode. It is not necessary to wait 1 µs before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. When the ADC powers up initially after supplies are applied, the track-and-hold is in hold. It returns to track on the fifth SCLK falling edge that the part receives after the falling edge of CS. Rev. 0 | Page 19 of 28 AD7911/AD7921 By using the power-down mode on the AD7911/AD7921 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 29 shows how, as the throughput rate is reduced, the device remains in its powerdown state longer and the average power consumption over time drops accordingly. For example, if the AD7911/AD7921 are operating in a continuous sampling mode with a throughput rate of 50 kSPS and a SCLK of 5 MHz (VDD = 5 V) and the devices are placed in power-down mode between conversions, then the power consumption is calculated as follows. The power dissipation during normal operation is 20 mW (VDD = 5 V). If one dummy cycle powers up the part between conversions (3.2 µs), and the remaining conversion time is another cycle (3.2 µs), then the AD7911/AD7921 dissipate 20 mW for 6.4 µs during each conversion cycle. If the throughput rate is 50 kSPS and the cycle time is 20 µs, then the average power dissipated during each cycle is In the previous examples, the power dissipation when the part is in power-down mode has not been taken into account, because the shutdown current is so low that it does not have any effect on the overall power dissipation value. Figure 29 shows the power consumption versus throughput rate when using the power-down mode between conversions with both 5 V and 3 V supplies. Power-down mode is intended for use with throughput rates of approximately 120 kSPS and under, because higher sampling rates do not have a power saving in power-down mode. 100 VDD = 5V, SCLK = 5MHz 10 POWER (mW) POWER VS. THROUGHPUT RATE VDD = 3V, SCLK = 5MHz 1 0.1 If VDD = 3 V, SCLK= 5 MHz, and the device is again in powerdown mode between conversions, then the power dissipation during normal operation is 6 mW. The AD7911/AD7921 now dissipate 6 mW for 6.4 µs during each conversion cycle. With a throughput rate of 50 kSPS, the average power dissipated during each cycle is (6.4/20) × (6 mW) = 1.92 mW Rev. 0 | Page 20 of 28 04350-0-035 (6.4/20) × (20 mW) = 6.4 mW 0.01 0 15 30 45 60 75 90 THROUGHPUT (kSPS) 105 120 Figure 29. Power Consumption vs. Throughput Rate 135 AD7911/AD7921 SERIAL INTERFACE Figure 30 and Figure 31 show the detailed timing diagrams for serial interfacing to the AD7921 and AD7911, respectively. The serial clock provides the conversion clock and also controls the transfer of information from the AD7911/AD7921 during conversion. If the rising edge of CS occurs before 14 SCLKs have elapsed, then the conversion is terminated and the DOUT line goes back into three-state. If 16 SCLKs are considered in the cycle, DOUT returns to three-state on the 16th SCLK falling edge, as shown in Figure 31. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state, the analog input is sampled at this point, and the conversion is initiated. CS going low clocks out the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the second leading zero. Therefore, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. For the AD7921, the conversion requires 16 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the trackand-hold goes back into track on the next SCLK rising edge, as shown in Figure 30 at Point B. On the 16th SCLK falling edge, the DOUT line goes back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, then the conversion is terminated and the DOUT line goes back into three-state. Otherwise, DOUT returns to three-state on the 16th SCLK falling edge, as shown in Figure 30. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7921. For the AD7911, the conversion requires 14 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the trackand-hold goes back into track on the next SCLK rising edge, as shown in Figure 31 at Point B. In applications with a slower SCLK, it is possible to read in data on each SCLK rising edge. In that case, the first falling edge of SCLK clocks out the second leading zero and it can be read in the first rising edge. However, the first leading zero that is clocked out when CS goes low is missed, unless it is not read in the first falling edge. The 15th falling edge of SCLK clocks out the last bit and it can be read in the 15th rising SCLK edge. If CS goes low just after the SCLK falling edge has elapsed, CS clocks out the first leading zero as before and it can be read in the SCLK rising edge. The next SCLK falling edge clocks out the second leading zero and it can be read in the following rising edge. t1 CS tCONVERT 1 SCLK 2 3 4 ZERO CHN X X X 13 14 15 16 t5 t7 DB11 t8 THREE-STATE DIN 5 t4 t3 Z DOUT B t6 DB10 DB2 t10 DB1 THREE-STATE t9 CHN tQUIET DB0 04350-0-029 t2 X X X X X X Figure 30. AD7921 Serial Interface Timing Diagram t1 CS tCONVERT t6 1 SCLK 2 3 X 5 X CHN X DB9 t8 CHN 13 DB8 X 15 16 t5 t9 X 14 t7 t4 t3 Z ZERO DOUT THREE-STATE DIN B 4 t10 tQUIET DB0 ZERO ZERO TWO TRAILING ZEROS THREE-STATE X X X Figure 31. AD7911 Serial Interface Timing Diagram Rev. 0 | Page 21 of 28 X 04350-0-030 t2 AD7911/AD7921 MICROPROCESSOR INTERFACING AD7911/AD7921 to TMS320C541 Interface The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7911/AD7921. The CS input allows easy interfacing between the TMS320C541 and the AD7911/AD7921 without any glue logic required. The serial port of the TMS320C541 is set up to operate in burst mode (FSM = 1 in the serial port control register, SPC) with the internal serial clock CLKX (MCM = 1 in the SPC register) and the internal frame signal (TXM = 1 in the SPC register); therefore, both pins are configured as outputs. For the AD7921, the word length should be set to 16 bits (FO = 0 in the SPC register). This DSP allows frames with a word length of 16 bits or 8 bits only. In the AD7911, therefore, where 14 bits are required, the FO bit should be set up to 16 bits, and 16 SCLKs are needed. For the AD7911, two trailing zeros are clocked out in the last two clock cycles. The values in the SPC register are as follows: FO = 0 FSM = 1 MCM = 1 TXM = 1 AD7911/AD7921 to ADSP-218x The ADSP-218x family of DSPs are interfaced directly to the AD7911/AD7921 without any glue logic required. The SPORT control register should be set up as follows: TFSW = RFSW = 1, alternate framing INVRFS = INVTFS = 1, active low frame signal DTYPE = 00, right-justify data ISCLK = 1, internal serial clock TFSR = RFSR = 1, frame every word IRFS = 0, set up RFS as an input ITFS = 1, set up TFS as an output SLEN = 1111, 16 bits for the AD7921 SLEN = 1101, 14 bits for the AD7911 To implement the power-down mode, SLEN should be set to 0111 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 33. The ADSP-218x has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described previously. The frame synchronization signal generated on the TFS is tied to CS and, as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC and, under certain conditions, equidistant sampling might not be achieved. ADSP-218x* AD7911/ AD7921* To implement the power-down mode on the AD7911/AD7921, the format bit, FO, can be set to 1, which sets the word length to 8 bits. The connection diagram is shown in Figure 32. Note that, for signal processing applications, the frame synchronization signal from the TMS320C541 must provide equidistant sampling. SCLK SCLK DOUT DR DIN DT CS RFS TFS 04350-0-032 The serial interface on the AD7911/AD7921 allows the parts to be directly connected to a range of microprocessors. This section explains how to interface the AD7911/AD7921 with some of the more common microcontroller and DSP serial interface protocols. *ADDITIONAL PINS OMITTED FOR CLARITY Figure 33. Interfacing to the ADSP-218x TMS320C541* AD7911/ AD7921* SCLK CLKX DOUT DR DIN DX CS FSX FSR *ADDITIONAL PINS OMITTED FOR CLARITY Figure 32. Interfacing to the TMS320C541 04350-0-031 CLKR The timer registers are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and, therefore, the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, that is, TX0 = AX0, the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high again before transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data might be transmitted, or it might wait until the next clock edge. Rev. 0 | Page 22 of 28 AD7911/AD7921 AD7911/AD7921 to DSP563xx Interface The connection diagram in Figure 34 shows how the AD7911/ AD7921 can be connected to the SSI (synchronous serial interface) of the DSP563xx family of DSPs from Motorola. The SSI is operated in synchronous and normal mode (SYN = 1 and MOD = 0 in the Control Register B, CRB) with internally generated word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in the CRB). Set the word length in the Control Register A (CRA) to 16 by setting Bits WL2 = 0, WL1 = 1, and WL0 = 0 for the AD7921. This DSP does not offer the option for a 14-bit word length, so the AD7911 word length is set up to 16 bits like the AD7921. For the AD7911, the conversion process uses 16 SCLK cycles, with the last two clock periods clocking out two trailing zeros to fill the 16-bit word. To implement the power-down mode on the AD7911/AD7921, the word length can be changed to 8 bits by setting Bits WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the CRB register can be set to 1, which means that the frame goes low and a conversion starts. Likewise, by means of the Bits SCD2, SCKD, and SHFD in the CRB register, the Pin SC2 (the frame sync signal) and SCK in the serial port are configured as outputs, and the MSB is shifted first. The values are as follows: MOD = 0 SYN = 1 WL2, WL1, WL0 depend on the word length FSL1 = 0, FSL0 = 0 FSP = 1, negative frame sync SCD2 = 1 SCKD = 1 SHFD = 0 Note that, for signal processing applications, the frame synchronization signal from the DSP563xx must provide equidistant sampling. DSP563xx* AD7911/ AD7921* SCLK SCK DOUT SRD DIN STD CS SC2 *ADDITIONAL PINS OMITTED FOR CLARITY Rev. 0 | Page 23 of 28 Figure 34. Interfacing to the DSP563xx 04350-0-033 For example, the ADSP-2189 has a master clock frequency of 40 MHz. If the SCLKDIV register is loaded with the value of 3, then an SCLK of 5 MHz is obtained, and eight master clock periods elapse for every one SCLK period. Depending on the throughput rate selected, if the timer register is loaded with the value 803 (803 + 1 = 804), then 100.5 SCLK occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling, because the transmit instruction occurs on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, then equidistant sampling is implemented by the DSP. AD7911/AD7921 APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7911/AD7921 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes, because it gives the best shielding. Digital and analog ground planes should be joined at only one place. If the AD7911/ AD7921 is in a system where multiple devices require an AGND-to-DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7911/AD7921. Avoid running digital lines under the device, because these couple noise onto the die. The analog ground plane should be allowed to run under the AD7911/AD7921 to avoid noise coupling. The power supply lines to the AD7911/AD7921 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast-switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also very important. The analog supply should be decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors to AGND. To achieve the best performance from these decoupling components, the user should endeavor to keep the distance between the decoupling capacitor and the VDD and GND pins to a minimum with short track lengths connecting the respective pins. Rev. 0 | Page 24 of 28 AD7911/AD7921 OUTLINE DIMENSIONS 2.90 BSC 3.00 BSC 8 5 4.90 BSC 3.00 BSC 8 7 6 5 1 2 3 4 1.60 BSC 4 2.80 BSC PIN 1 0.65 BSC PIN 1 0.90 0.87 0.84 0.65 BSC 1.10 MAX 0.15 0.00 1.95 BSC 1.00 MAX 0.38 0.22 COPLANARITY 0.10 0.23 0.08 0.80 0.60 0.40 8° 0° 0.10 MAX SEATING PLANE 0.38 0.22 0.20 0.08 0.55 0.45 0.35 8° 4° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-193BA COMPLIANT TO JEDEC STANDARDS MO-187AA Figure 35. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Figure 36. 8-Lead Thin Small Outline Transistor Package [TSOT] (UJ-8) Dimensions shown in millimeters ORDERING GUIDE Model AD7911ARM AD7911ARM-REEL AD7911ARM-REEL7 AD7911AUJ-R2 AD7911AUJ-REEL7 AD7921ARM AD7921ARM-REEL AD7921ARM-REEL7 AD7921AUJ-R2 AD7921AUJ-REEL7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Linearity Error (LSB)1 ±0.5 max ±0.5 max ±0.5 max ±0.5 max ±0.5 max ±1.5 max ±1.5 max ±1.5 max ±1.5 max ±1.5 max Package Description 8-lead MSOP 8-lead MSOP 8-lead MSOP 8-lead TSOT 8-lead TSOT 8-lead MSOP 8-lead MSOP 8-lead MSOP 8-lead TSOT 8-lead TSOT Linearity error here refers to integral nonlinearity. Rev. 0 | Page 25 of 28 Package Option RM-8 RM-8 RM-8 UJ-8 UJ-8 RM-8 RM-8 RM-8 UJ-8 UJ-8 Branding C1J C1J C1J C1J C1J C1K C1K C1K C1K C1K Quantity 1 3,000 1,000 250 3,000 1 3,000 1,000 250 3,000 AD7911/AD7921 NOTES Rev. 0 | Page 26 of 28 AD7911/AD7921 NOTES Rev. 0 | Page 27 of 28 AD7911/AD7921 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04350–0–4/04(0) Rev. 0 | Page 28 of 28