AD AD8151

streamª 33 17, 3.2 Gb/s
a
FUNCTIONAL BLOCK DIAGRAM
INP
INN
CS
RE
7
5
A
WE
FIRST
RANK
17 7-BIT
LATCH
SECOND
RANK
17 7-BIT
LATCH
INPUT
DECODERS
D
33
OUTPUT
ADDRESS
DECODER
FEATURES
Low Cost
33 17, Fully Differential, Nonblocking Array
3.2 Gb/s per Port NRZ Data Rate
Wide Power Supply Range: +3.3 V, –3.3 V
Low Power
425 mA (Outputs Enabled)
35 mA (Outputs Disabled)
LV PECL and LV ECL Compatible
CMOS/TTL-Level Control Inputs: 3 V to 5 V
Low Jitter
No Heat Sinks Required
Drives a Backplane Directly
Programmable Output Current
Optimize Termination Impedance
User-Controlled Voltage at the Load
Minimize Power Dissipation
Individual Output Disable for Busing and Reducing
Power
Double Row Latch
Buffered Inputs
Available in 184-Lead LQFP
Digital Crosspoint Switch
AD8151*
33
17
33 17
DIFFERENTIAL
SWITCH
17
MATRIX
OUTP
OUTN
AD8151
UPDATE
RESET
APPLICATIONS
High-Speed Serial Backplane Routing to OC-48 with FEC
Fiber Optic Network Switching
Fiber Channel
LVDS
PRODUCT DESCRIPTION
AD8151 is a member of the Xstream line of products and is
a breakthrough in digital switching, offering a large switch array
(33 × 17) on very little power, typically less than 1.5 W. Additionally, it operates at data rates in excess of 3.2 Gb/s per port,
making it suitable for Sonet OC-48 with 8b/10b Forward Error
Correction (FEC). Further, the pricing of the AD8151 makes
it affordable enough to be used for lower data rates as well.
The AD8151’s flexible supply voltages allow the user to operate
with either PECL or ECL data levels and will operate down to
3.3 V for further power reduction. The control interface is CMOS/
TTL compatible (3 V to 5 V).
Figure 1. Eye Pattern, 3.2 Gb/s, PRBS 23
Its fully differential signal path reduces jitter and crosstalk while
allowing the use of smaller single-ended voltage swings.
The AD8151 is offered in a 184-lead LQFP package that operates
over the extended commercial temperature range of 0°C to 85°C.
*Patent Pending.
Xstream is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
(@ 25C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 (see TPC 22), IOUT = 16 mA, unless
AD8151–SPECIFICATIONS otherwise noted.)
Parameter
DYNAMIC PERFORMANCE
Max Data Rate/Channel (NRZ)
Channel Jitter
RMS Channel Jitter
Propagation Delay
Propagation Delay Match
Output Rise/Fall Time
INPUT CHARACTERISTICS
Input Voltage Swing
Input Bias Current
Input Capacitance
Input VIN High
Input VIN Low
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Output Current
Output Capacitance
Output VOUT High
Output VOUT Low
POWER SUPPLY
Operating Range
PECL, VCC
ECL, VEE
VDD
VSS
Quiescent Current
VDD
VEE
Conditions
Typ
2.5
3.2
52
8
650
± 50
100
Data Rate = 3.2 Gb/s
Input to Output
20% to 80%
Single-Ended
200
Max
± 100
1000
2
2
VCC – 1.2
VCC – 2.4
Differential (See TPC 22)
VCC
VCC – 1.4
800
VCC – 1.8
5
VCC
25
2
VCC – 1.8
VCC
VEE = 0 V
VCC = 0 V
3.0
–5.25
3
5.25
–3.0
5
0
2
425
All Outputs Enabled, IOUT = 16 mA
TMIN to TMAX
All Outputs Disabled
THERMAL CHARACTERISTICS
Operating Temperature Range
θJA
LOGIC INPUT CHARACTERISTICS
Input VIN High
Input VIN Low
Min
450
35
0
Unit
Gb/s
ps p-p
ps
ps
ps
ps
mV p-p
µA
pF
V
V
mV p-p
V
mA
pF
V
V
V
V
V
V
mA
mA
mA
mA
85
°C
°C/W
VDD
0.9
V
V
30
VDD = 3 V dc to 5 V dc
1.9
0
–2–
REV. 0
AD8151
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage
VDD – VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 V
VCC – VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
VDD – VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
VSS – VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
VSS – VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
VDD – VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Internal Power Dissipation2
AD8151 184-Lead Plastic LQFP (ST) . . . . . . . . . . . . 4.2 W
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2.0 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
The maximum power that can be safely dissipated by the AD8151
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of
the plastic, approximately 150°C. Temporarily exceeding this
limit may cause a shift in parametric performance due to a change
in the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result in
device failure.
To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 2.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air (T A = 25°C):
184-lead plastic LQFP (ST): θJA = 30°C/W.
6.0
MAXIMUM POWER DISSIPATION – Watts
TJ = 150C
5.0
4.0
3.0
2.0
1.0
–10
0
10
20
30
40
50
60
AMBIENT TEMPERATURE – C
70
80
90
Figure 2. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD8151AST
0°C to 85°C
184-Lead Plastic LQFP
(20 mm × 20 mm)
Evaluation Board
ST-184
AD8151-EVAL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8151 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
AD8151
139 VEE
140 IN13P
142 VEE
141 IN13N
143 IN14P
145 VEE
144 IN14N
146 IN15P
148 VEE
147 IN15N
150 VEEREF
149 VCC
152 VSS
151 REF
153 D6
154 D5
155 D4
156 D3
157 D2
158 D1
159 D0
160 A4
161 A3
163 A1
162 A2
165 UPDATE
164 A0
167 RE
166 WE
169 RESET
168 CS
172 VEE
171 VCC
170 VDD
173 IN16P
175 VEE
174 IN16N
178 VEE
177 IN17N
176 IN17P
179 IN18P
181 VEE
180 IN18N
1
138
PIN 1
IDENTIFIER
2
3
4
137
136
135
134
5
6
133
7
132
8
131
9
130
10
11
129
128
12
13
127
126
14
15
125
16
123
17
122
121
124
18
19
120
119
20
21
22
118
AD8151
23
117
116
115
184L LQFP
24
TOP VIEW
(Not to Scale)
25
114
26
27
113
28
111
29
110
30
109
31
32
108
112
107
106
33
34
35
105
104
36
103
37
102
38
39
101
40
99
41
98
42
44
97
96
95
45
94
46
93
100
92
91
90
89
88
87
85
86
84
83
81
82
80
79
78
77
76
75
74
73
72
71
70
69
67
68
66
65
64
62
63
61
60
59
58
57
56
55
53
54
52
51
50
49
48
47
43
VEE
IN12N
IN12P
VEE
IN11N
IN11P
VEE
IN10N
IN10P
VEE
IN09N
IN09P
VEE
IN08N
IN08P
VEE
IN07N
IN07P
VEE
IN06N
IN06P
VEE
IN05N
IN05P
VEE
IN04N
IN04P
VEE
IN03N
IN03P
VEE
IN02N
IN02P
VEE
IN01N
IN01P
VEE
IN00N
IN00P
VEE
VCC
VEEA0
OUT00P
OUT00N
VEEA1
VEE
VEE
OUT15N
OUT15P
VEEA15
OUT14N
OUT14P
VEEA14
OUT13N
OUT13P
VEEA13
OUT12N
OUT12P
VEEA12
OUT11N
OUT11P
VEEA11
OUT10N
OUT10P
VEEA10
OUT09N
OUT09P
VEEA9
OUT08N
OUT08P
VEEA8
OUT07N
OUT07P
VEEA7
OUT06N
OUT06P
VEEA6
OUT05N
OUT05P
VEEA5
OUT04N
OUT04P
VEEA4
OUT03N
OUT03P
VEEA3
OUT02N
OUT02P
VEEA2
OUT01N
OUT01P
VEE
VEE
IN20P
IN20N
VEE
IN21P
IN21N
VEE
IN22P
IN22N
VEE
IN23P
IN23N
VEE
IN24P
IN24N
VEE
IN25P
IN25N
VEE
IN26P
IN26N
VEE
IN27P
IN27N
VEE
IN28P
IN28N
VEE
IN29P
IN29N
VEE
IN30P
IN30N
VEE
IN31P
IN31N
VEE
IN32P
IN32N
VEE
VCC
VEE
OUT16N
OUT16P
VEEA16
VEE
182 IN19P
184 VEE
183 IN19N
PIN CONFIGURATION
–4–
REV. 0
AD8151
PIN FUNCTION DESCRIPTIONS
Pin No.
Signal
Type
Description
1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31,
34, 37, 40, 42, 46, 47, 92, 93, 99, 102,
105, 108, 111, 114, 117, 120, 123,
126, 129, 132, 135, 138, 139, 142,
145, 148, 172, 175, 178, 181, 184
2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41, 98, 149, 171
VEE
Power Supply
Most Negative PECL Supply (Common with Other
Points Labeled VEE)
IN20P
IN20N
IN21P
IN21N
IN22P
IN22N
IN23P
IN23N
IN24P
IN24N
IN25P
IN25N
IN26P
IN26N
IN27P
IN27N
IN28P
IN28N
IN29P
IN29N
IN30P
IN30N
IN31P
IN31N
IN32P
IN32N
VCC
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
Power Supply
43
44
45
48
49
50
51
52
53
54
55
56
57
58
59
60
61
OUT16N
OUT16P
VEEA16
OUT15N
OUT15P
VEEA15
OUT14N
OUT14P
VEEA14
OUT13N
OUT13P
VEEA13
OUT12N
OUT12P
VEEA12
OUT11N
OUT11P
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
Most Positive PECL Supply (Common with Other
Points Labeled VCC)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to This Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
REV. 0
–5–
AD8151
Pin No.
Signal
Type
Description
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
94
95
96
97
100
101
103
104
106
107
109
110
112
113
115
116
118
119
121
122
VEEA11
OUT10N
OUT10P
VEEA10
OUT09N
OUT09P
VEEA9
OUT08N
OUT08P
VEEA8
OUT07N
OUT07P
VEEA7
OUT06N
OUT06P
VEEA6
OUT05N
OUT05P
VEEA5
OUT04N
OUT04P
VEEA4
OUT03N
OUT03P
VEEA3
OUT02N
OUT02P
VEEA2
OUT01N
OUT01P
VEEA1
OUT00N
OUT00P
VEEA0
IN00P
IN00N
IN01P
IN01N
IN02P
IN02N
IN03P
IN03N
IN04P
IN04N
IN05P
IN05N
IN06P
IN06N
IN07P
IN07N
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Output Complement
High-Speed Output
Most Negative PECL Supply (Unique to this Output)
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
–6–
REV. 0
AD8151
Pin No.
Signal
Type
Description
124
125
127
128
130
131
133
134
136
137
140
141
143
144
146
147
150
IN08P
IN08N
IN09P
IN09N
IN10P
IN10N
IN11P
IN11N
IN12P
IN12N
IN13P
IN13N
IN14P
IN14N
IN15P
IN15N
VEEREF
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
R-Program
151
REF
R-Program
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
173
174
176
177
179
180
182
183
VSS
D6
D5
D4
D3
D2
D1
D0
A4
A3
A2
A1
A0
UPDATE
WE
RE
CS
RESET
VDD
IN16P
IN16N
IN17P
IN17N
IN18P
IN18N
IN19P
IN19N
Power Supply
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Power Supply
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
Connection Point for Output Logic Pull-Down
Programming Resistor (Must be Connected to VEE)
Connection Point for Output Logic Pull-Down
Programming Resistor
Most Negative Control Logic Supply
Enable/Disable Output
(32) MSB Input Select
(16)
(8)
(4)
(2)
(1) LSB Input Select
(16) MSB Output Select
(8)
(4)
(2)
(1) LSB Output Select
Second Rank Program
First Rank Program
Enable Readback
Enable Chip to Accept Programming
Disable All Outputs (Hi-Z)
Most Positive Control Logic Supply
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
High-Speed Input
High-Speed Input Complement
REV. 0
–7–
AD8151–Typical Performance Characteristics
TPC 4. Eye Pattern 3.2 Gb/s, PRBS 23
TPC 1. Eye Pattern 2.5 Gb/s, PRBS 23
p-p = 43ps
STD DEV = 8ps
150mV/DIV
150mV/DIV
p-p = 53ps
STD DEV = 8ps
20ps/DIV
20ps/DIV
TPC 5. Jitter @ 3.2 Gb/s, PRBS 23
100
100
90
90
80
80
70
70
EYE HEIGHT – %
EYE WIDTH – %
TPC 2. Jitter @ 2.5 Gb/s, PRBS 23
60
% EYE WIDTH =
50
(CLOCK PERIOD – JITTER p-p)
CLOCK PERIOD
100
40
60
% EYE HEIGHT =
50
(VOUT @ DATA RATE)
VOUT @ 0.5Gb/s
100
40
30
30
20
20
10
10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
3.5
1.0
1.5
2.0
2.5
3.0
3.5
DATA RATE – Gb/s
DATA RATE – Gb/s
TPC 3. Eye Width vs. Data Rate, PRBS 23
TPC 6. Eye Height vs. Data Rate, PRBS 23
–8–
REV. 0
AD8151
100
90
90
80
80
70
70
JITTER – ps
100
JITTER – ps
60
50
PEAK-PEAK
JITTER
40
60
40
30
30
20
20
10
0
1.0
2.0
2.5Gb/s JITTER
3.2Gb/s STD DEV
STANDARD DEVIATION
1.5
3.2Gb/s JITTER
50
10
2.5
3.0
2.5Gb/s STD DEV
0
3.5
0
10
20
30
40
50
60
70
80
90
TEMPERATURE – C
DATA RATE – Gb/s
TPC 10. Jitter vs. Temperature, PRBS 23
TPC 7. Jitter vs. Data Rate, PRBS 23
150mV/DIV
150mV/DIV
p-p = 38ps
STD DEV = 7.7ps
p-p = 32ps
STD DEV = 4.7ps
100ps/DIV
75ps/DIV
TPC 8. Crosstalk, 2.5 Gb/s, PRBS 23, Attack Signal is OFF
TPC 11. Crosstalk, 3.2 Gb/s, PRBS 23, Attack Signal is OFF
150mV/DIV
150mV/DIV
p-p = 70ps
STD DEV = 8ps
p-p = 70ps
STD DEV = 9ps
75ps/DIV
100ps/DIV
TPC 9. Crosstalk, 2.5 Gb/s, PRBS 23, Attack Signal is ON
REV. 0
TPC 12. Crosstalk, 3.2 Gb/s, PRBS 23, Attack Signal is ON
–9–
150mV/DIV
150mV/DIV
AD8151
1.1ns/DIV
1.4ns/DIV
TPC 16. Response, 3.2 Gb/s, 32-Bit Pattern
1111 1111 0000 0000 0101 0101 0011 0011
TPC 13. Response, 2.5 Gb/s, 32-Bit Pattern
1111 1111 0000 0000 0101 0101 0011 0011
100
100
90
90
80
80
70
70
P-P JITTER – ps
P-P JITTER – ps
3.2Gb/s
60
2.5Gb/s JITTER
50
40
60
50
2.5Gb/s
40
30
30
3.2Gb/s JITTER
20
20
10
10
0
0.2
0.3
0.4
0.5
0.6
0.7
INPUT AMPLITUDE – V
0.8
0.9
0
–5.0
1
TPC 14. Jitter vs. Single-Ended Input Amplitude, PRBS 23
100
90
90
80
80
70
2.5Gb/s
P-P JITTER – ps
P-P JITTER – ps
70
60
3.2Gb/s
50
40
–3.6
–3.4
–3.2
–3.0
20
10
0
–1.4
0.6
3.2Gb/s
2.5Gb/s
10
TPC 15. Jitter vs. VIH, PRBS 23
–4.0 –3.8
VEE – V
40
20
0.4
–4.2
50
30
0.2
–4.4
60
30
0
–4.6
TPC 17. Jitter vs. Supply, PRBS 23
100
0
–1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2
VIH – V
–4.8
–1.2
–1.0
–0.8
–0.6
–0.4
VOH – V
–0.2
0
0.2
TPC 18. Jitter vs. VOH, PRBS 23, Output Amplitude = 0.4 V
Single-Ended
–10–
REV. 0
AD8151
100
200
90
150
PROPAGATION DELAY – ps
80
FREQUENCY
70
60
50
40
30
20
100
50
0
–50
–100
–150
10
0
550
570
590
610 630 650 670 690
PROPAGATION DELAY – ps
710
–200
–100
730
–80
–60
–40
–20
0
20
40
60
80
100
NORMALIZED TEMPERATURE – C
TPC 21. Propagation Delay, Normalized at 25 °C vs.
Temperature
TPC 19. Variation in Channel-to-Channel Delay,
All 561 Points
100
VCC
90
PRBS
GENERATOR
80
P-P JITTER – ps
70
DATA OUT
49.9
AD8151
P
–6dB
105
DATA OUT
50
IN
P
OUT
N
–6dB
N
50
3.2Gb/s
40
49.9
1.65k
VEE
VEE
20
VTT
VCC = 0V, VEE = –3.3V, VTT = –1.6V, VDD = 5V, VSS = 0V
RSET = 1.54k, IOUT = 16mA, VOH = –0.8V, VOL = –1.2V
10
0
HIGH-SPEED
SAMPLING
OSCILLOSCOPE
50
2.5Gb/s
60
30
VIN = 0.8V p-p EXCEPT AS NOTED
5
10
15
20
OUTPUT CURRENT – mA
25
TPC 22. Test Circuit
TPC 20. Jitter vs. IOUT, PRBS 23
REV. 0
1.65k
VTT
VCC
–11–
AD8151
Control Interface Truth Tables
The following are truth tables for the control interface.
Table I. Basic Control Functions
RESET
CS
Control Pins
WE
RE UPDATE
0
1
X
1
X
X
X
X
X
X
1
0
0
X
X
1
0
X
0
X
1
0
X
X
0
1
0
0
1
0
Function
Global Reset. Reset all second rank enable bits to zero (disable all outputs).
Control Disable. Ignore all logic (but the signal matrix still functions as
programmed). D[6:0] are high-impedance.
Single Output Preprogram. Write input configuration data from data bus D[6:0].
into first rank of latches for the output selected by the output address bus A[4:0].
Single Output Readback. Readback input configuration data from second rank of latches
onto data bus D[6:0] for the single output selected by the output address bus A[4:0].
Global Update. Copy input configuration data from all 17 first rank latches into second
rank of latches, updating signal matrix connections for all outputs.
Transparent Write and Update. It is possible to write data directly onto rank two. This
simplifies logic when synchronous signal matrix updating is not necessary.
Table II. Address/Data Examples
Output Address Pins
MSB–LSB
Enable
Bit
Input Address Pins
MSB–LSB
A4
A3
A2
A1
A0
D6/E
D5
D4
D3
D2
D1
D0
Function
0
0
0
0
0
X
0
0
0
0
0
0
Lower Address/Data Range. Connect Output #00
(A[4:0] = 00000) to Input #00 (D[5:0] = 000000).
1
0
0
0
0
X
1
0
0
0
0
0
Upper Address/Data Range. Connect Output #16
(A[4:0] = 10000) to Input #32 (D[5:0] = 100000).
<Binary Output Number*>
1
<Binary Output Number*>
0
1
0
0
0
1
X
1
0
0
1
0
X
<Binary Input Number>
X
X
X
X
X
Enable Output. Connect Selected Output (A[4:0] = 0
to 16) to Designated Input (D[5:0] = 0 to 32) and
Enable Output (D6 = 1).
X
<Binary Input Number>
1
0
0
0
0
Disable Output. Disable Specified Output (D6 = 0).
Broadcast Connection. Connect all 17 outputs to
same designated input and set all 17 enable bits to
the value of D6. Readback is not possible with the
broadcast address.
1
Reserved. Any address or data code greater or equal
to these are reserved for future expansion or factory
testing.
*The binary output number may also be the broadcast connection designator, 10001.
–12–
REV. 0
AD8151
Control Interface Timing Diagrams
CS INPUT
WE INPUT
A[4:0] INPUTS
D[6:0] INPUTS
tCSW
tCHW
tASW
tAHW
tWP
tDSW
tDHW
Figure 3. First Rank Write Cycle
Table III. First Rank Write Cycle
Symbol
Parameter
tCSW
tASW
tDSW
Setup Time
Chip Select to Write Enable
Address to Write Enable
Data to Write Enable
tCHW
tAHW
tDHW
Hold Time
Chip Select from Write Enable
Address from Write Enable
Data from Write Enable
tWP
Width of Write Enable Pulse
Conditions
Min
Typ
Max
Unit
TA = 25°C
VDD = 5 V
VCC = 3.3 V
0
0
15
ns
ns
ns
0
0
0
ns
ns
ns
15
ns
CS INPUT
UPDATE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 1
TOGGLE
OUT[0:16][N:P]
OUTPUTS
PREVIOUS RANK 2 DATA
DISABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 2
tCSU
DATA FROM RANK 1
tCHU
tUW
tUOE
tUOD
tUOT
Figure 4. Second Rank Update Cycle
Table IV. Second Rank Update Cycle
Symbol
Parameter
tCSU
tCHU
tUOE
tUOT
tUOD
Setup Time
Hold Time
Output Enable Times
Output Toggle Times
Output Disable Times
tUW
Width of Update Pulse
REV. 0
Chip Select to Update
Chip Select from Update
Update to Output Enable
Update to Output Reprogram
Update to Output Disabled
Conditions
Min
TA = 25°C
VDD = 5 V
VCC = 3.3 V
0
0
25
25
25
15
–13–
Typ
Max
Unit
40
40
30
ns
ns
ns
ns
ns
ns
AD8151
CS INPUT
UPDATE INPUT
WE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
INPUT {DATA 1}
INPUT {DATA 2}
INPUT {DATA 1}
INPUT {DATA 0}
tCSU
tCHU
tUW
tUOT
tWOT
tUOE
tWHU
tWOD
Figure 5. First Rank Write Cycle and Second Rank Update Cycle
Table V. First Rank Write Cycle and Second Rank Update Cycle
Symbol
Parameter
Conditions
Min
0
0
tCSU
tCHU
Setup Time
Hold Time
Chip Select to Update
Chip Select from Update
TA = 25°C
VDD = 5 V
tUOE
tWOE*
Output Enable Times
Update to Output Enable
Write Enable to Output Enable
VCC = 3.3 V
tUOT
tWOT
Output Toggle Times
tUOD*
tWOD
Typ
Max
Unit
ns
ns
25
25
40
40
ns
ns
Update to Output Reprogram
Write Enable to Output Reprogram
25
25
30
30
ns
ns
Output Disable Times
Update to Output Disabled
Write Enable to Output Disabled
25
25
30
30
ns
ns
tWHU
Setup Time
Write Enable to Update
tUW
Width of Update Pulse
10
ns
15
ns
*Not Shown.
CS INPUT
RE INPUT
A[4:0]
INPUTS
ADDR 1
ADDR 2
DATA
{ADDR1}
D[6:0]
OUTPUTS
DATA {ADDR2}
tCSR
tRDE
tAA
tCHR
tRHA
tRDD
Figure 6. Second Rank Readback Cycle
Table VI. Second Rank Readback Cycle
Symbol
Parameter
Conditions
Min
0
0
5
tCSR
tCHR
tRHA
Setup Time
Hold Time
Chip Select to Read Enable
Chip Select from Read Enable
Address from Read Enable
TA = 25°C
VDD = 5 V
VCC = 3.3 V
tRDE
tAA
tRDD
Enable Time
Access Time
Release Time
Data from Read Enable
Data from Address
Data from Read Enable
10 kΩ
20 pF on D[6:0]
Bus
–14–
Typ
Max
Unit
ns
ns
ns
15
15
15
30
ns
ns
ns
REV. 0
AD8151
RESET INPUT
DISABLING
OUT[0:16][N:P]
OUTPUTS
tTOD
tTW
Figure 7. Asynchronous Reset
Table VII. Asynchronous Reset
Symbol
tTOD
tTW
Parameter
Disable Time
Width of Reset Pulse
Output Disable from Reset
Conditions
Min
TA = 25°C
VDD = 5 V
VCC = 3.3 V
15
Typ
Max
Unit
25
30
ns
ns
Control Interface Programming Example
The following conservative pattern connects all outputs to input number 7, except output 16 which is connected to input number 32.
The vector clock period, T0 is 15 ns. It is possible to accelerate the execution of this pattern by deleting vectors 1, 4, 7, and 9.
Table VIII. Basic Test Pattern
Vector No.
RESET
CS
WE
RE
UPDATE
A[4:0]
D[6:0]
Comments
0
1
2
3
4
5
6
7
8
9
10
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
xxxxx
xxxxx
10001
10001
10001
10000
10000
10000
xxxxx
xxxxx
xxxxx
xxxxxxx
xxxxxxx
1000111
1000111
1000111
1100000
1100000
1100000
xxxxxxx
xxxxxxx
xxxxxxx
Disable All Outputs
REV. 0
–15–
All Outputs to Input #07
Write to First Rank
Output #16 to Input #32
Write to First Rank
Transfer to Second Rank
Disable Interface
AD8151
7
UPDATE RESET
7
7
7
7
7
7
D[0:6]
0
0
1
1
2
2
7
CONTROL PIN DESCRIPTION
A[4:0] Inputs
TO 1733
SWITCH
MATRIX
33
7
7
7
33
7
7
33
7
33
Output address pins. The binary encoded address applied to
these five input pins determines which one of the seventeen
outputs is being programmed (or being read back). The most
significant bit is A4.
D[6:0] Inputs/Outputs
7
7
16
16
RANK 1
RANK 2
7
17 ROWS OF 7-BIT
LATCHES
Input configuration data pins. In write mode, the binary encoded
data applied to pins D[6:0] determine which one of 33 inputs is
to be connected to the output specified with the A[4:0] pins.
The most significant bit is D5, and the least significant bit is
D0. Bit D6 is the enable bit, setting the specified output signal pair to an enabled state if D6 is logic HIGH, or disabled
to a high-impedance state if D6 is logic LOW.
1 OF 33
DECODERS
WE
In readback mode, pins D[6:0] are low-impedance outputs indicating the data word stored in the second rank for the output
specified with the A[4:0] pins. The readback drivers were designed
to drive high impedances only, so external drivers connected
to the D[6:0] should be disabled during readback mode.
1 OF 17 DECODERS
A[0:4]
RE
WE Input
Figure 8. Control Interface (Simplified Schematic)
AD8151 CONTROL INTERFACE
The AD8151 control interface receives and stores the desired
connection matrix for the 33 input and 17 output signal pairs.
The interface consists of 17 rows of double-rank 7-bit latches,
one row for each output. The 7-bit data word stored in each
of these latches indicates to which (if any) of the 33 inputs the
output will be connected.
One output at a time can be preprogrammed by addressing the
output and writing the desired connection data into the first
rank of latches. This process can be repeated until each of the
desired output changes has been preprogrammed. All output
connections can then be programmed at once by passing the
data from the first rank of latches into the second rank. The
output connections always reflect the data programmed into
the second rank of latches, and do not change until the first rank
of data is passed into the second rank.
If necessary for system verification, the data in the second rank
of latches can be read back from the control interface.
At any time, a reset pulse can be applied to the control interface
to globally reset the appropriate second rank data bits, disabling
all 17 signal output pairs. This feature can be used to avoid
output bus contention on system start-up. The contents of the
first rank remain unchanged.
The control interface pins are connected via logic-level translators. These translators allow programming and readback of the
control interface using logic levels different from those in the
signal matrix.
In order to facilitate multiple chip address decoding, there is a
chip-select pin. All logic signals except the reset pulse are ignored
unless the chip select pin is active. The chip select pin disables
only the control logic interface, and does not change the operation of the signal matrix. The chip select pin does not power
down any of the latches, so any data programmed in the latches
is preserved.
First Rank Write Enable. Forcing this pin to logic LOW allows
the data on pins D[6:0] to be stored in the first rank latch for
the output specified by pins A[4:0]. The WE pin must be returned
to a logic HIGH state after a write cycle to avoid overwriting
the first rank data.
UPDATE Input
Second Rank Write Enable. Forcing this pin to logic LOW allows
the data stored in all 17 first rank latches to be transferred to the
second rank latches. The signal connection matrix will be reprogrammed when the second rank data is changed. This is a global
pin, transferring all 17 rows of data at once. It is not necessary
to program the address pins. It should be noted that after initial
power-up of the device, the first rank data is undefined. It may
be desirable to preprogram all seventeen outputs before performing
the first update cycle.
RE Input
Second Rank Read-Enable. Forcing this pin to logic LOW enables
the output drivers on the bidirectional D[6:0] pins, entering the
readback mode of operation. By selecting an output address with
the A[4:0] pins and forcing RE to logic LOW, the 7-bit data
stored in the second rank latch for that output address will be
written to D[6:0] pins. Data should not be written to the D[6:0]
pins externally while in readback mode. The RE and WE pins
are not exclusive, and may be used at the same time, but data
should not be written to the D[6:0] pins from external sources
while in readback mode.
CS Input
Chip-Select. This pin must be forced to logic LOW in order
to program or receive data from the logic interface, with the
exception of the RESET pin, described below. This pin has
no effect on the signal pairs and does not alter any of the stored
control data.
RESET Input
Global Output Disable Pin. Forcing the RESET pin to logic
LOW will reset the enable bit, D6, in all 17 second rank
latches, regardless of the state of any other pins. This has the
effect of immediately disabling the 17 output signal pairs in the
All control pins are level-sensitive, not edge-triggered.
–16–
REV. 0
AD8151
matrix. It is useful to momentarily hold RESET at a logic LOW
state when powering up the AD8151 in a system that has multiple output signal pairs connected together. Failure to do this
may result in several signal outputs contending after power-up.
The reset pin is not gated by the state of the chip-select pin, CS.
It should be noted that the RESET pin does not program the
first rank, which will contain undefined data after power-up.
CONTROL INTERFACE TRANSLATORS
The AD8151 control interface has two supply pins, VDD and
VSS. The potential between the positive logic supply VDD and
the negative logic supply VSS must be at least 3 V and no more
than 5 V. Regardless of supply, the logic threshold is approximately 1.6 V above VSS, allowing the interface to be used with
most CMOS and TTL logic drivers.
In order to maintain signal fidelity at the high data rates supported
by the AD8151, the input transmission lines should be terminated
as close to the input pins as possible. The preferred input termination structure will depend primarily on the application and
the output circuit of the data source. Standard ECL components have open emitter outputs that require pull-down resistors.
Three input termination networks suitable for this type of source
are shown in Figure 10. The characteristic impedance of the transmission line is shown as ZO. The resistors, R1 and R2, in the
Thevenin termination are chosen to synthesize a VTT source
with an output resistance of ZO and an open-circuit output voltage equal to VCC – 2 V. The load resistors (RL) in the differential
termination scheme are needed to bias the emitter followers of
the ECL source.
VCC
The signal matrix supplies, VCC and VEE, can be set independent of the voltage on VDD and VSS, with the constraints that
(VDD–VEE) ≤ 10 V. These constraints will allow operation of
the control interface on 3 V or 5 V while the signal matrix is
operated on +3.3 V or +5 V PECL, or –3.3 V or –5 V ECL.
The AD8151 has 33 pairs of differential voltage-mode inputs.
The common-mode input range extends from the positive supply voltage (VCC) down to include standard ECL or PECL input
levels (VCC – 2 V). The minimum differential input voltage is
200 mV. Unused inputs may be connected directly to any level
within the allowed common-mode input range. A simplified
schematic of the input circuit is shown in Figure 9.
VCC
INxxN
INxxP
INxxN
ZO
ZO
INxxP
ZO
INxxP
ZO
ECL SOURCE
R2
R2
VEE
VTT = VCC – 2V
(a)
(b)
VCC
ZO
INxxN
ZO
2ZO
INxxP
ECL SOURCE
RL
RL
VEE
(c)
Figure 10. AD8151 Input Termination from ECL/PECL
Sources: a) Parallel Termination Using VTT Supply, b)
Thevenin Equivalent Termination, c) Differential Termination
If the AD8151 is driven from a current mode output stage such
as another AD8151, the input termination should be chosen
to accommodate that type of source, as explained in the following section.
High-Speed Data Outputs (OUTyyP, OUTyyN)
The AD8151 has 17 pairs of differential current-mode outputs.
The output circuit, shown in Figure 11, is an open-collector
NPN current switch with resistor-programmable tail current and
output compliance extending from the positive supply voltage
(VCC) down to standard ECL or PECL output levels (VCC – 2 V).
The outputs may be disabled individually to permit outputs
from multiple AD8151s to be connected directly. Since the
output currents of multiple enabled output stages connected
in this way sum, care should be taken to ensure that the output compliance limit is not exceeded at any time; this can be
achieved by disabling the active output driver before enabling
any inactive driver.
VEE
Figure 9. Simplified Input Circuit
REV. 0
R1
INxxN
CIRCUIT DESCRIPTION
High-Speed Data Inputs (INxxP, INxxN)
VCC – 2V
ZO R1
ZO
ECL SOURCE
The AD8151 is a high-speed 33 × 17 differential crosspoint switch
designed for data rates up to 3.2 Gb/s per channel. The AD8151
supports PECL-compatible input and output levels when operated
from a 5 V supply (VCC = 5 V, VEE = GND) or ECL-compatible
levels when operated from a –5 V supply (VCC = GND, VEE =
–5 V). To save power, the AD8151 can run from a +3.3 V supply
to interface with low-voltage PECL circuits or a –3.3 V supply
to interface with low-voltage ECL circuits. The AD8151 utilizes
differential current mode outputs with individual disable control,
which facilitates busing together the outputs of multiple AD8151s
to assemble larger switch arrays. This feature also reduces system crosstalk and can greatly reduce power dissipation in a large
switch array. A single external resistor programs the current for
all enabled output stages, allowing for user control over output
levels with different output termination schemes and transmission line characteristic impedances.
VCC
–17–
AD8151
VCC
VCC
RCOM
OUTyyP
OUTyyN
VCC – 2V
AD8151
VCOM
RL
RL
OUTyyN
OUTyyP
AD8151
ZO
ZO
OUTyyN
OUTyyP
IOUT
DISABLE
ZO
ZO
RL
VEE
RL
VEE
Figure 11. Simplified Output Circuit
RECEIVER
To ensure proper operation, all outputs (including unused output)
must be pulled high using external pull-up networks to a level
within the output compliance range. If outputs from multiple
AD8151s are wired together, a single pull-up network may be
used for each output bus. The pull-up network should be chosen
to keep the output voltage levels within the output compliance
range at all times. Recommended pull-up networks to produce
PECL/ECL 100 kΩ and 10 kΩ compatible outputs are shown
in Figure 12. Alternatively, a separate supply can be used to
provide VCOM; making RCOM and DCOM unnecessary.
VCC
VCC
RCOM
AD8151
RL
DCOM
VCOM
RL
AD8151
OUTyyN
OUTyyN
OUTyyP
OUTyyP
RL
VCOM
RL
Figure 13. Double Termination of AD8151 Outputs
In this case, the output levels are:
VOH = VCOM – (1/4) IOUTRL
VOL = VCOM – (3/4) IOUTRL
VSWING = VOH – VOL = (1/2) IOUTRL
Output Current Set Pin (REF)
A simplified schematic of the reference circuit is shown in Figure 14. A single external resistor connected between the REF
pin and VEE determines the output current for all output stages.
This feature allows a choice of pull-up networks and transmission
line characteristic impedances while still achieving a nominal
output swing of 800 mV. At low data rates, substantial power
savings can be achieved by using lower output swings and higher
load resistances.
Figure 12. Output Pull-Up Networks: a) ECL 100 kΩ,
b) ECL 10 kΩ
AD8151
IOUT/20
VCC
The output levels are simply:
REF
1.2V
VOH = VCOM
RSET
VOL = VCOM – IOUTRL
VEE
VSWING = VOH – VOL = IOUTRL
Figure 14. Simplified Reference Circuit
VCOM = VCC – IOUTRCOM (100 kΩ Mode)
The nominal output current is given by the following expression:
VCOM = VCC – V (DCOM) (10 kΩ Mode)
The common-mode adjustment element (RCOM or DCOM) may
be omitted if the input range of the receiver includes the positive
supply voltage. The bypass capacitors reduce common-mode
perturbations by providing an ac short from the common nodes
(VCOM) to ground.
When busing together the outputs of multiple AD8151s or when
running at high data rates, double termination of its outputs is
recommended to mitigate the impact of reflections due to open
transmission line stubs and the lumped capacitance of the
AD8151 output pins. A possible connection is shown in Figure
13; the bypass capacitors provide an ac short from the common
nodes of the termination resistors to ground. To maintain signal
fidelity at high data rates, the stubs connecting the output pins
to the output transmission lines or load resistors should be as
short as possible.
 1 .2 V 
IOUT = 20 

 RSET 
The minimum set resistor is RSET,MIN = 960 Ω resulting in
IOUT,MAX = 25 mA. The maximum set resistor is RSET,MAX =
4.8 kΩ resulting in IOUT,MIN = 5 mA. Nominal 800 mV differential output swing can be achieved in a 50 Ω load using RSET =
1.5 kΩ (IOUT = 16 mA), or in a doubly-terminated 75 Ω load
using RSET = 1.13 kΩ (IOUT = 21.3 mA).
To minimize stray capacitance and avoid the pickup of unwanted
signals, the external set resistor should be located close to the
REF pin. Bypassing the set resistor is not recommended.
–18–
REV. 0
AD8151
the part is to be ac-coupled, it is not necessary to have the input/
output common mode at the same level as the other system
circuits, but it will probably be more convenient to use the same
supply rails for all devices.
Power Supplies
There are several options for the power supply voltages for the
AD8151, as there are two separate sections of the chip that require
power supplies. These are the control logic and the high-speed
data paths. Depending on the system architecture, the voltage
levels of these supplies can vary.
Logic Supplies
The control (programming) logic is CMOS and is designed to
interface with any of the various standard single-ended logic
families (CMOS or TTL). Its supply voltage pins are VDD (Pin
170, logic positive) and VSS (Pin 152, logic ground). In all cases
the logic ground should be connected to the system digital ground.
VDD should be supplied at between 3.3 V to 5 V to match the
supply voltage of the logic family that is used to drive the logic
inputs. VDD should be bypassed to ground with a 0.1 µF ceramic
capacitor. The absolute maximum voltage from VDD to VSS
is 5.5 V.
For PECL operation, VEE will be at ground potential and VCC
will be a positive voltage from 3.3 V to 5 V. Thus, the common
mode of the inputs and outputs will be at a positive voltage.
These can then be dc-coupled to other PECL operated devices.
If the data paths are ac-coupled, then the common-mode levels
do not matter, see Figure 16.
+3.3V TO +5V
VDD
The data path supplies have more options for their voltage levels. The choices here will affect several other areas, like power
dissipation, bypassing, and common mode levels of the inputs
and outputs. The more positive voltage supply for the data paths
is VCC (Pins 41, 98, 149 and 171). The more negative supply is
VEE, which appears on many pins that will not be listed here.
The maximum allowable voltage across these supplies is 5.5 V.
GND
0.1F
VDD
VCC
AD8151
CONTROL
LOGIC
+3.3V TO +5V
DATA
PATHS
VSS
VEE
GND
GND
Figure 16. Power Supplies and Bypassing for PECL
Operation
POWER DISSIPATION
For analysis, the power dissipation of the AD8151 can be divided
into three separate parts. These are the control logic, the data
path circuits and the (ECL or PECL) outputs, which are part of
the data path circuits, but can be dealt with separately. The first
of these, the control logic, is CMOS technology and does not
dissipate a significant amount of power. This power will, of
course, be greater when the logic supply is 5 V rather than 3 V,
but overall it is not a significant amount of power and can be
ignored for thermal analysis.
VCC
AD8151
VDD
CONTROL
LOGIC
VCC
ROUT
AD8151
DATA
PATHS
IOUT
DATA
PATHS
CONTROL
LOGIC
VSS
VEE
I, DATA PATH
LOGIC
0.1F
(ONE FOR EVERY TWO VEE PINS)
GND
VSS
–3.3V TO –5V
Figure 15. Power Supplies and Bypassing for ECL
Operation
If the data paths are to be dc-coupled to other ECL logic devices
that run with ground as the most positive supply and a negative
voltage for VEE, then this is the proper way to run. However, if
REV. 0
0.1F
(ONE FOR EACH VCC PIN,
4 REQUIRED)
0.1F
Data Path Supplies
The first choice in the data path power supplies is to decide
whether to run the device as ECL (Emitter-Coupled Logic) or
PECL (Positive ECL). For ECL operation, VCC will be at ground
potential, while VEE will be at a negative supply between –3.3 V
to –5 V. This will make the common-mode voltage of the inputs
and outputs at a negative voltage, see Figure 15.
+3.3V TO +5V
GND
VOUT LOW – VEE
VEE
GND
Figure 17. Major Power Consumption Paths
The data path circuits operate between the supplies VCC and
VEE. As described in the power supply section, this voltage can
range from 3.3 V to 5 V. The current consumed by this section
will be constant, so operating at a lower voltage can save about
35 percent in power dissipation.
–19–
AD8151
The power dissipated in the data path outputs is affected by several
factors. The first is whether the outputs are enabled or disabled.
The worst case occurs when all of the outputs are enabled.
the pin leads can provide an even lower thermal resistive path. If
possible to use, 2 oz. copper foil will provide better heat removal
than 1 oz.
The current consumed by the data path logic can be approximated by:
The AD8151 package has a specified thermal impedance θJA of
30°C/W. This is the worst case, still-air value that can be expected
when the circuit board does not significantly enhance the heat
removal from the package. By using the concept described above
or by using forced-air circulation, the thermal impedance can be
lowered.
ICC = 35 mA + [4.5 mA + (IOUT/20 mA × 3 mA)]
× (# of outputs enabled)
This says that there will always be a minimum of 35 mA flowing. ICC will increase by a factor that is proportional to both the
number of enabled outputs and the programmed output current.
The power dissipated in this circuit section will simply be the
voltage of this section (VCC – VEE) times the current. For a worst
case, assume that VCC – VEE is 5.0 V, all outputs are enabled
and the programmed output current is 25 mA. The power dissipated by the data path logic will be:
P = 5.0 V {35 mA + [4.5 mA + (25 mA/20 mA × 3 mA)]
× 17} = 876 mW
APPLICATIONS
AD8151 INPUT AND OUTPUT BUSING
The power dissipated by the output current depends on several
factors. These are the programmed output current, the voltage
drop from a logic low output to VEE and the number of enabled
outputs. A simplifying assumption is that one of each (enabled)
differential output pair will be low and draw the full output
current (and dissipate most of the power for that output), while
the complementary output of the pair will be high and draw
insignificant current. Thus, its power dissipation of the high
output can be ignored and the output power dissipation for each
output can be assumed to occur in a single static low output
that sinks the full output-programmed current.
The voltage across which this current flows can also vary, depending on the output circuit design and the supplies that are used
for the data path circuitry. In general, however, there will be a
voltage difference between a logic low signal and VEE. This is
the drop across which the output current flows. For a worst
case, this voltage can be as high as 3.5 V. Thus, for all outputs
enabled and the programmed output current set to 25 mA, the
power dissipated by the outputs:
Although the AD8151 is a digital part, in any application that
runs at high speed, analog design details will have to be given very
careful consideration. At high data rates, the design of the signal
channels will have a strong influence on the data integrity and
its associated jitter and ultimately bit error rate (BER).
While it might be considered very helpful to have a suggested
circuit board layout for any particular system configuration,
this is not something that can be practically realized. Systems
come in all shapes, sizes, speeds, performance criteria and cost
constraints. Therefore, some general design guidelines will be
presented that can be used for all systems and judiciously modified where appropriate.
High-speed signals travel best, i.e. maintain their integrity, when
they are carried by a uniform transmission line that is properly
terminated at either end. Any abrupt mismatches in impedance
or improper termination will create reflections that will add to
or subtract from parts of the desired signal. Small amounts of
this effect are unavoidable, but too much will distort the signal
to the point that the channel BER will increase. It is difficult to
fully quantify these effects, because they are influenced by many
factors in the overall system design.
P = 3.5 V (25 mA) × 17 = 1.49 W
HEAT SINKING
Depending on several factors in its operation, the AD8151 can
dissipate upwards of 2 W or more. The part is designed to operate without the need for an explicit external heatsink. However,
the package design offers enhanced heat removal via some of the
package pins to the PC board traces.
The VEE pins on the input sides of the package (Pins 1 to 46 and
Pins 93 to 138) have “finger” extensions inside the package
that connect to the “paddle” upon which the IC chip is mounted.
These pins provide a lower thermal resistance from the IC to
the VEE pins than other pins that just have a bond wire. As a
result these pins can be used to enhance the heat removal process from the IC to the circuit board and ultimately to the ambient.
The VEE pins described above should be connected to a large area
of circuit board trace material in order to take most advantage
their lower thermal resistance. If there is a large area available
on an inner layer that is at VEE potential, then vias can be provided from the package pin traces to this layer. There should be
no thermal-relief pattern when connecting the vias to the inner
layers for these VEE pins. Additional vias in parallel and close to
For an extreme worst case analysis, the junction rise above the
ambient can be calculated assuming 2 W of power dissipation
and θJA of 30°C/W to yield a 60°C rise above the ambient. There
are many techniques described above that can mitigate this situation. Most actual circuits will not result in this high a rise of the
junction temperature above the ambient.
A constant-impedance transmission line is characterized by
having a uniform cross-section profile over its entire length. In
particular, there should be no “stubs,” which are branches that
intersect the main run of the transmission line. These can have
an electrical “appearance” that is approximated by a lumped
element, such as a capacitor, or if long enough, as another transmission line. To the extent that stubs are unavoidable in a design,
their effect can be minimized by making them as short as possible and as high an impedance as possible.
Figure 13 shows a differential transmission line that connects
two differential outputs from AD8151s to a generic receiver. A
more generalized system can have more outputs bused, and
more receivers on the same bus, but all the same concepts apply.
The inputs of the AD8151 can also be considered as a receiver.
The transmission lines that bus all of the devices together are
shown with terminations at each end.
The individual outputs of the AD8151 are stubs that intersect
the main transmission line. Ideally, their current-source outputs
would be infinite impedance, and they would have no effect on
signals that propagate along the transmission line. In reality, each
–20–
REV. 0
AD8151
external pin of the AD8151 projects into the package, and has a
bond wire connected to the chip inside. On-chip wiring then
connects to the collectors of the output transistors and to ESD
protection diodes.
Unlike some other high-speed digital components, the AD8151
does not have on-chip terminations. While this location would
be closer to the actual end of the transmission line for some
architectures, this concept can limit system design options. In
particular, it is not possible to bus more than two inputs or
outputs on the same transmission line and it is also not possible
to change the value of these terminations to use for different
impedance transmission lines. The AD8151, with the added
ability to disable its outputs, is much more versatile in these
types of architectures.
If the external traces are kept to a bare minimum, then the
output will present a mostly lumped capacitive load of about
2 pF. A single stub of 2 pF will not seriously adversely affect
signal integrity for most transmission lines, but the more of
these stubs, the more adverse their influence will be.
One way to mitigate this effect is to locally reduce the capacitance
of the main transmission line near the point of stub intersection.
Some practical means for doing this are to narrow the PC board
traces in the region of the stub and/or to remove some of the
ground plane(s) near this intersection. The effect of these techniques will locally lower the capacitance of the main transmission
line at these points, while the added capacitance of the AD8151
outputs will “compensate” for this reduction in capacitance.
The overall intent is to create as uniform a transmission line as
possible.
Operating in PECL mode requires VCC to be at a positive voltage, while VEE is at ground. Since this would make the shells of
the I/O connectors at a positive voltage, it can cause problems
when directly connecting to test equipment. Some equipment,
such as battery-operated oscilloscopes, can be “floated” from
ground, but care should be taken with line-powered equipment
to avoid creating a dangerous situation. Refer to the manual of
the test equipment that is being used.
The voltage difference from VCC to VEE can range from 3 V to
5 V. Power savings can be realized by operating at a lower voltage without any compromise in performance.
A separate connection is provided for VTT, the termination
potential of the outputs. This can be at a voltage as high as VCC,
but power savings can be realized if VTT is at a voltage that is
somewhat lower. Please consult elsewhere in the data sheet for
the specification for the limits of the VTT supply.
As a practical matter, current on the evaluation board will flow
from the VTT supply, through the termination resistors, into the
multiple outputs of the AD8151, and on to the VEE supply. When
running in ECL mode, VTT will want to be at a negative supply.
Most power supplies will not allow their ground connection to
VCC and then the negative supply to VTT. This will require them
to source current from their negative supply, which wants to
flow to the more-negative VEE. This current will not then return
to the ground terminal of the VTT supply. Thus, VTT should be
referenced to VEE when running in ECL mode or a true bipolar
supply should be used.
In selecting the location of the termination resistors it is important to keep in mind that, as their name implies, they should be
placed at either end of the line. There should be no or minimal
projection of the transmission line beyond the point where the
termination resistors connect to it.
The digital supply is provided to the AD8151 by the VDD and
VSS pins. VSS should always be at ground potential to make it
compatible with standard CMOS or TTL logic. VDD can range
from 3 V to 5 V, and should be matched to the supply voltage of
the logic used to control the AD8151. However, since PCs use
5 V logic on their parallel port, VDD should be at 5 V when using a
PC to program the AD8151.
EVALUATION BOARD
Bypassing
An evaluation board has been designed and is available to rapidly
test the main features of the AD8151. This board lets the user
analyze the analog performance of the AD8151 channels and
easily control the configuration of the board by a standard PC.
The board has limited numbers of differential input/output
pairs. Each differential pair of microstrip is connected to either
top-mount or side-launch SMA connectors. The top-mount
SMA connectors are drilled and stubbed for superior performance. The FR4 type board contains a total of nine outputs (all
even numbered outputs) and 20 inputs (numbers 0, 2, 4, 6, 8,
10, 12, 13, 14, 15, 16, 17, 18, 20, 22, 24, 26, 28, 30, 32). It is
important to note that the shells of the SMA connectors are
attached to VCC. This makes only ECL or negative level swings
possible during testing.
Power Supplies
The AD8151 is designed to work with standard ECL logic levels.
This means that VCC is at ground and VEE is at a negative supply.
The shells of the I/O SMA connectors are at VCC potential. Thus,
when operating in the standard ECL configuration, test equipment
can be directly connected to the board, as the test equipment
will have its connector “shells” at ground potential also.
REV. 0
Most of the board’s bypass capacitors are opposite the DUT on
the solder side, connected between VCC and VEE. This is where
they will be most effective. These capacitors are 0.01 µF ceramic
chip capacitors for low inductance. There are additional higher
value capacitors elsewhere on the board for bypassing at lower
frequencies. The location of these is not as critical.
Input and Output Considerations
Each input contains a 100 Ω differential termination. Although
the differential termination eases board layout due to its compact
nature, it can cause problems with the driving generator. A typical
pulse or pattern generator wants to see 50 Ω to ground (or to
–2 V in some cases). High speed probing of the input showed if
this type of termination is not present then input amplitudes could
be slightly off. Even more affected can be the dc input levels.
Depending on the generator used, these levels can be off as much
as 800 mV in either direction. A correction for this problem is to
attach a 6 dB attenuator to each P and N input. Because the
AD8151 has a large common-mode voltage range on its input
stage, it will not be significantly affected by dc level errors.
–21–
AD8151
On this evaluation board all unused inputs are tied to VCC (GND).
All outputs, whether brought out to connectors or not, are tied
to VTT through a 49.9 Ω resistor. The AD8151 device is on the
component side of the board, while input terminations and output
back terminations are on the circuit side. The input signals from
the circuit side transit through via holes to the DUT’s pads. The
component-side output signals connect to via holes and to
circuit-side 49.9 Ω termination resistors.
Board Construction
For this board FR4 material was chosen over more exotic board
materials. Tests showed exotic materials to be unnecessary. This
is a 4-layer board. Power is bused on both external and internal
layers. Test structures showed microstrip performance to be
unaffected by the dc bias levels on the plane beneath it.
The manufacturing process should produce a controlledimpedance board. The board stack consists of a 5-mil-thick
layer between external and internal layers. This allows the use of
an 8-mil-wide microstrip trace running from SMA connector to
the DUT’s pads. The narrow trace avoids the need to neck down
the trace width as DUT’s pads are approached and it helps to
control the microstrip trace impedance. The thin 5-mil dielectric
also helps to control crosstalk by way of confining the electromagnetic fields more between the trace and the plane below.
Configuration Programming
The board is configurable by one of two methods. For ease of
use, custom software is provided that controls the AD8151
programming via the parallel port of a PC. This requires a usersupplied standard printer cable that has a DB-25 connector at
one end (parallel- or printer-port interface) and a Centronixtype connector at the other that connects to P2 of the AD8151
evaluation board. The programming with this scheme is done in
a serial fashion, so it is not the fastest way to configure the AD8151
matrix. However, the user interface makes it very convenient to
use this programming method.
If a high-speed programming interface is desired, the AD8151
address and data buses are directly available on P3. The source
of the program signals can be a piece of test equipment, like the
Tektronix HFS-9000 digital test generator, or some other usersupplied hardware that generates programming signals.
When using the PC interface, the jumper at W1 should be
installed and no connections should be made to P3. When using
the P3 interface, no jumper is installed at W1. There are locations for termination resistors for the address and data signals if
these are necessary.
Software Installation
The software to operate the AD8151 is provided on two 3.5"
floppy disks. The software is installed by inserting Disk 1 into
the floppy drive of a PC and running the “setup.exe” program.
This will routinely install the software and prompt the user
when to change to Disk 2. The setup program will also prompt
the user to select the directory for the program.
After running the software, the user will be prompted to identify
which (of three) software driver is used with the PC’s parallel
port. The default is LPT1, which is most commonly used. However, some laptops commonly use the PRN driver. It is also
possible that some systems are configured with the LPT2 driver.
If it is not known which driver is used, it is best to select LPT1
and proceed to the next screen. This will show a full array of
“buttons” that allows the connection of any input to output of
the AD8151. All of the outputs should be in the output “OFF”
state right after the program starts running. Any of the active
buttons can be selected with a mouse click, which will send out
one burst of programming data.
After this, the PC keyboard’s left or right arrow keyboard key
can be held down to generate a steady stream of programming
signals out of the parallel port. The CLOCK test point on the
AD8151 evaluation board can be monitored with an oscilloscope for any activity (user-supplied printer cable must be
connected). If there is a square-wave present, the proper software driver is selected for the PC’s parallel port.
If there is no signal present, another driver should be tried by
selecting the Parallel Port menu item under the “File” pulldown menu selection just under the title bar. Select a different
software driver and carry out the above test until signal activity
is present at the CLOCK test point.
Software Operation
Any button can be clicked in the matrix to program the input to
output connection. This will send the proper programming
sequence out the PC parallel port. Since only one input can be
programmed to a given output at one time, clicking a button in
a horizontal row will cancel the other selection that is already
selected in that row. However, any number of outputs can share
the same input.
A shortcut for programming all outputs to the same input is to
use the broadcast feature. After clicking on the Broadcast Connection button, a screen will appear that will prompt for the
user to select which input should be connected to all outputs.
The user should type in an integer from 0 to 32 and then click
on OK. This will send out the proper program data and return
to the main screen with a full column of buttons selected under
the chosen input.
The Off column can be used to disable to whichever output one
chooses. To disable all outputs, the Global Reset button can be
clicked. This will select the full column of OFF buttons.
Two scratch-pad memories (Memory 1 and Memory 2) are
provided to conveniently save a particular configuration. However, these registers are erased when the program is terminated.
For long-term storage of configurations, the disk-storage memory
should be used. The Save and Load selections can be accessed
from the “File” pull-down menu under the title bar.
–22–
REV. 0
AD8151
AD8151
Figure 18. Evaluation Board Controller
REV. 0
–23–
AD8151
Figure 19. Component Side
–24–
REV. 0
AD8151
Figure 20. Circuit Side
REV. 0
–25–
AD8151
Figure 21. Silkscreen Top
–26–
REV. 0
AD8151
Figure 22. Soldermask Top
REV. 0
–27–
AD8151
Figure 23. Silkscreen Bottom
–28–
REV. 0
AD8151
Figure 24. Soldermask Bottom
REV. 0
–29–
AD8151
Figure 25. INT1 (VEE)
–30–
REV. 0
AD8151
Figure 26. INT2 (VCC)
REV. 0
–31–
AD8151
VEE VCC
VEE VCC
C12
0.01F
C6
0.01F
C8
0.01F
VEE
VEE VCC
C10
0.01F
C14
0.01F
143
144
IN14N
IN14P
IN15N
IN15P
145
146
147
148
149
150
152
151
153
154
155
156
157
158
159
160
161
163
162
164
165
166
167
168
IN13N
IN13P
VEE VCC
VDD
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
169
170
171
IN16N
IN16P
172
173
174
175
IN17N
IN17P
176
177
IN18N
IN18P
178
179
180
181
IN19N
IN19P
182
184
183
1
2
VDD VSS
C13
0.01F
VCC VEE
C30
0.01F
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
PIN 1
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
120
119
118
117
116
AD8151
184L LQFP
TOP VIEW
(Not to Scale)
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
40
41
42
43
44
45
46
99
98
VCC
VEE
OUT00P
OUT00N
VEE
VEE
C60
0.01F
VEE
92
91
90
89
87
88
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
67
68
66
65
64
62
63
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
97
96
95
94
93
VEE
IN12N
IN12P
VEE
IN11N
IN11P
VEE
IN10N
IN10P
VEE
IN09N
IN09P
VEE
IN08N
IN08P
VEE
IN07N
IN07P
VEE
IN06N
IN06P
VEE
IN05N
IN05P
VEE
IN04N
IN04P
VEE
IN03N
IN03P
VEE
IN02N
IN02P
VEE
IN01N
IN01P
VEE
IN00N
IN00P
VEE
VEE
OUT15N
OUT15P
VEE
OUT14N
OUT14P
VEE
OUT13N
OUT13P
VEE
OUT12N
OUT12P
VEE
OUT11N
OUT11P
VEE
OUT10N
OUT10P
VEE
OUT09N
OUT09P
VEE
OUT08N
OUT08P
VEE
OUT07N
OUT07P
VEE
OUT06N
OUT06P
VEE
OUT05N
OUT05P
VEE
OUT04N
OUT04P
VEE
OUT03N
OUT03P
VEE
OUT02N
OUT02P
VEE
OUT01N
OUT01P
VEE
C31
VEE
0.01F
IN20P
VCC
IN20N
VEE
IN21P
IN21N
VEE
IN22P
VCC
IN22N
C32
VEE
0.01F
IN23P
IN23N
VEE
IN24P
IN24N
VEE
IN25P
IN25N
VEE
IN26P
IN26N
VEE
IN27P
IN27N
VEE
IN28P
IN28N
VEE
IN29P
IN29N
VEE
IN30P
IN30N
VEE
IN31P
IN31N
VEE
C11
IN32P
0.01F IN32N
VCC
VEE
VEE
VEE
OUT16N
VCC
C15 OUT16P
VEE
0.01F
VEE
VEE VCC
VCC VEE
C4
0.01F
C29
0.01F
C9
0.01F
R203
1.5k
140
VCC VEE
VEE VCC
139
C7
0.01F
141
C5
0.01F
142
VCC VEE
VEE VCC
Figure 27. Bypassing Schematic
–32–
REV. 0
AD8151
VCC
R19
1.65k
VCC
IN00P
P4
R20
105
P5
IN00N
R21
1.65k
R40
1.65k
VCC
IN06P
VCC
IN12P
P28
P16
R39
105
P17
IN06N
R38
1.65k
VEE
R58
1.65k
VCC
IN18P
R56
1.65k
IN12N
R90
105
P41
VCC
IN24P
IN24N
R92
1.65k
VEE
R116
1.65k
IN30P
OUT08P
R160
49.9
R117
105
P65
R118
1.65k
VEE
OUT08N
R162
49.9
P30
VEE
OUT09P
R28
1.65k
P8
VCC
IN02P
R27
105
P9
R44
1.65k
R165
49.9
P20
R45
105
IN02N
R46
1.65k
VEE
IN08N
R62
1.65k
P32
R63
105
R85
1.65k
P44
VCC
IN20P
R175
49.9
IN20N
IN26P
R99
105
OUT11P
R112
1.65k
P68
IN26N
R125
49.9
VTT
OUT01N
R127
49.9
OUT02P
R130
49.9
P99
R111
105
VTT
OUT02N
P82
R132
49.9
VTT
OUT11
N
R172
49.9
OUT12P
R185
49.9
VTT
OUT03N
R133
49.9
VEE
VEE
OUT04P
R140
49.9
IN32N
P79
VTT
OUT12N
R183
49.9
IN15P
OUT13P
OUT04N
P78
R180
49.9
IN15N
OUT13N
P95
VTT
R142
49.9
P94
R145
OUT05P 49.9
VTT
VTT
R67
1.65k
P98
R135
OUT03P 49.9
R170
49.9
IN32P
R110
1.65k
R66
105
P35
P102
P69
R100
1.65k
VEE
R173
49.9
VCC
P34
OUT01P
VCC
P57
R83
1.65k
VEE
R98
1.65k
P56
R84
105
P45
IN14N
R65
1.65k
R122
49.9
VTT
VCC
IN14P
R64
1.65k
VEE
OUT10P
OUT10N
P33
P21
R26
1.65k
OUT09N
R163
49.9
IN13N
VCC
IN08P
OUT00N
P86
P83
VEE
VCC
VTT
IN13P
R61
1.65k
R121
49.9
VTT
R60
105
P31
P103
OUT00P
IN30N
VCC
R59
1.65k
P87
VTT
P64
R93
105
P53
IN18N
R91
1.65k
VEE
R94
1.65k
P52
P40
R57
105
P29
VEE
R89
1.65k
R182
49.9
OUT05N
R143
49.9
OUT06P
R150
49.9
VEE
VCC
R34
1.65k
P12
VCC
IN04P
R33
105
P13
R32
1.65k
VEE
IN04N
R50
1.65k
P24
VCC
IN10P
R51
105
P25
R52
1.65k
IN10N
R68
1.65k
P36
IN16P
R69
105
P37
R79
1.65k
P48
IN16N
VEE
VCC
IN22P
OUT14P
R104
1.65k
P60
R78
105
P49
R70
1.65k
VEE
VCC
R105
105
P38
OUT14N
IN22N
VEE
R106
1.65k
IN28N
OUT15P
IN01, IN03, IN05, IN07,
IN09, IN11, IN19, IN21,
IN23, IN25, IN27, IN29, IN31
OUT15N
R192
49.9
OUT16P
R200
49.9
N
OUT16N
R198
49.9
OUT07N
–33–
R153
49.9
C16
0.01F
P71
VCC
VTT
C82
0.01F
VCC
VTT
P70
C83
0.01F
VTT
Figure 28. Evaluation Board Input/Output Schematic
P90
VTT
VTT
VEE
REV. 0
R152
49.9
R155
OUT07P 49.9
P
P39
IN17N
OUT06N
P74
R190
49.9
VEE
R72
105
R73
1.65k
VTT
VTT
VCC
IN17P
R193
49.9
P61
R77
1.65k
P91
P75
VTT
IN28P
VCC
R71
1.65k
R195
49.9
VCC
AD8151
CLK
A1
1
CLK P2 6
74HC14
DATA
3
DATA P2 5
A1
4
74HC14
VSS P2 25
2
5
1
A1
2
6
3
74HC14
4
5
VSS
6
7
VDD
8
9
10
VSS
VCC
OUT_EN
20
19
1
VDD
2
Q0
18
Q1
17
Q2
D2
16
Q3
D3
A2
15
D4 74HC74 Q4
14
Q5
D5
13
Q6
D6
12
Q7
D7
11
CLK
GND
D0
D1
3
OUT_EN
VCC
Q0
D0
Q1
D1
4
Q2
D2
5
D3
Q3
A3
6
D4 74HC74 Q4
7
D5
Q5
8
D6
Q6
9
D7
Q7
10
GND
CLK
VDD
VSS
20
19
A1
9
VDD
VDD
8
74HC14
A1
11
10
18
17
74HC14
A1
12
16
15
13
14
12
74HC14
A4
9
11
10
13
8
74HC132
A4
12
13
R7
49.0
VSS
VSS
VSS
1
A4
2
74HC132
WRITE
RESET
READ
D0
A4
A3
A2
A1
A0
D6
D5
D4
D3
D2
D1
UPDATE
CHIP_SELECT
VDD
P3 13
P3 7
P3 11
P3 27
P3 25
P3 23
P3 21
P3 19
P3 17
P3 39
P3 37
P3 35
P3 33
P3 31
P3 29
P3 15
P3 9
P3 5
VSS P3 14
P3 8
P3 12
P3 28
P3 26
P3 24
P3 22
P3 20
P3 18
P3 40
P3 38
P3 36
P3 34
P3 32
P3 30
P3 16
P3 10
P3 6
VSS
164A0
VSS
VSS
P2 7
P2 3
P2 8
P2 4
P2 2
VSS
163A1
3
4
5
VSS
A4
153D6
R13
49.0
154D5
R14
49.0
162A2
R11
49.0
W1
READ
RESET
WRITE
UPDATE
CHIP_SELECT
VSS
R10
49.0
VSS
VDD
161A3
R9
49.0
VSS
R1
20k
VSS
74HC132
R12
49.0
160A4
R8
49.0
155D4
R15
49.0
156D3
R16
49.0
157D2
R17
49.0
158D1
R18
49.0
6
VSS
11
159D0
74HC132
TP5
TP6
TP4
TP20
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP7
TP8
VDD
VSS
VSS
VSS
VSS
VSS
VSS
R2
49.0
R3
49.0
R4
49.0
R5
49.0
R6
49.0
CHIP_SELECT
168
UPDATE
165
VTT P1 6
C3
+ 10F
WRITE
166
VCC P1 1
P1 2
RESET
169
VEE
READ
167
P1 3
P1 4
VDD P1 7
VSS P1 5
+ C1
10F
+ C2
10F
VTT
VTT
A1, 4 PIN 14 IS TIED TO VDD.
A1, 4 PIN 7 IS TIED TO VSS.
VCC
VCC
VEE
VEE
VDD
C86
0.1F
VDD
C87
0.1F
VDD
C88
0.1F
VDD
C89
0.1F
VDD
VSS
VSS
VSS
VSS
VSS
P104
P105
Figure 29. Evaluation Board Logic Controls
–34–
REV. 0
AD8151
OUTLINE DIMENSIONS
Dimensions shown in mm and (inches).
184-Lead Plastic LQFP
(ST-184)
1.60 (0.063)
MAX
0.75 (0.030)
0.60 (0.024)
0.45 (0.018)
SEATING
PLANE
22.00 (0.866) BSC SQ
20.00 (0.787) BSC SQ
186
1
139
138
PIN 1
TOP VIEW
(PINS DOWN)
0.08 (0.003)
0.15 (0.006)
0.05 (0.002)
1.45 (0.057)
1.40 (0.053)
1.35 (0.048)
46
47
93
92
0.40 (0.016)
BSC
0.23 (0.009)
0.18 (0.007)
0.13 (0.005)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
REV. 0
–35–
–36–
PRINTED IN U.S.A.
C02169–1.5–4/01(0)