NCP81234 D

NCP81234
Dual-Channel/Two-Phase
Controller for DrMOS
The NCP81234, a dual−channel/two−phase synchronous buck
controller, provides flexible power management solutions for
applications supported by DrMOS. Operating in high switching
frequency up to 1.2 MHz allows employing small size inductor and
capacitors.
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Features
Typical Applications
Telecom Applications
Server and Storage System
Multiple Rail Systems
DDR Applications
MARKING DIAGRAM
1
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
XXXXX = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
26
25
24
23
22
ILMT1
OTP1
COMP1
FB1
PWM1
1 VIN
27
VREF
PINOUT
28
ISP1 21
ISN1 20
2 EN1
ISP2 19
3 EN2
GND
29
4 DRVON
ISN2 18
5 PGOOD1
PWM2 17
6 PGOOD2
FB2 16
COMP2 15
SS
FSET
CNFG
ILMT2
OTP2
/REFIN
7 FAULT
DLY2
/DDR
•
•
•
•
28
1
VCC5V
•
•
•
•
•
•
•
•
•
•
•
•
Single Vin = 4.5 ~ 20 V with Input Feedforward
Integrated 5.35 V LDO
Vout = 0.6 V ~ 5.3 V
Fsw = 200 k ~ 1.2 MHz
PWM Output Compatible to 3.3 V and 5 V DrMOS
Dual−Channel or Two−Phase Operation
DDR Power Mode Option
Interleaved Operation
Differential Current Sense Compatible for both Inductor DCR Sense
and DrMOS Iout
2 Independent Enables with Programmable Input UVLO
Programmable DrMOS Power Ready Detection (DRVON)
2 Power Good Indicators
Comprehensive Fault Indicator
Externally Programmable Soft Start and Delay Time
Programmable Hiccup Over Current Protection
Hiccup Under Voltage Protection
Recoverable Over Voltage Protection
Hiccup Over Temperature Protection
Thermal Shutdown Protection
QFN−28, 5x5 mm, 0.5 mm Pitch Package
This is a Pb−Free Device
DLY1
•
•
•
•
•
•
•
•
•
QFN28
MN SUFFIX
CASE 485BQ
8
9
10
11
12
13
14
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP81234MNTXG
QFN28
(Pb−Free)
5000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 0
1
Publication Order Number:
NCP81234/D
NCP81234
Table 1. PIN DESCRIPTION
Pin
Name
Type
Description
1
VIN
Power Input
Power Supply Input. Power supply input pin of the device, which is connected to the integrated
5 V LDO. 4.7 mF or more ceramic capacitors must bypass this input to power ground. The capacitors should be placed as close as possible to this pin.
2
EN1
Analog Input
Enable 1. Logic high enables channel 1 and logic low disables channel 1. Input supply UVLO
can be programmed at this pin for channel 1.
3
EN2
Analog Input
Enable 2. Logic high enables channel 2 and logic low disables channel 2. Input supply UVLO
can be programmed at this pin for channel 2.
4
DRVON
Logic Input
5
PGOOD1
Logic Output
Power GOOD 1. Open−drain output. Provides a logic high valid power good output signal, indicating the regulator’s output is in regulation window of channel 1.
6
PGOOD2
Logic Output
Power GOOD 2. Open−drain output. Provides a logic high valid power good output signal, indicating the regulator’s output is in regulation window of channel 2.
7
FAULT
Logic Output
Fault. Digital output to indicate fault mode.
8
DLY1
Analog Input
Delay 1. A resistor from this pin to GND programs delay time of soft start for channel 1.
9
DLY2/DDR
Analog Input
Delay 2 / DDR. A resistor from this pin to GND programs delay time of soft start for channel 2.
Short to GND to have DDR operation mode.
10
SS
Analog Input
Soft Start Time. A resistor from this pin to ground programs soft start time for both channels.
11
FSET
Analog Input
Frequency Selection. A resistor from this pin to ground programs switching frequency.
12
CNFG
Analog Input
Configuration. A resistor from this pin to ground programs configuration of power stages.
13
ILIMT2
Analog Input
Limit of Current 2. Voltage at this pin sets over−current threshold for channel 2.
14
OTP2/REFIN
Analog Input
Over Temperature Protection 2. Voltage at this pin sets over−temperature threshold for channel 2.
15
COMP2
Analog Output
16
FB2
Analog Input
17
PWM2
Analog Output
18
ISN2
Analog Input
Current Sense Negative Input 2. Inverting input of differential current sense amplifier of phase 2.
19
ISP2
Analog Input
Current Sense Positive Input 2. Non−inverting input of differential current sense amplifier of
phase 2.
20
ISN1
Analog Input
Current Sense Negative Input 1. Inverting input of differential current sense amplifier of phase 1.
21
ISP1
Analog Input
Current Sense Positive Input 1. Non−inverting input of differential current sense amplifier of
phase 1.
22
PWM1
Analog Output
23
FB1
Analog Input
24
COMP1
Analog Output
25
OTP1
Analog Input
26
ILIMT1
Analog Input
27
VREF
Analog Output
Output of Reference. Output of 0.6 V reference. A 10 nF ceramic capacitor bypasses this input
to GND. This capacitor should be placed as close as possible to this pin.
28
VCC5V
Analog Power
Voltage Supply of Controller. Output of integrated 5.35 V LDO and power supply input pin of
control circuits. A 4.7 mF ceramic capacitor bypasses this input to GND. This capacitor should be
placed as close as possible to this pin.
29
THERM/GND Analog Ground
Driver On. Logic high input means drivers’ power is ready.
Compensation 2. Output pin of error amplifier of channel 2.
Feedback 2. An inverting input of internal error amplifier for channel 2.
PWM 2. PWM output of phase 2.
PWM 1. PWM output of phase 1.
Feedback 1. An inverting input of internal error amplifier for channel 1.
Compensation 1. Output pin of error amplifier of channel 1.
Over Temperature Protection 1. Voltage at this pin sets over−temperature threshold for channel 1.
Limit of Current 1. Voltage at this pin sets over−current threshold for channel 1.
Thermal Pad and Analog Ground. Ground of internal control circuits. Must be connected to the
system ground.
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2
NCP81234
VIN
VIN
VIN
VCIN
Vout1
DISB#
VSWH
VCC5V
ZCD_EN#
VREF
VREF
PWM1
EN1
ISP1
EN1
ISP1
PGOOD1
ISN1
PGOOD1
NCP5339
PWM
CGND
PGND
ISN1
ISP1
ISN1
EN2
EN2
PGOOD2
PGOOD2
Vout1
DLY1
FB1
DLY2
COMP1
SS
VIN
CNFG
FSET
NCP81234
VIN
VCIN
Vout2
DISB#
VSWH
ZCD_EN#
PWM2
NCP5339
PWM
ISP2
CGND
PGND
ISP2
ISP2
ISN2
ISN2
ISN2
Vout2
FB2
COMP2
GND
Figure 1. Typical Application Circuit for Dual−Channel Applications
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3
NCP81234
VIN
VIN
VCIN
VIN
Vout1
DISB#
VSWH
VCC5V
ZCD_EN#
VREF
VREF
PWM1
ISP1
EN1
EN1
ISP1
PGOOD1
ISN1
NCP5339
PWM
CGND
PGND
ISN1
PGOOD1
ISP1
ISN1
EN2
Vout1
DLY1
FB1
COMP1
SS
VIN
CNFG
FSET
NCP81234
VIN
VCIN
DISB#
VSWH
ZCD_EN#
PWM2
NCP5339
PWM
ISP2
CGND
PGND
ISP2
ISP2
ISN2
ISN2
ISN2
GND
Figure 2. Typical Application Circuit for Two−Phase Applications
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4
NCP81234
VIN
VIN
VIN
Vout1
PWM1
VCC5V
PWM
VSWH
NCP81293
VREF
TOUT
ISP1
VTEMP1
REFIN
IOUT
CGND
PGND
ISP1
ISP1
ISN1
ISN1
ISN1
VIN
ILMT1
OTP1
VIN
PWM
PWM2
VSWH
NCP81293
VTEMP1
TOUT
CGND
ISP2
VCC5V
REFIN
IOUT
PGND
ISP2
ISP2
NCP81234
ISN2
ISN2
ISN2
DLY1
Vout1
SS
FB1
CNFG
COMP1
FSET
EN1
EN1
PGOOD1
PGOOD1
EN2
GND
Figure 3. Typical Two−Phase Application Circuit for DrMOS with Integrated Current Sense and Temperature Sense
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5
NCP81234
VIN
VCC5V
GND
PWM1
5V LDO
FB1
Dual−Channel
/
Two −Phase
FB2
VREF
COMP1
Reference
PWM
Control
COMP2
OC1
&
DRVON
OC2
Protections
EN1
OT1
UVLO
&
PGOOD
EN2
PGOOD1
PWM2
OT2
PGOOD2
ISP1
FAULT
CS1
ISN1
CNFG
FSET
ISP2
Programming
Detection
SS
NCP81234
CS2
ISN2
DLY 1
DLY 2/DDR
OC1
COMP1
ILMT1
Current Limit
OC2
ILMT2
FB1
CS1
0.6V
REFIN
CS2
MUX
OT1
FB2
OT2
COMP2
Figure 4. Functional Block Diagram
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6
OTP1
Over
Temperature
Protection
OTP2/REFIN
NCP81234
Table 2. MAXIMUM RATINGS
Value
Rating
Symbol
Power Supply Voltage to PGND
VVIN
Supply Voltage VCC5V to GND
VVCC5V
Other Pins to GND
Min
Max
Unit
30
V
−0.3
6.5
V
−0.3
VCC5V + 0.3
V
V
Human Body Model (HBM) ESD Rating (Note 1)
ESD HBM
2000
Machine Model (MM) ESD Rating (Note 1)
ESD MM
200
Latch up Current: (Note 2)
All pins, except digital pins
Digital pins
ILU
V
mA
−100
−10
100
10
Operating Junction Temperature Range (Note 3)
TJ
−40
125
°C
Operating Ambient Temperature Range
TA
−40
125
°C
Storage Temperature Range
TSTG
−55
150
°C
Thermal Resistance Junction to Top Case (Note 4)
RYJC
5.0
°C/W
Thermal Resistance Junction to Board (Note 4)
RYJB
3.8
°C/W
Thermal Resistance Junction to Ambient (Note 4)
RθJA
38
°C/W
PD
2.63
W
MSL
1
−
Power Dissipation (Note 5)
Moisture Sensitivity Level (Note 6)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device is ESD sensitive. Handling precautions are needed to avoid damage or performance degradation.
2. Latch up Current per JEDEC standard: JESD78 class II.
3. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
4. JEDEC standard JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM. It is for checking junction temperature using external measurement.
5. The maximum power dissipation (PD) is dependent on input voltage, maximum output current and external components selected. TA = 25°C,
TJ_max = 125°C, PD = (TJ_max−T_amb)/Theta JA
6. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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7
NCP81234
Table 3. ELECTRICAL CHARACTERISTICS (VIN = 12 V, typical values are referenced to TA = 25°C, Min and Max values are
referenced to TA from −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
12
20
V
SUPPLY VOLTAGE
(Note 7)
VIN
4.5
VCC5V Under−Voltage (UVLO)
Threshold
VCC5V falling
VCCUV−
3.7
VCC5V OK Threshold
VCC5V rising
VIN Supply Voltage Range
VCC5V UVLO Hysteresis
V
VCCOK
4.3
VCCHYS
260
V
mV
VCC5V REGULATOR
Output Voltage
6 V < VIN < 20 V, IVCC5V = 15 mA
(External), EN1 = EN2 = Low
VCC
5.2
5.35
5.5
V
−2.0
0.2
2.0
%
200
mV
Load Regulation
IVCC5V = 5 mA to 25 mA (External),
EN1 = EN2 = Low
Dropout Voltage
VIN = 5 V, IVCC5V = 25 mA (External),
EN1 = EN2 = Low
VDO_VCC
VIN Quiescent Current
EN1 high, 1 channel and 1 phase only EN1
and EN2 high, 2 channel and 2 phase
IQVIN
−
−
15
18
20
25
mA
VIN Shutdown Current
EN1 and EN2 low
IsdVIN
−
8
10
mA
VFB
596
594
600
600
604
606
mV
VVREF
594
600
606
mV
1.0
%
SUPPLY CURRENT
REGULATION REFERENCE
Regulated Feedback Voltage
Include offset of error
amplifier
0°C to 85°C
–40°C to 125°C
REFERENCE OUTPUT
VREF Output Voltage
Load Regulation
IVREF = 500 mA
IVREF = 0 mA to 2 mA
−1.0
VOLTAGE ERROR AMPLIFIER
Open−Loop DC Gain
(Note 7)
GAINEA
80
dB
Unity Gain Bandwidth
(Note 7)
GBWEA
20
MHz
Slew Rate
(Note 7)
SRCOMP
20
V/ms
ICOMP(source) = 2 mA
VmaxCOMP
3.2
3.4
−
ICOMP(sink) = 2 mA
VminCOMP
−
1.05
1.15
VFB = VREFIN = 1.0 V
IFB
−400
COMP Voltage Swing
FB, REFIN Bias Current
400
V
nA
DIFFERENTIAL CURRENT−SENSE AMPLIFIER
DC Gain
GAINCA
6
V/V
BWCA
10
MHz
−3 dB Gain Bandwidth
(Note 7)
Input Common Mode Voltage Range
(Note 7)
−0.2
Differential Input Voltage Range
(Note 7)
−60
Input Bias Current
ISP,ISN = 2.5 V
ICS
−100
−
VCC+0.1
V
60
mV
100
nA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Guaranteed by design, not tested in production.
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8
NCP81234
Table 3. ELECTRICAL CHARACTERISTICS (VIN = 12 V, typical values are referenced to TA = 25°C, Min and Max values are
referenced to TA from −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
Rfs = 2.7k
Rfs = 5.1k
Float
Rfs = 8.2k
Short to GND
Rfs = 13k
Rfs = 20k
Rfs = 33k
FSW
180
270
360
450
540
720
900
1080
200
300
400
500
600
800
1000
1200
220
330
440
550
660
880
1100
1320
kHz
IFS
45
50
55
mA
TRST
1.8
2.0
2.2
ms
TDL
−
0.9
1.8
2.7
3.6
7.2
10.8
18
−
0
1.0
2.0
3.0
4.0
8.0
12
20
TDL1
−
1.1
2.2
3.3
4.4
8.8
13.2
22
−
ms
IDL
45
50
55
mA
TSS
0.9
2.7
3.6
5.4
1.0
3.0
4.0
6.0
1.1
3.3
4.4
6.6
ms
0.9
2.7
3.6
5.4
1.0
3.0
4.0
6.0
1.1
3.3
4.4
6.6
45
50
55
SWITCHING FREQUENCY
Switching Frequency
Source Current
SYSTEM RESET TIME
System Reset Time
Measured from EN to start of soft start
with TDL = 0 ms
DELAY TIME
Delay Time
Float
Rdl = 33k
Rdl = 20k
Rdl = 13k
Rdl = 8.2k
Rdl = 5.1k
Rdl = 2.7k
Short to GND
(DLY1 Only)
Short to GND (DDR
Mode, DLY2 Only)
(Note 7)
Source Current
SOFT START TIME
Soft Start Time
OTP Configuration 1
(Note 7)
Rss = 13k
Float
Rss = 20k
Rss = 33k
OTP Configuration 2
(Note 7)
Rss = 2.7k
Short to GND
Rss = 5.1k
Rss = 8.2k
Source Current
ISS
mA
CONFIGURATION
PWM Configuration
CNFG pin is Float
Channel 1
Channel 2
PWM1
PWM2
(Note 7)
CNFG shorted to GND
PWM1, PWM2
Source Current
ICNFG
45
50
55
mA
PGOOD
PGOOD Startup Delay
PGOOD Shutdown Delay
PGOOD Low Voltage
PGOOD Leakage Current
Measured from end of Soft Start to
PGOOD assertion
Td_PGOOD
Measured from EN to PGOOD
de−assertion
100
ms
240
ns
IPGOOD = 4 mA (sink)
VlPGOOD
−
−
0.3
V
PGOOD = 5 V
IlkgPGOOD
−
−
1.0
mA
Isource = 0.5 mA
VFAULT_H
VCC−0.5
FAULT
FAULT Output High Voltage
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Guaranteed by design, not tested in production.
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9
NCP81234
Table 3. ELECTRICAL CHARACTERISTICS (VIN = 12 V, typical values are referenced to TA = 25°C, Min and Max values are
referenced to TA from −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Isink = 0.5 mA
VFAULT_L
Measured from ILIMT ISP−ISN = 50 mV
to GND
ISP−ISN = 20 mV
VOCTH+
Measured from ILIMT ISP−ISN = −50 mV
to GND (only active in
non−latched OVP) ISP−ISN = −20 mV
VOCTH−
Min
Typ
Max
Unit
0.5
V
mV
FAULT
FAULT Output Low Voltage
PROTECTIONS
Positive Current Limit Threshold
Negative Current Limit Threshold
Positive Over Current Protection
(OCP) Debounce Time
(Note 7)
Under Voltage Protection (UVP)
Threshold
Voltage from FB to GND
VUVTH
Under Voltage Protection (UVP)
Hysteresis
Voltage from FB to GND
VUVHYS
Under Voltage Protection (UVP)
Debounce Time
Shutdown Time in Hiccup Mode
300
315
110
120
130
285
300
315
110
120
130
500
510
mV
ms
8 Cycles
520
mV
20
mV
(Note 7)
1.5
ms
UVP (Note 7)
OCP (Note 7)
OTP (Note 7)
12*TSS
16*TSS
8*TSS
ms
First−Level Over Voltage Protection
(OVP_L) Threshold
Voltage from FB to GND
VOVTH_L
First−Level Over Voltage Protection
(OVP_L) Hysteresis
Voltage from FB to GND
VLOVHYS
First−Level Over Voltage Protection
(OVP_L) Debounce Time
(Note 7)
Second−Level Over Voltage Protection
(OVP_H) Threshold
Voltage from FB to GND
VOVTH_H
Second−Level Over Voltage Protection
(OVP_H) Hysteresis
Voltage from FB to GND
VHOVHYS
Second−Level Over Voltage Protection
(OVP_H) Debounce Time
(Note 7)
Offset Voltage of OTP Comparator
285
VILMT = 200 mV
OTP Source Current
650
710
VOS_OTP
−2
IOTP
9
OTP Debounce Time
(Note 7)
Thermal Shutdown (TSD) Threshold
(Note 7)
Tsd
Recovery Temperature Threshold
(Note 7)
Trec
Thermal Shutdown (TSD) Debounce
Time
(Note 7)
140
660
670
mV
−20
mV
1.0
ms
720
730
mV
−20
mV
1.0
ms
10
2
mV
11
mA
160
ns
165
°C
125
°C
120
ns
ENABLE
EN ON Threshold
Hysteresis Source Current
VCC5V is OK
VEN_TH
0.75
0.8
0.85
V
IEN_HYS
25
30
35
mA
VDRVON_TH
0.75
0.8
0.85
V
IDRVON_HYS
25
30
35
mA
DRVON
DRVON ON Threshold
Hysteresis Source Current
VCC5V is OK
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Guaranteed by design, not tested in production.
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NCP81234
Table 3. ELECTRICAL CHARACTERISTICS (VIN = 12 V, typical values are referenced to TA = 25°C, Min and Max values are
referenced to TA from −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Minimum On Time
(Note 7)
Ton_min
Minimum Off Time
(Note 7)
Toff_min
Min
Typ
Max
Unit
50
ns
PWM MODULATION
160
ns
0% Duty Cycle
COMP voltage when the PWM outputs
remain Lo (Note 7)
1.3
V
100% Duty Cycle
COMP voltage when the PWM outputs
remain HI, Vin = 12.0 V (Note 7)
2.5
V
Ramp Feed−forward Voltage Range
(Note 7)
4.5
20
V
PWM OUTPUT
PWM Output High Voltage
Isource = 0.5 mA
VPWM_H
PWM Output Low Voltage
Isink = 0.5 mA
VPWM_L
Rise and Fall Times
VCC−0.2
0.2
CL (PCB) = 50 pF, measured between
10% & 90% of VCC (Note 7)
Leakage Current in Hi−Z Stage
V
V
10
ILK_PWM
−1.0
ns
mA
1.0
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Guaranteed by design, not tested in production.
Table 4. RESISTOR OPTIONS FOR FUNCTION PROGRAMMING
Resistance Range (kW)
Resistor Options (kW)
Min
Typ
Max
±5%
±1%
2.565
2.7
2.835
2.7
2.61
2.67
2.74
2.80
4.845
5.1
5.355
5.1
4.87
4.99
5.11
5.23
7.79
8.2
8.61
8.2
7.87
8.06
8.25
8.45
12.35
13
13.65
13
12.4
12.7
13
13.3
19
20
21
20
19.1
19.6
20
20.5
31.35
33
34.65
33
31.6
32.4
33.2
34
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NCP81234
DETAILED DESCRIPTION
General
Soft Start
The NCP81234, a dual−channel/two−phase synchronous
buck controller, provides flexible power management
solutions for applications supported by DrMOS. Operating
in high switching frequency up to 1.2 MHz allows
employing small size inductor and capacitors.
The NCP81234 has a soft start function and the soft start
time is externally programmed at SS pins. The output starts
to ramp up following a system reset period TRST and a
programmable delay time TDLY after the device is enabled
and both VCC5V and DRVON are ready. The device is able
to start up smoothly under an output pre−biased condition
without discharging the output before ramping up.
VCC5V
VCC5V
VCCOK
DRVON
DRVON
VDRVON_OK
EN
EN
TRST
T DLY
T SS
TRST
T d_PGOOD
Vout
Vout
PGOOD
PGOOD
Tri−State
T DLY
T SS
T d_PGOOD
Tri−State
PWM
PWM
(1) VCC5V and DRVON Ready before EN
(2) VCC5V and DRVON Ready after EN
Figure 5. Timing Diagrams of Power Up Sequence
VCC5V
VCC5V
DRVON
DRVON
EN
EN
VDRVON _F
VDRVON _OK
T RST
Vout
Vout
PGOOD
PGOOD
T SS
T d_PGOOD
Tri −State
Tri−State
PWM
T DLY
PWM
Figure 6. Timing Diagram of Power Down
Sequence
Figure 7. Timing Diagram of DRVON UVLO
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12
NCP81234
VCC OK
VCC UVLO
VCC
5V
VDRVON_TH
EN_Int
DRV
ON
IDRVON_HYS
VEN_TH
EN
IEN_HYS
Figure 8. Enable, DRVON, and VCC UVLO
Enable and Input UVLO
The low threshold in ENABLE signal is
The NCP81234 is enabled when the voltage at EN pin is
higher than an internal threshold VEN_TH = 0.8 V. A
hysteresis can be programmed by an external resistor REN
connected to EN pin as shown in Figure 9. The high
threshold in ENABLE signal is
V EN_H + V EN_TH
V EN_L + V EN_TH * V EN_HYS
(eq. 2)
The programmable hysteresis in ENABLE signal is
V EN_HYS + I EN_HYS @ R EN
(eq. 3)
(eq. 1)
VEN_TH
EN_Int
VEN_H
VEN_L
ENABLE
EN
REN
IEN_HYS
Figure 9. Enable and Hysteresis Programming
A UVLO function for input power supply can be
implemented at EN pins. As shown in Figure 10, the UVLO
threshold can be programmed by two external resistors.
V IN_H +
ǒ
R EN1
R EN2
Ǔ
) 1 @ V EN_TH
(eq. 4)
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13
V IN_L + V IN_H * V IN_HYS
(eq. 5)
V IN_HYS + I EN_HYS @ R EN1
(eq. 6)
NCP81234
VIN_H
VEN_TH
VIN_L
VIN
EN_Int
REN1
EN
REN2
IEN_HYS
Figure 10. Enable and Input Supply UVLO Circuit
To avoid undefined operation, EN pins cannot be left float in applications.
DDR Mode Operation
EN
DLY2 /
DDR
COMP2
EN2
EN1
COMP2
0.6V
DAC2
DLY 2/DDR
Detector
OTP2/
REFIN
FB2
Out High if pin is
grounded.
VTT
VDDQ
Figure 11. Block Diagram of DDR Mode Operation
In DDR mode, two channels have independent fault
detections and protections but have hiccup together if
anyone of them needs to start a hiccup.
As shown in Figure 11, if DLY2/DDR pin is shorted to
GND before the device starts up, the NCP81234 is internally
configured to operate in DDR mode. The two enable pins
need to be connected together. The channel 1 provides
power for VDDQ rail and the channel 2 provides power for
VTT rail. The both channels have the same delay time
programmed at DLY1 pin, and VTT rail always tracks with
VDDQ/2. An external resistor divider, which is connected
from VDDQ to GND, is employed to get 0.6 V at REFIN pin
in steady−state operation. Another external resistor divider,
which is connected from VTT to GND, is applied to obtain
an expected VTT voltage considering FB2 voltage is 0.6 V
as REFIN.
Over Voltage Protection (OVP)
A two−level recoverable over voltage protection is
employed in the NCP81234, which is based on voltage
detection at FB pin. If FB voltage is over VOVTH_L (660 mV
typical) for more than 1 ms, the first over voltage protection
OVPL is triggered and PGOOD is pulled low. In the
meanwhile, all the high−side MOSFETs are turned off and
all the low−side MOSFETs are turned on. A negative current
protection in low−side MOSFETs is active in this protection
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14
NCP81234
Under Voltage Protection (UVP)
level, and it turns off low−side MOSFET for at least 50 ns
if negative current is over the limit. However, in a worse case
that FB voltage rises to be over VOVTH_H (720 mV typical)
for more than 1 ms, the second level over voltage protection
OVPH takes in charge. As same as the first level OVP, all the
high−side MOSFETs are turned off and all the low−side
MOSFETs are turned on, but the negative current protection
is disabled. The over voltage protection can be cleared once
FB voltage drops 20 mV lower than VOVTH_L, and then the
system comes back to normal operation.
OVPH detection starts from the beginning of soft−start
time TSS and ends in shutdown and idle time of hiccup mode
caused by other protections, while OVPL detection starts
after PGOOD delay (Td_PGOOD) is expired and ends at the
same time as OVPH.
The NCP81234 pulls PGOOD low and turns off both
high−side and low−side MOSFETs once FB voltage drops
below VUVTH (540 mV typical) for more than 1.5 ms. Under
voltage protection operates in a hiccup mode. A normal
power up sequence happens after a hiccup interval.
UVP detection starts when PGOOD delay (Td_PGOOD) is
expired right after a soft start, and ends in shutdown and idle
time of hiccup mode.
Over Current Protection (OCP)
The NCP81234 senses phase currents by differential
current sense amplifiers and provides a cycle−by−cycle over
current protection for each phase. If OCP happens in all the
phases of the same channel and lasts for more than 8 times
of switching cycle, the channel shuts down and enters into
a hiccup mode. The channel may enter into hiccup mode
sooner due to the under voltage protection in a case if the
output voltage drops down very fast.
ISP
ISP
ISP
ISP
6
6
ISN
ISN
RNTC
OCP
ISN
ISN
OCP
RT2
RILMT1
ILMT
VREF
ILMT
RT3
RT1
OTP
RILIM2
0.6V
VREF
OTP
ROTP2
ROTP2
OTP
VT
OTP
ROTP1
10uA
10uA
(1) OTP Configuration 1
ROTP1
(2) OTP Configuration 2
Figure 12. Over−Current Protection and Over−Temperature Protection
Over Temperature Protection (OTP)
The over−current threshold can be externally
programmed at the ILIM pin for each channel. As shown in
Figure 12 (1), a NTC resistor RNTC can be employed for
temperature compensated over current protection. The peak
current limit per phase can be calculated by
V ISP * V ISN +
1
@
6
R T3
R T1 )
[email protected] NTC
RT2)RNTC
The NCP81234 provides over temperature protection for
each channel. To serve different types of DrMOS, one of two
internal configurations of OTP detection can be selected at
SS pin combined with a soft start time programming.
With OTP Configuration 1, as shown in Figure 12 (1), the
NTC resistor RNTC senses the hot−spot temperature and
changes the voltage at ILMT pin. Both over−temperature
threshold and hysteresis are externally programmed at OTP
pin by a resistor divider. Once the voltage at ILMT pin is
higher than the voltage at OTP pin, OTP trips and the
channel is shut down. The channel will have a normal start
up after a hiccup interval in condition that the temperature
drops below the OTP reset threshold. The OTP assertion
threshold VOTP and reset threshold VOTP_RST can be
calculated by
(eq. 7)
@ V REF
) R T3
If no temperature compensation is needed, as shown in
Figure 12 (2), the peak current limit per phase can be simply
set by
V ISP * V ISN +
R ILIM2
1
@
@ V REF
6 R ILIM1 ) R ILIM2
(eq. 8)
OCP detection starts from the beginning of soft−start time
TSS, and ends in shutdown and idle time of hiccup mode.
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15
NCP81234
V OTP +
V REF ) I OTP_HYS @ R OTP1
1)
reference voltage. If the voltage is over the threshold OTP
happens. The OTP assertion threshold VOTP and reset
threshold VOTP_RST in this configuration can be obtained by
(eq. 9)
ROTP1
ǒ
ROTP2
V T_OTP + 1 )
V OTP_RST +
V REF @ R OTP2
(eq. 10)
R OTP1 ) R OTP2
V T_OTP_RST +
The corresponding OTP temperature TOTP and reset
temperature TOTP_RST can be calculated by
T OTP +
1
ǒ
Ǔ
ln R NTC_OTPńRNTC
1
)
25)273.15
B
T OTP_RST +
ǒ
(eq. 11)
where
1
1
R T_OTP*RT1
R NTC_OTPRST +
R T_OTP +
ǒ
R T_OTPRST +
ǒ
* 1
(eq. 13)
RT2
1
V OTP
Ǔ
* 1 @ R T3
V REF
V OTP_RST
(eq. 17)
* I OTP_HYS @ R OTP1 ) 0.6
(eq. 18)
FAULT Indicator
(eq. 14)
* 1
RT_OTPRST*RT1
RT2
The NCP81234 has a comprehensive fault indicator by
means of a cycle−by−cycle fault signal output from FAULT
pin. Figure 13 shows a typical timing diagram of FAULT
signal. FAULT signal is composed of ALEART and two
portions of fault flags for the two channels, having a total
cycle period of 36 ms. A corresponding fault flag is asserted
to high once the fault happens. The periodic fault signal
starts from the point where any fault has been confirmed and
ends after PGOOD is asserted again. Note the last FAULT
cycle has to be complete after PGOOD assertion.
1
V REF
@ 0.6
The NCP81234 has an internal thermal shutdown
protection to protect the device from overheating in an
extreme case that the die temperature exceeds 165°C. TSD
detection is activated when VCC5V and at least one of ENs
are valid. Once the thermal protection is triggered, the whole
chip shuts down and all PWM signals are in high impedance.
If the temperature drops below 125°C, the system
automatically recovers and a normal power sequence
follows.
ln RNTC_OTPRSTńRNTC
(eq. 12)
1
)
25)273.15
B
R NTC_OTP +
Ǔ
Ǔ
Thermal Shutdown (TSD)
−273.15
Ǔ
0.6
R OTP2
R OTP2
OTP detection starts from the beginning of soft−start time
TSS, and ends in shutdown and idle time of hiccup mode.
* 273.15
1
ǒ
R OTP1
Ǔ
* 1 @ R T3
(eq. 15)
(eq. 16)
With OTP Configuration 2, as shown in Figure 12 (2), the
NCP81234 receives an external signal VT linearly
representing temperature and compares to an internal 0.6 V
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16
NCP81234
PGOOD1 / PGOOD2
FAULT
ALERT
Start
4
4
OC
1 1
Channel 1
Channel 2
Fault Flags
Fault Flags
OT
UV
OV
L
Interval
OV
H
2
OC
OT
4
36
Figure 13. Timing Diagram of FAULT Signal
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17
UV
OV
L
OV
H
End
4
NCP81234
LAYOUT GUIDELINES
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
• Power Paths: Use wide and short traces for power
paths (such as VIN, VOUT, SW, and PGND) in power
stages to reduce parasitic inductance and
high−frequency loop area. It is also good for efficiency
improvement.
• Power Supply Decoupling: The devices should be
well decoupled by input capacitors and input loop area
should be as small as possible to reduce parasitic
inductance, input voltage spike, and noise emission.
Usually, a small low−ESL MLCC is placed very close
to VIN and PGND pins.
• VCC Decoupling: Place decoupling caps as close as
possible to VCC5V pin of the NCP81234 and VCCP
pins of DrMOS.
• Switching Node: Each SW node in power stages
should be a copper pour, but compact because it is also
a noise source.
• Bootstrap: The bootstrap cap and an option resistor per
phase need to be very close and directly connected
between bootstrap pin and SW pin of DrMOS.
• Ground: It would be good to have separated ground
planes for power ground PGND and analog ground
GND and connect the two planes at one point.
• Voltage Sense: Use Kelvin sense pair and arrange a
“quiet” path for the differential output voltage sense.
Careful layout for multi−phase locations and output
capacitor distribution would help to get even voltage
•
•
ripple at the voltage sensing point, and have better
current balance as well.
Current Sense: Use Kelvin sense pair and arrange a
“quiet” path for the differential current sense per phase.
Careful layout for current sensing is critical for jitter
minimization, accurate current limiting, and good
current balance. The current−sense filter capacitors and
resistors should be close to the controller. The
temperature compensating thermistor should be placed
as close as possible to the inductor. The wiring path
should be kept as short as possible but well away from
the switch nodes.
Compensation Network: The small feedback
capacitor from COMP to FB should be as close to the
controller as possible. Keep the FB traces short to
minimize their capacitance to ground.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
• The exposed pads must be well soldered on the board.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More free vias are welcome to be around DrMOS and
underneath the exposed pads to connect the inner
ground layers to reduce thermal impedance.
• Use large area copper pour to help thermal conduction
and radiation.
• Do not put the inductor to be too close to the DrMOS,
thus the heat sources are decentralized.
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18
NCP81234
PACKAGE DIMENSIONS
QFN28 5x5, 0.5P
CASE 485BQ−01
ISSUE O
A
B
D
PIN ONE
INDICATOR
ÉÉ
ÉÉ
L
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
0.15 C
ÉÉ
ÇÇ
ÇÇ
EXPOSED Cu
0.15 C
TOP VIEW
DETAIL B
0.10 C
(A3)
SIDE VIEW
C
0.10
DETAIL A
M
A1
ALTERNATE
CONSTRUCTIONS
A1
NOTE 4
ÇÇ
ÉÉ
DETAIL B
A
0.08 C
A3
MOLD CMPD
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT
C A B
D2
8
0.10
M
5.30
C A B
28X
15
K
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
5.00 BSC
3.15
3.35
5.00 BSC
3.15
3.35
0.50 BSC
0.32 REF
0.45
0.65
0.05
0.15
0.77
3.40
E2
1
1
28
L
22
28X
e
BOTTOM VIEW
5.30
3.40
b
0.10
M
C A B
0.05
M
C
NOTE 3
0.50
PITCH
28X
0.32
DIMENSIONS: MILLIMETERS
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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19
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NCP81234/D