For Information Equipment MN89303A SVGA Display Controller Overview The MN89303A is an LCD/CRT display controller with IBM™ VGA-compatible registers. It features all the necessary interfaces for a compact display system: ISA bus interface, local bus interface, DRAM interface, and LCD panel interface. The built-in graphics acceleration functions include support for hardware cursor. Note: IBM™ and VGA are registered trademarks of International Business Machines Corporation. Features Monochrome STN LCD panel support Built-in graphics acceleration functions Maximum display size: 800 × 600 • Hardware cursor (16 × 16 or 32 × 32) Support for single and dual panels Built-in automatic display centering 16-monochrome gradation Built-in gradation control table (rewritable) for optimizing gradation to match panel Color STN LCD panel support Maximum display size: 800 × 600 DRAM interface with 16-bit bus Support for single and dual panels • Choice of DRAM access timing to match system performance (EDO/normal) 16-gradation for each color (RGB) Color TFT LCD panel support Maximum display size: 800 × 600 4-bit output for each color (RGB) Maximum number of colors in concurrent display 640 × 480: 256/4096 palette (TFT, STN) 800 × 600: 256/4096 palette (TFT, STN) • Support for 2CAS/2WE mode • Refresh control Host interfaces • ISA bus (16-bit) • i386/i486 local bus (16-bit) Note: i386 and i486 are trademarks of Intel Corporation. Applications Point-of-sale terminals, Factory automation terminals, word processors, and other terminals 325 MN89303A For Information Equipment 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 VDD VSS LOGICON LCDON BACKON LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 VDD VSS UD0 UD1 UD2 UD3 UD4 UD5 UD6 UD7 Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 XIN VSS AEN SBHE IOWR IORD SMEMW SMEMR A21 A20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 BIOSEN REFRESH MAO VSS VDD RAS UCAS LCAS WE MD15 MD14 MD13 MD12 MD11 MD10 VSS VDD MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 VSS VDD RESET MINTEST TEST VSS XOUT (TOP VIEW) QFH128-P-1818 Note: Never leave VDD and VSS pins open. FP LP DISP DCLK VDD VSS IOCS16 MEMCS16 IOCHRDY VDD VSS SD0 SD1 SD2 SD3 SD4 SD5 VSS SD6 SD7 SD8 VDD SD9 SD10 SD11 VSS SD12 SD13 SD14 SD15 VDD VSS For Information Equipment MN89303A Block Diagram Gray scale engine RAM table UD[7:0] Hardware cursor LD[7:0] BACKON LCDON LOGICON LP FO DISP DCLK 83 84 85 63 LCD panel controller Attribute control 64 62 61 1 XIN RESET TEST/MINTEST LCD/CRT controller 124 126/125 Memory interface Address[21:0] SD[15:0] AEN SBHE IOWR IORD SMEMW SMEMR IOCHRDY REFRESH MEMCS16 IOCS16 Video FIFO 3 4 Access attributer 5 6 7 8 56 32 57 58 Host interface Memory write buffer Graphics controller MA[9:0] MD[15:0] 100 RAS 101 UCAS 102 LCAS 103 WE 31 BIOSEN MN89303A For Information Equipment Pin Descriptions Pin No. 3 Symbol AEN I/O Level I TTL Function Description Address Enable "H" level input from this pin indicates that a DMA transfer is in progress, so the chip does not respond to I/O access. 4 SBHE I TTL Byte High Enable This input indicates the state of the 16-bit bus. 5 IOWR I TTL I/O Write This input indicates an I/O write request. 6 IORD I TTL I/O Read This input indicates an I/O read request. 7 SMEMW I TTL Memory Write This input indicates a memory write request dedicated for an address space in the first megabyte (000000 to 0FFFFFH). 8 SMEMR I TTL Memory Read This input indicates a memory read request dedicated for an address space in the first megabyte (000000 to 0FFFFFH). 9 to 10 A[21:20] I TTL Address[21:20] These inputs give the address 21:20. 11 to 30 SA[19:0] I TTL Address[19:0] These inputs give the address 19:0. 35 to 53 SD[15:0] I/O TTL Data[15:0] These pins represent the host data bus. 56 IOCHRDY I/O TTL I/O Channel Ready This pin is "L" level when I/O or memory access is given wait state. 57 MEMCS16 O TTL Memory Chip Select 16 This output indicates to the system that 16-bit memory access is available. 58 IOCS16 O TTL 32 REFRESH I TTL MA[9:0] O CMOS 100 RAS O CMOS 101 UCAS O CMOS I/O Chip Select 16 This output indicates to the system that 16-bit I/O access is available. Refresh "L" level input indicates that the system is refreshing its DRAM. 88 to 97 Memory Address These outputs give the address of the display memory. Row Address Strobe (RAS) This output is the strobe signal for the row address latch. Upper Column Address Strobe (UCAS) This output is the strobe signal for the upper column address latch. In the 2WE mode, however, it functions as the CAS signal. For Information Equipment MN89303A Pin Descriptions (continued) Pin No. 102 Symbol LCAS I/O Level O CMOS Function Description Lower Column Address Strobe (LCAS) This output is the strobe signal for the lower column address latch. In the 2WE mode, however, it functions as the LWE signal. 103 WE O CMOS Write Enable This output is the data write signal. In the 2WE mode, however, it functions as the UWE signal. 104 to 121 MD[15:0] I/O TTL Memory Data These pins represent the data bus to the DRAM. 31 BIOSEN O CMOS 83 BACKON O CMOS BIOS Enable This output enables ROM BIOS output. Backlight ON This output requests backlighting. "L" level: OFF; "H" level: ON 84 LCDON O CMOS LCD Drive ON This output requests power-ON for the LCD panel. "L" level: OFF; "H" level: ON 85 LOGICON O CMOS LCD Logic ON This output requests power-ON for LCD panel logic circuits. "L" level: OFF; "H" level: ON 63 LP O CMOS Line Pulse This output provides pulses indicating the end of a line of the LCD panel. 64 FP O CMOS Frame Pulse This output provides pulses indicating the start of a frame of the LCD panel. 62 DISP O CMOS Display Enable This output enables the LCD display. An external RAMDAC uses this signal as a blanking signal. A TFT LCD uses it as an enable signal. 61 DCLK O CMOS Data Shift Clock This pin provides a data shift clock signal for an STN LCD panel. It also outputs a dot clock signal on a TFT LCD panel or external RAMDAC display mode. 65 to 72 UD[7:0] O CMOS Upper Data[7:0] 75 to 82 LD[7:0] O CMOS Lower Data[7:0] This pins provide display data. Usage varies with the LCD panel type. MN89303A For Information Equipment Pin Descriptions (continued) Pin No. 124 Symbol RESET I/O Level I TTL Function Description Reset "H" level input from this pin initializes the chip. If the host is in a i386 mode, the chip aligns the clock phase with this signal. 96 to 97 MA[1:0] I CMOS Host Type During a reset, these pins select the host type. MA[1:0] 126/125 TEST/ CMOS MINTEST 1/128 XIN/ Host Type 0 0 ISA 0 1 386SX 1 0 386DX 1 1 486 Chip Test Condition This pin selects the chip test mode. I/O XOUT Clock IN/OUT These pins are the clock I/O pins. Connect them to a crystal oscillator. Absolute Maximum Ratings Parameter Symbol Ratings Unit VDD – 0.3 to +7.0 V Input pin voltage VI – 0.3 to V DD+0.3 V Output pin voltage VO – 0.3 to V DD+0.3 V Power supply voltage Power dissipaiton PD 1000 mW Operating ambient temperature T opr 0 to +70 ˚C Storage temperature Tstg – 55 to +150 ˚C Recommended Operating Conditions Parameter Symbol Conditions min typ max 5.00 Unit Power supply voltage VDD 4.75 5.25 V Ambient temperature Ta 0 70 ˚C Rise time for input tr 0 150 ns Fall time for input tf 0 150 ns Oscillation frequency f OSC At self-excited operation 25 33 MHz Operating frequency fopr1 At self-excited operation 25 33 MHz Operating frequency fopr2 Using external input 0 33 MHz For Information Equipment MN89303A Electrical Characteristics VDD =4.75 to 5.25V, VSS=0.00V, f=33MHz, Ta=0 to 70˚C Parameter Power supply current Symbol Conditions max Unit IDD0 VI=VDD or VSS ,V DD=5.0V min typ 120 mA IDD1 VI=VDD or VSS ,V DD=5.0V 15 mA IDD2 VI=VDD or VSS ,V DD=5.0V 40 mA during operation Power supply current in the SUSPEND mode Power supply current in the STANDBY mode "H" level input voltage 1 VIH1 2.0 VDD V VIH2 VDD × 0.7 VDD V VIL1 0 0.8 V VIL2 0 VDD × 0.3 V TEST ,AEN ,SBHE , IOWR ,IORD ,SMEMW , SMEMR ,REFRESH , A21 to 20 ,SA19 to 0 , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY "H" level input voltage 2 MINTEST ,RAS ,UCAS , LCAS ,BACKON , LCDON ,LOGICON , MA9 to 0 "L" level input voltage 1 TEST ,AEN ,SBHE , IOWR ,IORD ,SMEMW , SMEMR ,REFRESH , A21 to 20 ,SA19 to 0 , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY "L" level input voltage 2 MINTESTRAS UCAS , LCAS ,BACKON , LCDON ,LOGICON , MA9 to 0 ILI1 VI=VDD or VSS ±20 µA ILI2 VI=VDD or VSS ±10 µA RPD1 VI=VDD ,VDD =5.0V 75 kΩ Input threshold voltage VtHL VDD=4.75 to 5.25V RESET VtLH Input leakage current 1 TEST ,MINTEST Input leakage current 2 AEN ,SBHE ,IOWR , IORD ,SMEMW , SMEMR ,REFRESH , A21 to 20 ,SA19 to 0 , RESET Pull-down resistance 12 30 1.0 1.8 V MN89303A For Information Equipment Electrical Characteristics (continued) VDD =4.75 to 5.25V, VSS =0.00V, f=33MHz, Ta=0 to 70˚C Parameter Symbol "H" level output voltage 1 VOH1 Conditions IO=–2.0mA min typ max Unit VDD– 0.6 V VDD– 0.6 V VDD– 0.6 V VDD– 0.6 V VI=V DD or VSS BACKON ,LCDON , LOGICON ,SD15 to 0 , MD15 to 0 ,BIOSEN "H" level output voltage 2 VOH2 IO=–8.0mA VI=V DD or VSS DCLK ,DISP ,LP ,FP , UD7 to 0 ,LD7 to 0 , WE ,MA9 to 0 ,RAS , UCAS ,LCAS "H" level output voltage 3 VOH3 IOCHRDY "H" level output voltage 4 VI=V DD or VSS VOH4 IOCS16 ,MEMCS16 "L" level output voltage 1 IO=–12.0mA IO=–16.0mA VI=V DD or VSS V OL1 IO=2.0mA 0.4 V 0.4 V 0.4 V 0.4 V 0.4 V ±10 µA VI=V DD or VSS BACKON ,LCDON , LOGICON "L" level output voltage 2 V OL2 IO=4.0mA VI=V DD or VSS SD15 to 0 ,MD15 to 0 , BIOSEN "L" level output voltage 3 V OL3 IO=0.8mA VI=V DD or VSS DCLK ,DISP ,LP ,FP , UD7 to 0 ,LD7 to 0 , WE ,MA9 to 0 ,RAS , UCAS ,LCAS "L" level output voltage 4 V OL4 IO=12.0mA V OL5 IO=16.0mA IOCHRDY "L" level output voltage 5 VI=V DD or VSS IOCS16 ,MEMCS16 Output leakage current VI=V DD or VSS ILO VO=High-impedance state IOCS16 ,BACKON , VI=V DD or VSS MA9 to 0 ,MEMCS16 , VO=VDD or VSS UCAS ,LCAS ,RAS , LOGICON ,LCDON , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY For Information Equipment MN89303A Timing Chart for LCD Panel Outputs FP LP DCLK LD7/UD7 R1 B3 G638 R1 B3 G6 LD6/UD6 G1 R4 B638 G1 R4 B6 LD5/UD5 B1 G4 R639 B1 G4 R7 LD4/UD4 R2 B4 G639 R2 B4 G7 LD3/UD3 G2 R5 B639 G2 R5 B7 LD2/UD2 B2 G5 R640 B2 G5 R8 LD1/UD1 R3 B5 G640 R3 B5 G8 LD0/UD0 G3 R6 B640 G3 R6 B8 FP LP UD 240 lines 1 line 2 lines 3 lines 4 lines 5 lines LD 480 lines 241 lines 242 lines 243 lines 244 lines 245 lines 1 1 line 2 lines · · · · · 2 3 R1 G1 B1 R2 G2 B2 R3 G3 B3 UD7 UD6 UD5 UD4 UD3 UD2 UD1 UD0 UD7 640 R640 G640 B640 UD2 UD1 UD0 First byte of data Upper screen 240 lines 241 lines 242 lines · · · · · · · 480 lines R1 G1 B1 R2 G2 B2 R3 G3 B3 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 LD7 First byte of data Lower screen R640 G640 B640 LD2 LD1 LD0 MN89303A For Information Equipment Application Circuit Example BIOS CE (20) XOUT XIN Address[21:0] BIOSEN RESET UD[7:0] SD[15:0] LD[7:0] AEN SBHE BACKON IOWR LCDON LCD IORD MN89303A SMEMW LOGICON panel SMEMR LP REFRESH FP IOCHRDY 4MDRAM ISA bus MA[9:0] RAS UCAS LCAS WE BIOSEN IOCS16 MD[15:0] DISP MEMCS16 DCLK For Information Equipment MN89303A Package Dimensions (Unit: mm) QFH128-P-1818 20.0±0.2 18.0±0.2 96 65 64 18.0±0.2 20.0±0.2 (1.25) 97 0.1 SEATING PLANE 0 to 10° 1.0±0.2 +0.10 32 0.2±0.1 0.15–0.05 0.5 3.4±0.3 1 3.3±0.2 (1.25) 33 0.1±0.1 128 0.5±0.2