0.8 GHz to 2.5 GHz Quadrature Modulator AD8346 High accuracy 1 degree rms quadrature error @ 1.9 GHz 0.2 dB I/Q amplitude balance @ 1.9 GHz Broad frequency range: 0.8 GHz to 2.5 GHz Sideband suppression: −46 dBc @ 0.8 GHz Sideband suppression: −36 dBc @ 1.9 GHz Modulation bandwidth: dc to 70 MHz 0 dBm output compression level @ 0.8 GHz Noise floor: −147 dBm/Hz Single 2.7 V to 5.5 V supply Quiescent operating current: 45 mA Standby current: 1 μA 16-lead TSSOP FUNCTIONAL BLOCK DIAGRAM IBBP 1 16 QBBP IBBN 2 15 QBBN COM1 3 14 COM4 COM1 4 13 COM4 LOIN 5 12 VPS2 LOIP 6 VPS1 7 PHASE SPLITTER 11 VOUT 10 COM3 AD8346 ENBL 8 BIAS 9 COM2 05335-001 FEATURES Figure 1. APPLICATIONS Digital and spread spectrum communication systems Cellular/PCS/ISM transceivers Wireless LAN/wireless local loop QPSK/GMSK/QAM modulators Single-sideband (SSB) modulators Frequency synthesizers Image reject mixer GENERAL DESCRIPTION The AD8346 is a silicon RFIC I/Q modulator for use from 0.8 GHz to 2.5 GHz. Its excellent phase accuracy and amplitude balance allow high performance direct modulation to RF. The differential LO input is applied to a polyphase network phase splitter that provides accurate phase quadrature from 0.8 GHz to 2.5 GHz. Buffer amplifiers are inserted between two sections of the phase splitter to improve the signal-tonoise ratio. The I and Q outputs of the phase splitter drive the LO inputs of two Gilbert-cell mixers. Two differential V-to-I converters connected to the baseband inputs provide the baseband modulation signals for the mixers. The outputs of the two mixers are summed together at an amplifier which is designed to drive a 50 Ω load. This quadrature modulator can be used as the transmit modulator in digital systems such as PCS, DCS, GSM, CDMA, and ISM transceivers. The baseband quadrature inputs are directly modulated by the LO signal to produce various QPSK and QAM formats at the RF output. Additionally, this quadrature modulator can be used with direct digital synthesizers in hybrid phase-locked loops to generate signals over a wide frequency range with millihertz resolution. The AD8346 comes in a 16-lead TSSOP package, measuring 6.5 mm × 5.1 mm × 1.1 mm. It is specified to operate over a −40°C to +85°C temperature range and a 2.7 V to 5.5 V supply voltage range. The device is fabricated on Analog Devices’ high performance 25 GHz bipolar silicon process. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD8346 TABLE OF CONTENTS Specifications..................................................................................... 3 Bias ............................................................................................... 10 Absolute Maximum Ratings............................................................ 4 Basic Connections...................................................................... 11 ESD Caution.................................................................................. 4 LO Drive ...................................................................................... 11 Pin Configuration and Function Descriptions............................. 5 RF Output.................................................................................... 11 Equivalent Circuits ........................................................................... 6 Interface to AD9761 TXDAC® .................................................. 12 Typical Performance Characteristics ............................................. 7 AC-Coupled Interface ............................................................... 13 Circuit Description......................................................................... 10 Evaluation Board ............................................................................ 14 Overview...................................................................................... 10 Characterization Setups................................................................. 16 LO Interface................................................................................. 10 SSB Setup..................................................................................... 16 V-to-I Converter......................................................................... 10 CDMA Setup............................................................................... 17 Mixers .......................................................................................... 10 Outline Dimensions ....................................................................... 18 Differential-to-Single-Ended Converter ................................. 10 Ordering Guide .......................................................................... 18 REVISION HISTORY 6/05—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Figures 30, 31, 32........................................................ 14 Update Outline Dimensions ......................................................... 18 Changes to Ordering Guide .......................................................... 18 3/99—Revision 0: Initial Version Rev. A | Page 2 of 20 AD8346 SPECIFICATIONS VS = 5 V; TA = 25°C; LO frequency = 1900 MHz; LO level = –10 dBm; BB frequency = 100 kHz; BB inputs are dc-biased to 1.2 V; BB input level = 1.0 V p-p each pin for 2.0 V p-p differential drive; LO source and RF output load impedances are 50 Ω, dBm units are referenced to 50 Ω unless otherwise noted. Table 1. Parameters RF OUTPUT Operating Frequency Quadrature Phase Error I/Q Amplitude Balance Output Power Output VSWR Output P1 dB Carrier Feedthrough Sideband Suppression IM3 Suppression Equivalent Output IP3 Output Noise Floor RESPONSE TO CDMA IS95 BASEBAND SIGNALS ACPR (Adjacent Channel Power Ratio) EVM (Error Vector Magnitude) Rho (Waveform Quality Factor) MODULATION INPUT Input Resistance Modulation Bandwidth LO INPUT LO Drive Level Input VSWR ENABLE ENBL HI Threshold ENBL LO Threshold ENBL Turn-On Time ENBL Turn-Off Time Conditions Min Typ 0.8 See Figure 35 for setup See Figure 35 for setup I and Q channels in quadrature Max Unit 2.5 GHz Degree rms dB dBm 20 MHz offset from LO 1 0.2 −10 1.25:1 −3 −42 −36 −60 20 −147 See Figure 35 for setup See Figure 35 for setup See Figure 35 for setup −72 2.5 0.9974 dBc % −3 dB 12 70 kΩ MHz −13 −12 −6 −35 −25 dBm dBm dBc dBc dBm dBm/Hz −6 dBm 2.0 2.5 V V μs 12 μs 1.9:1 0.5 Settle to within 0.5 dB of final SSB output power Time for supply current to drop below 2 mA POWER SUPPLIES Voltage Current Active (ENBL HI) Current Standby (ENBL LO) 2.7 35 Rev. A | Page 3 of 20 45 1 5.5 55 20 V mA μA AD8346 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPS1, VPS2 Input Power LOIP, LOIN (relative to 50 Ω) Min Input Voltage IBBP, IBBN, QBBP, QBBN Max Input Voltage IBBP, IBBN, QBBP, QBBN Internal Power Dissipation θJA Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Min Rating 5.5 V 10 dBm 0V 2.5 V 500 mW 125°C/W −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 4 of 20 AD8346 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IBBP 1 16 QBBP IBBN 2 15 QBBN COM1 3 14 COM4 AD8346 13 COM4 TOP VIEW LOIN 5 (Not to Scale) 12 VPS2 LOIP 6 11 VOUT VPS1 7 10 COM3 ENBL 8 9 COM2 05335-002 COM1 4 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic IBBP 2 IBBN 3 4 5 COM1 COM1 LOIN 6 LOIP 7 VPS1 8 9 10 11 12 ENBL COM2 COM3 VOUT VPS2 13 14 15 COM4 COM4 QBBN 16 QBBP Description I Channel Baseband Positive Input Pin. Input should be dc-biased to approximately 1.2 V. Nominal characterized ac swing is 1 V p-p (0.7 V to 1.7 V). This makes the differential input 2 V p-p when IBBN is 180 degrees out of phase from IBBP. I Channel Baseband Negative Input Pin. Input should be dc-biased to approximately 1.2 V. Nominal characterized ac swing is 1 V p-p (0.7 V to 1.7 V). This makes the differential input 2 V p-p when IBBN is 180 degrees out of phase from IBBP. Ground Pin for the LO phase splitter and LO buffers. Ground Pin for the LO phase splitter and LO buffers. LO Negative Input Pin. Internal dc bias (approximately VPS1 to 800 mV) is supplied. This pin must be ac coupled. LO Positive Input Pin. Internal dc bias (approximately VPS1 to 800 mV) is supplied. This pin must be ac-coupled. Power Supply Pin for the bias cell and LO buffers. This pin should be decoupled using local 100 pF and 0.01 μF capacitors. Enable Pin. A high level enables the device; a low level puts the device in sleep mode. Ground Pin for the input stage of output amplifier. Ground Pin for the output stage of output amplifier. 50 Ω DC-Coupled RF Output. User must provide ac coupling on this pin. Power Supply Pin for baseband input voltage to current converters and mixer core. This pin should be decoupled using local 100 pF and 0.01 μF capacitors. Ground Pin for baseband input voltage to current converters and mixer core. Ground Pin for baseband input voltage to current converters and mixer core. Q Channel Baseband Negative Input. Input should be dc biased to approximately 1.2 V. Nominal characterized ac swing is 1 V p-p. This makes the differential input 2 V p-p when QBBN is 180° out of phase from QBBP. Q Channel Baseband Positive Input. Input should be dc-biased to approximately 1.2 V. Nominal characterized ac swing is 1 V p-p. This makes the differential input 2 V p-p when QBBN is 180° out of phase from QBBP. Rev. A | Page 5 of 20 Equivalent Circuit Circuit A Circuit A Circuit B Circuit B Circuit C Circuit D Circuit A Circuit A AD8346 EQUIVALENT CIRCUITS VPS1 VPS2 TO MIXER CORE 75kΩ TO BIAS FOR STARTUP/ SHUTDOWN 75kΩ 9kΩ INPUT 30kΩ ENBL 05335-003 3kΩ ACTIVE LOADS 40kΩ 780Ω Figure 5. Circuit C Figure 3. Circuit A VPS2 VPS1 LOIN PHASE SPLITTER CONTINUES 43Ω 05335-004 43Ω Figure 4. Circuit B Figure 6. Circuit D Rev. A | Page 6 of 20 05335-006 VOUT LOIP 05335-005 BUFFER AD8346 TYPICAL PERFORMANCE CHARACTERISTICS 2 –6 T = 25°C 1 OUTPUT POWER VARIATION (dB) VP = 5.5V –8 –9 –10 VP = 3V –11 VP = 2.7V –12 –13 –15 800 05335-007 –14 1000 1200 1400 1600 1800 2000 LO FREQUENCY (MHz) 2200 –4 –5 –6 –7 1 2 LO = 800MHz, –6dBm VP = 5V T = +85°C 0 VP = 5V T = –40°C LO = 800MHz, –10dBm –8 LO = 1900MHz, –6dBm –9 –10 LO = 1900MHz, –10dBm –11 100 10 Figure 10. I and Q Input Bandwidth. FLO =1900 MHz, I or Q inputs driven with differential amplitude of 2.00 V p-p. SSB OUTPUT P1dB (dBm) –12 –2 –4 VP = 2.7V T = –40°C –6 –8 VP = 2.7V T = +85°C –10 –13 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 05335-008 –12 –14 800 Figure 8. SSB POUT vs. Temperature. I and Q inputs driven in quadrature with differential amplitude of 2.00 V p-p at FBB = 100 kHz. 05335-011 SSB OUTPUT POWER (dBm) –3 BASEBAND FREQUENCY (MHz) –7 1000 1200 1400 1600 1800 2000 LO FREQUENCY (MHz) 2200 2400 Figure 11. SSB Output 1 dB Compression Point (OP 1 dB) vs. FLO. I and Q inputs driven in quadrature at FBB = 100 kHz. 30 –35 T = +85°C T = –40°C –37 25 VP = 5.5V –39 PERCENTAGE 20 –41 VP = 5V –43 VP = 3V –45 –47 15 10 VP = 2.7V 5 –49 –51 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 05335-009 CARRIER FEEDTHROUGH (dBm) –2 –8 0.1 2400 Figure 7. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (FLO). I and Q inputs driven in quadrature at baseband frequency (FBB) = 100 kHz with differential amplitude of 2.00 V p-p. –6 0 –1 0 –90 Figure 9. Carrier Feedthrough vs. Temperature. FLO = 1900 MHz, LO input level = –10 dBm. 05335-012 SSB POWER (dBm) VP = 5V 05335-010 –7 –86 –82 –78 –74 –70 –66 –62 –58 –54 CARRIER FEEDTHROUGH (dBm/ AFTER NULLING TO <–60dBm @ 25°C) –50 –46 Figure 12. Histogram Showing Carrier Feedthrough Distributions at the Temperature Extremes after Nulling at Ambient at FLO = 1900 MHz, LO Input Level = –10 dBm. Rev. A | Page 7 of 20 AD8346 –7 –30 –8 –32 VP = 5.5V SB SUPPRESSION (dBc) VP = 3V VP = 5V –11 –12 VP = 2.7V –13 –15 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 2 4 6 8 10 12 14 16 BASEBAND FREQUENCY (MHz) 18 20 Figure 16. Sideband Suppression vs. FBB. FLO = 1900 MHz, I and Q inputs driven in quadrature with differential amplitude of 2.00 V p-p. –40 VP = 3V –42 –44 VP = 5V –46 VP = 2.7V –48 –50 1200 1400 1600 1800 2000 LO FREQUENCY (MHz) 2200 VP = 5V VP = 2.7V –50 VP = 3V –55 –60 –65 05335-014 –54 –45 VP = 5.5V –70 –40 –30 –20 –10 2400 0 05335-017 –40 INPUT THIRD HARMONIC DISTORTION (dBc) CARRIER FEEDTHROUGH (dBm) VP = 2.7V –40 0 VP = 5.5V –52 10 20 30 40 TEMPERATURE (°C) 50 60 70 80 Figure 17. Third Harmonic Distortion vs. Temperature. FLO =1900 MHz, I and Q inputs driven in quadrature with differential amplitude of 2.00 V p-p at FBB = 100 kHz. Figure 14. Carrier Feedthrough vs. FLO. LO input level = –10 dBm. 0 –32 T = 25°C VP = 5.5V –2 –34 –4 –36 VP = 5V RETURN LOSS (dB) SIDEBAND SUPPRESSION (dBc) VP = 5V –35 –38 1000 –38 –44 T = 25°C 800 VP = 5.5V –36 80 Figure 13. SSB POUT vs. Temperature. FLO = 1900 MHz, I and Q inputs driven in quadrature with differential amplitude of 2.00 V p-p at FBB = 100 kHz. –36 VP = 3V –42 05335-013 –14 –34 05335-016 –10 –38 –40 VP = 3V –42 –6 T = +25°C T = –40°C –8 –10 T = +85°C –12 –14 –44 –16 VP = 2.7V 05335-015 –46 –48 900 1100 1300 1500 1700 1900 LO FREQUENCY (MHz) 2100 2300 05335-018 SSB OUTPUT POWER (dBm) –9 –18 –20 800 2500 Figure 15. Sideband Suppression vs. FLO. VPOS = 2.7 V, I and Q inputs driven in quadrature with differential amplitude of 2.00 V p-p at FBB = 100 kHz. Rev. A | Page 8 of 20 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 2200 Figure 18. Return Loss of LOIN Input vs. FLO. VPOS = 5.0 V, LOIP pin ac-coupled to ground. 2400 AD8346 –30 –40 VP = 2.7V –32 –45 VP = 5.5V VP = 2.7V VP = 5V –38 –40 VP = 3V –50 VP = 5.5V –55 VP = 5V –60 –44 –40 –30 –20 –10 05335-019 –42 0 10 20 30 40 TEMPERATURE (°C) 50 60 70 –65 80 0 –35 SSB POUT 2 4 6 8 10 12 14 16 BASEBAND FREQUENCY (MHz) 18 20 Figure 22. Third Harmonic Distortion vs. FBB. FLO =1900 MHz, I and Q inputs driven in quadrature with differential amplitude of 2.00 V p-p. Figure 19. Sideband Suppression vs. Temperature. FLO = 1900 MHz, I and Q inputs driven in quadrature with differential amplitude of 2.00 V p-p at FBB = 100 kHz. –30 05335-022 SB SUPPRESSION (dBc) –36 INPUT THIRD HARMONIC DISTORTION (dB)c VP = 3V –34 –6 52 –8 50 –10 48 –60 –16 –65 –18 3RD HARMONIC –70 –22 1.0 1.5 2.0 2.5 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) 3.0 42 VP = 3V 40 38 36 –40 0 0 –5 –5 –10 20 40 TEMPERATURE (°C) 60 80 RETURN LOSS (dB) –10 T = –40°C –15 –20 –25 T = +25°C –20 –25 T = +25°C –30 –35 –35 T = +85°C 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) 2200 –40 800 2400 T = –40°C –15 –30 05335-021 RETURN LOSS (dB) 0 Figure 23. Power Supply Current vs. Temperature Figure 20. Third Harmonic Distortion and SSB Output Power vs. Baseband Differential Input Voltage Level. FLO = 1900 MHz, I and Q inputs driven in quadrature at FBB = 100 kHz. –40 800 –20 T = +85°C 05335-024 –80 0.5 VP = 5V 44 VP = 2.7V –20 –75 VP = 5.5V 46 05335-023 –14 –55 SUPPLY CURRENT (mA) –12 –50 SSB OUTPUT POWER (dBm) –45 05335-020 INPUT THIRD HARMONIC DISTORTION (dBc) –40 1000 1200 1400 1600 1800 2000 2200 FREQUENCY (MHz) Figure 24. Return Loss of VOUT Output vs. FLO. VPOS = 5.0 V. Figure 21. Return Loss of VOUT Output vs. FLO. VPOS = 2.7 V. Rev. A | Page 9 of 20 2400 AD8346 CIRCUIT DESCRIPTION OVERVIEW V-TO-I CONVERTER The AD8346 can be divided into the following sections: local oscillator (LO) interface, mixer, voltage-to-current (V-to-I) converter, differential-to-single-ended (D-to-S) converter, and bias. A detailed block diagram of the part is shown in Figure 25. Each baseband input pin is connected to an op amp driving an emitter follower. Feedback at the emitter maintains a current proportional to the input voltage through the transistor. This current is fed to the two mixers in differential form. The LO interface generates two LO signals, with 90° of phase difference between them, to drive two mixers in quadrature. Baseband voltage signals are converted into current form in the V-to-I converters, feeding into two mixers. The output of the mixers are combined to feed the D-to-S converter which provides the 50 Ω output interface. Bias currents to each section are controlled by the Enable (ENBL) signal. Detailed descriptions of each section follows. MIXERS There are two double-balanced mixers, one for the in-phase channel (I-channel) and one for the quadrature channel (Q channel). Each mixer uses the gilbert cell design with four cross-connected transistors. The bases of the transistors are driven by the LO signal of the corresponding channel. The output currents from the two mixers are summed together in two resistors in series with two coupled on-chip inductors. The signal developed across the R-L loads is sent to the D-to-S stage. LO INTERFACE DIFFERENTIAL-TO-SINGLE-ENDED CONVERTER The differential LO inputs allow the user to drive the LO differentially in order to achieve maximum performance. The LO can be driven single-endedly but the LO feedthrough performance is degraded, especially towards the higher end of the frequency range. The LO interface consists of interleaved stages of polyphase network phase splitters and buffer amplifiers. The phase-splitter contains resistors and capacitors connected in a circular manner to split the LO signal into I and Q paths in precise quadrature with each other. The signal on each path goes through a buffer amplifier to make up for the loss and high frequency roll-off. The two signals then go through another polyphase network to enhance the quadrature accuracy. The broad operating frequency range of 0.8 GHz to 2.5 GHz is achieved by staggering the RC time constants in each stage of the phase-splitters. The outputs of the second phase-splitter are fed into the driver amplifiers for the mixers’ LO inputs. The differential-to-single-ended converter consists of two emitter followers driving a totem-pole output stage. Output impedance is established by the emitter resistors in the output transistors. The output of this stage is connected to the output (VOUT) pin. BIAS A band gap reference circuit based on the Δ-VBE principle generates the proportional-to-absolute-temperature (PTAT) currents used by the different sections as references. The band gap voltage is also used to generate a temperature-stable current in the V-to-I converters to produce a temperature-independent slew rate. When the band gap reference is disabled by pulling down the ENBL pin, all other sections are shut off accordingly. IBBP IBBN V-TO-I V-TO-I AD8346 MIXER LOIN LOIP PHASE SPLITTER 2 PHASE SPLITTER 1 D-TO-S VOUT MIXER BIAS CELL V-TO-I QBBP Figure 25. Detailed Block Diagram Rev. A | Page 10 of 20 05335-025 ENBL V-TO-I QBBN AD8346 BASIC CONNECTIONS The basic connections for operating the AD8346 are shown in Figure 27. A single power supply of between 2.7 V and 5.5 V is applied to pins VPS1 and VPS2. A pair of ESD protection diodes are connected internally between VPS1 and VPS2 so these must be tied to the same potential. Both pins should be individually decoupled using 100 pF and 0.01 μF capacitors, located as close as possible to the device. For normal operation, the enable pin, ENBL, must be pulled high. The turn-on threshold for ENBL is 2 V. To put the device in its power-down mode, ENBL must be pulled below 0.5 V. Pins COM1 to COM4 should all be tied to a low impedance ground plane. have a bias level about 800 mV below supply. An LO drive level of between −6 dBm and −12 dBm is required. For optimal performance, a drive level of −10 dBm is recommended, although a level of −6 dBm results in more stable temperature performance (see Figure 8). Higher levels degrade linearity while lower levels tend to increase the noise floor. 100pF LO LOIP 05335-026 AD8346 LOIN 100pF The I and Q ports should be driven differentially. This is convenient as most modern high speed DACs have differential outputs. For optimal performance, the drive signal should be a 2 V p-p (differential) signal with a bias level of 1.2 V, that is, each input swings from 0.7 V to 1.7 V. The I and Q inputs have input impedances of 12 kΩ. By dc coupling the DAC to the AD8346 and applying small offset voltages, the LO feedthrough can be reduced to well below its nominal value of −42 dBm (see Figure 12). The LO terminal can be driven single-ended, as shown in Figure 26 at the expense of slightly higher LO feedthrough. LOIN is ac coupled to ground using a capacitor and LOIP is driven through a coupling capacitor from a (single-ended) 50 Ω source (this scheme could also be reversed with LOIP being ac-coupled to ground). LO DRIVE RF OUTPUT The return loss of the LO port is shown in Figure 18. No additional matching circuitry is required to drive this port from a 50 Ω source. For maximum LO suppression at the output, a differential LO drive is recommended. In Figure 27, this is achieved using a balun (M/A-COM Part Number ETC1-1-13). The output of the balun is ac-coupled to the LO inputs which The RF output is designed to drive a 50 Ω load, but must be accoupled, as shown in Figure 27. If the I and Q inputs are driven in quadrature by 2 V p-p signals, the resulting output power is about −10 dBm (see Figure 7 for variations in output power over frequency). 2 IBBN C6 100pF 5 1 T1 2 ETC1-1-13 4 +VS QBBN 15 AD8346 IN LO QP QBBP 16 C4 0.01μF C7 100pF 3 C3 100pF QN 3 COM1 COM4 14 4 COM1 COM4 13 5 LOIN VPS2 12 6 LOIP VOUT 11 7 VPS1 COM3 10 8 ENBL COM2 9 Figure 27. Basic Connections Rev. A | Page 11 of 20 C1 100pF C2 0.01μF +VS VOUT C5 100pF 05335-027 1 IBBP IP Figure 26. Single-Ended LO Drive AD8346 INTERFACE TO AD9761 TXDAC® Figure 28 shows a dc-coupled current output DAC interface. The use of dual-integrated DACs, such as the AD9761 with specified ±0.02 dB and ±0.004 dB gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain. The use of a precision thin-film resistor network sets the bias levels precisely to prevent the introduction of offset errors, which increase LO feedthrough. For instance, selecting resistor networks with a 0.1% ratio matching characteristics maintains 0.03 dB gain and offset matching performance. 10 mA, giving a voltage swing of 0 V to 1 V (at the DAC output). This results in a 0.5 V p-p swing at the I and Q inputs of the AD8346 (resulting in a 1 V p-p differential swing). Note that the ratio matching characteristics of the resistive network, as opposed to its absolute accuracy, is critical in preserving the gain and offset balance between the I and Q signal path. By applying small dc offsets to the I and Q signals from the DAC, the LO suppression can be reduced from its nominal value of −42 dBm to as low as −60 dBm while holding to approximately −50 dBm over temperature (see Figure 12 for a plot of LO feedthrough over temperature for an offset compensated circuit). Using resistive division, the dc bias level at the I and Q inputs to the AD8346 is set to approximately 1.2 V. Each of the four current outputs of the DAC delivers a full-scale current of 5V +5V DVDD 634Ω DCOM AVDD 500Ω 100Ω IOUTA LATCH I 2× I DAC 0.1μF VPS1 VPS2 IBBP CFILTER IOUTB 500Ω 100Ω DAC DATA INPUTS 500Ω 500Ω Σ IBBN VOUT AD9761 500Ω 100Ω QOUTA LATCH Q 2× Q DAC CLOCK 100Ω MUX CONTROL SLEEP FS ADJ RSET 2kΩ QBBP LOIN 500Ω 0.5V p-p EACH PIN WITH VCM = 1.2V QBBN AD8346 REFIO 05335-028 WRITE LOIP PHASE SPLITTER CFILTER QOUTB SELECT 500Ω 500Ω 0.1μF Figure 28. AD8346 Interface to AD9761 TxDAC Rev. A | Page 12 of 20 AD8346 AC-COUPLED INTERFACE An ac-coupled interface can also be implemented, as shown in Figure 29. This is an advantage because there is almost no voltage loss due to the biasing network, allowing the AD8346 inputs to be driven by the full 2 V p-p differential signal from the AD9761 (each of the DAC’s 4 outputs delivering 1 V p-p). The network shown has a high-pass corner frequency of approximately 14.3 kHz (note that the 12 kΩ input impedance of the AD8346 has been factored into this calculation). Increasing the resistors in the network or increasing the coupling capacitance reduces the corner frequency further. As in the dc-coupled case, the bias levels on the I and Q inputs should be set to as precise a level as possible, relative to each other. This prevents the introduction of additional input offset voltages. In Figure 29, the bias level on each input is set to approximately 1.2 V. The 2.43 kΩ resistors should have a ratio tolerance of 0.1% or better. Note that the LO suppression can be manually optimized by replacing a portion of the four top 2.43 kΩ resistors with potentiometers. In this case, the bottom four resistors in the biasing network no longer need to be precision devices. 5V 5V 1kΩ DVDD DCOM IOUTA LATCH I 2× 2.43kΩ 2.43kΩ AVDD I DAC IOUTB 100Ω 0.01μF CFILTER IBBP VPS1 VPS2 2.43kΩ 100Ω 0.01μF DAC DATA INPUTS 0.1μF Σ IBBN 2.43kΩ VOUT AD9761 LOIP QOUTA LATCH Q 2× Q DAC QOUTB 2.43kΩ FS ADJ RSET 2kΩ QBBP PHASE SPLITTER LOIN 2.43kΩ QBBN 0.01μF 2.43kΩ MUX CONTROL SLEEP 2.43kΩ AD8346 1V p-p EACH PIN WITH VCM = 1.2V REFIO 05335-029 CLOCK 0.01μF CFILTER 100Ω SELECT WRITE 100Ω 0.1μF Figure 29. AC-Coupled DAC Interface Rev. A | Page 13 of 20 AD8346 EVALUATION BOARD All connectors are of the SMA type. The I and Q inputs are provided with pads for implementing a simple RC filter network. The local oscillator input is driven through a balun (M/A-COM Part Number ETC1-1-13). The schematic of the AD8346 evaluation board is shown in Figure 30. This is a 4-layer FR4 board; the two center layers are used as ground planes and the top and bottom layers are used for signal and power. Figure 31 shows the layout and Figure 32 shows the silkscreen. The evaluation board circuit closely follows the basic connections circuit shown in Figure 27. Slide SW1 to the A position to connect the ENBL pin to +VS via the 10 kΩ pull-up resistor REP. Slide SW1 to the B position to disable the device by grounding the ENOP pin through the 49.9 Ω pull-down resistor REG. The device may be enabled via an external voltage applied to the SMA connector ENOP or TP2. CIP OPEN RIP IP 1 IBBP 0Ω 0Ω 5 CLON 100pF 1 CLOP 100pF T1 2 ETC1-1-13 RLOS OPEN 4 3 RLOP OPEN COM4 4 COM1 COM4 13 5 LOIN VPS2 12 14 6 LOIP VOUT 11 7 VPS1 COM3 10 8 ENBL COM2 TP2 ENOP +VS C1 0.01μF R7 0Ω QN 0Ω CQN OPEN RLON OPEN LO RQN QBBN 15 3 COM1 QP 0Ω RQS OPEN 2 IBBN CIN OPEN RQP QBBP 16 RIS OPEN RIN IN CQP OPEN AD8346 R2 C4 100pF 0Ω C3 0.01μF +VS CVO 100pF VOUT 9 C2 100pF REP 10kΩ A ENOP B REG 49.9kΩ Figure 30. Evaluation Board Schematic Rev. A | Page 14 of 20 05335-030 SW1 05335-031 AD8346 05335-032 Figure 31. Layout of Evaluation Board Figure 32. Silkscreen of Evaluation Board Rev. A | Page 15 of 20 AD8346 CHARACTERIZATION SETUPS SSB SETUP Two main setups were used to characterize this product. These setups are shown in Figure 33 and Figure 35. Figure 33 shows the setup used to evaluate the product as an SSB. The AD8346 motherboard had circuitry that converted the single-ended I and Q inputs from the arbitrary function generator to differential inputs with a dc bias of approximately 1.2 V. In addition, the motherboard also provided connections for power supply routing. The HP34970A and its associated plug-in 34901 were used to monitor power supply currents and voltages being supplied to the AD8346 evaluation board (a full schematic of IEEE the AD8346 evaluation board can be found in Figure 30). The two HP34907 plug-ins were used to provide additional miscellaneous dc and control signals to the motherboard. The LO was driven by an RF signal generator (through the balun on the evaluation board to present a differential LO signal to the device) and the output was measured with a spectrum analyzer. With the I channel driven with a sine wave and the Q channel driven with a cosine wave, the lower sideband is the single sideband output. The typical SSB output spectrum is shown in Figure 34. HP34970A D1 D2 D3 34901 34907 34907 D1 +15V MAX COM +25V MAX –25V MAX IEEE TEKAFG2020 D3 AD8346 I IN OUTPUT 1 Q IN OUTPUT 2 VN MOTHERBOARD GND VP HP3631 P1 IN HP8648C IEEE D2 VPS1 IN IP QP IP QP QN AD8346 QN HP8593E SWEEP OUT EVAL BOARD LO ENBL RFOUT IEEE ARB FUNC. GEN VOUT P1 RF I/P CAL OUT 28VOLT IEEE 05335-033 SPECTRUM ANALYZER IEEE PC CONTROLLER Figure 33. Evaluation Board SSB Test Setup 0 –10 –20 –30 –40 –50 –60 –70 05335-034 –80 –90 –100 CENTER 1.9GHz 50kHz/ SPAN 500kHz Figure 34. Typical SSB Output Spectrum Rev. A | Page 16 of 20 AD8346 CDMA SETUP For evaluating the AD8346 with CDMA waveforms, the setup shown in Figure 35 was used. This is essentially the same setup as that used for the single sideband characterization, except that the AFG2020 was replaced with the AWG2021 for providing the I and Q input signals, and the spectrum analyzer used to monitor the output was changed to an FSEA30 Rohde & Schwarz analyzer with vector demodulation capability. The I/Q input signals for these measurements were IS95 baseband signals generated with Tektronix I/Q SIM software and downloaded to the AWG2021. IEEE For measuring ACPR, the I/Q input signals used were generated with Pilot (Walsh Code 00), Sync (WC 32), Paging (WC 01), and 6 Traffic (WC 08, 09, 10, 11, 12, 13) channels active. The I/Q SIM software was set for 32× oversampling and was using a BS equifilter. Figure 36 shows the typical output spectrum for this configuration. The ACPR was measured 885 kHz away from the carrier frequency. For performing EVM, Rho, phase, and amplitude balance measurements, the I/Q input signals used were generated with only the pilot channel (Walsh Code 00) active. The I/Q SIM software was set for 32× oversampling using a CDMA equifilter. HP34970A D1 D2 D3 34901 34907 34907 D1 IEEE HP3631 AD8346 IN IEEE RFOUT TEKAFG2020 D3 I IN OUTPUT 1 Q IN OUTPUT 2 VN MOTHERBOARD GND VP P1 HP8648C D2 VPS1 IN IP QP IP QP QN AD8346 QN FSEA30 EVAL BOARD LO ENBL IEEE ARB FUNC. GEN VOUT P1 RF I/P IEEE SPECTRUM ANALYZER 05335-035 +15V MAX COM +25V MAX –25V MAX IEEE PC CONTROLLER Figure 35. Evaluation Board CDMA Test Setup –20 –30 –40 –50 –60 CH PWR = –20.7dBm ACP UPR = –71.8dBc ACP LWR = –71.7dBc –70 –80 –90 05335-036 –100 –110 –120 CENTER 1.9GHz 187.5kHz/ SPAN 1.875MHz Figure 36. Typical CDMA Output Spectrum Rev. A | Page 17 of 20 AD8346 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 37.16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model AD8346ARU AD8346ARU-REEL AD8346ARU-REEL7 AD8346ARUZ-REEL 1 AD8346ARUZ-REEL71 AD8346-EVAL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead (TSSOP) 13" Tape and Reel 16-Lead (TSSOP) 7" Tape and Reel 16-Lead (TSSOP) 13" Tape and Reel 16-Lead (TSSOP) 7" Tape and Reel Evaluation Board Z = Pb-free part. Rev. A | Page 18 of 20 Package Option RU-16 RU-16 RU-16 RU-16 RU-16 AD8346 NOTES Rev. A | Page 19 of 20 AD8346 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C05335–0–6/05(A) Rev. A | Page 20 of 20