3 nV/√Hz, Low Power Instrumentation Amplifier AD8421 Data Sheet Medical instrumentation Precision data acquisition Microphone preamplification Vibration analysis Multiplexed input applications ADC driver AD8421 –IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF +IN 4 5 –VS TOP VIEW (Not to Scale) Figure 1. 10µ G = 100 BEST AVAILABLE 7mA LOW NOISE IN-AMP 1µ 100n 10n BEST AVAILABLE 1mA LOW POWER IN-AMP AD8421 RS NOISE ONLY 1n 100 1k 10k 100k SOURCE RESISTANCE, RS (Ω) 1M 10123-078 APPLICATIONS PIN CONNECTION DIAGRAM TOTAL NOISE DENSITY AT 1kHz (V/√Hz) Low power 2.3 mA maximum supply current Low noise 3.2 nV/√Hz maximum input voltage noise at 1 kHz 200 fA/√Hz current noise at 1 kHz Excellent ac specifications 10 MHz bandwidth (G = 1) 2 MHz bandwidth (G = 100) 0.6 μs settling time to 0.001% (G = 10) 80 dB CMRR at 20 kHz (G = 1) 35 V/μs slew rate High precision dc performance (AD8421BRZ) 94 dB CMRR minimum (G = 1) 0.2 μV/°C maximum input offset voltage drift 1 ppm/°C maximum gain drift (G = 1) 500 pA maximum input bias current Inputs protected to 40 V from opposite supply ±2.5 V to ±18 V dual supply (5 V to 36 V single supply) Gain set with a single resistor (G = 1 to 10,000) 10123-001 FEATURES Figure 2. Noise Density vs. Source Resistance GENERAL DESCRIPTION The AD8421 is a low cost, low power, extremely low noise, ultralow bias current, high speed instrumentation amplifier that is ideally suited for a broad spectrum of signal conditioning and data acquisition applications. This product features extremely high CMRR, allowing it to extract low level signals in the presence of high frequency common-mode noise over a wide temperature range. The 10 MHz bandwidth, 35 V/μs slew rate, and 0.6 μs settling time to 0.001% (G = 10) allow the AD8421 to amplify high speed signals and excel in applications that require high channel count, multiplexed systems. Even at higher gains, the current feedback architecture maintains high performance; for example, at G = 100, the bandwidth is 2 MHz and the settling time is 0.8 μs. The AD8421 has excellent distortion performance, making it suitable for use in demanding applications such as vibration analysis. The AD8421 delivers 3 nV/√Hz input voltage noise and 200 fA/√Hz current noise with only 2 mA quiescent current, making it an ideal choice for measuring low level signals. For applications with high source impedance, the AD8421 employs innovative process technology and design techniques to provide noise performance that is limited only by the sensor. The AD8421 uses unique protection methods to ensure robust inputs while still maintaining very low noise. This protection allows input voltages up to 40 V from the opposite supply rail without damage to the part. A single resistor sets the gain from 1 to 10,000. The reference pin can be used to apply a precise offset to the output voltage. The AD8421 is specified from −40°C to +85°C and has typical performance curves to 125°C. It is available in 8-lead MSOP and SOIC packages. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. AD8421 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Gain Selection............................................................................. 20 Applications....................................................................................... 1 Reference Terminal .................................................................... 21 Pin Connection Diagram ................................................................ 1 Input Voltage Range................................................................... 21 General Description ......................................................................... 1 Layout .......................................................................................... 21 Revision History ............................................................................... 2 Input Bias Current Return Path ............................................... 22 Specifications..................................................................................... 3 Input Voltages Beyond the Supply Rails.................................. 22 AR and BR Grades........................................................................ 3 Radio Frequency Interference (RFI)........................................ 23 ARM and BRM Grades................................................................ 5 Calculating the Noise of the Input Stage................................. 23 Absolute Maximum Ratings............................................................ 8 Applications Information .............................................................. 25 Thermal Resistance ...................................................................... 8 Differential Output Configuration .......................................... 25 ESD Caution.................................................................................. 8 Driving an ADC ......................................................................... 26 Pin Configuration and Function Descriptions............................. 9 Outline Dimensions ....................................................................... 27 Typical Performance Characteristics ........................................... 10 Ordering Guide .......................................................................... 27 Theory of Operation ...................................................................... 20 Architecture................................................................................. 20 REVISION HISTORY 5/12—Revision 0: Initial Version Rev. 0 | Page 2 of 28 Data Sheet AD8421 SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. AR AND BR GRADES Table 1. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 Over Temperature, G = 1 CMRR at 20 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz 1 Input Voltage Noise, eni Output Voltage Noise, eno Peak to Peak, RTI G=1 G = 10 G = 100 to 1000 Current Noise Spectral Density Peak to Peak, RTI VOLTAGE OFFSET 2 Input Offset Voltage, VOSI Over Temperature Average TC Output Offset Voltage, VOSO Over Temperature Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC Test Conditions/ Comments Min AR Grade Typ Max Min BR Grade Typ Max Unit VCM = −10 V to +10 V T = −40°C to +85°C VCM = −10 V to +10 V 86 106 126 136 80 94 114 134 140 93 dB dB dB dB dB 80 90 100 110 80 100 110 120 dB dB dB dB VIN+, VIN− = 0 V 3 3.2 60 3 3.2 60 nV/√Hz nV/√Hz 2 0.5 0.07 2 0.5 0.07 2.2 μV p-p μV p-p μV p-p 200 18 200 18 f = 0.1 Hz to 10 Hz f = 1 kHz f = 0.1 Hz to 10 Hz VS = ±5 V to ±15 V TA = −40°C to +85°C 60 86 0.4 350 0.66 6 TA = −40°C to +85°C 0.09 fA/√Hz pA p-p 25 45 0.2 250 0.45 5 μV μV μV/°C μV mV μV/°C VS = ±2.5 V to ±18 V 90 110 124 130 120 120 130 140 1 TA = −40°C to +85°C 50 0.5 TA = −40°C to +85°C 1 Rev. 0 | Page 3 of 28 100 120 140 140 2 8 2 2.2 120 140 150 150 0.1 50 0.1 1 dB dB dB dB 0.5 6 0.5 0.8 nA nA pA/°C nA nA pA/°C AD8421 Parameter DYNAMIC RESPONSE Small Signal Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time to 0.01% G=1 G = 10 G = 100 G = 1000 Settling Time to 0.001% G=1 G = 10 G = 100 G = 1000 Slew Rate G = 1 to 100 GAIN 3 Gain Range Gain Error G=1 G = 10 to 1000 Gain Nonlinearity G=1 G = 10 to 1000 Gain vs. Temperature3 G=1 G>1 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range 4 Over Temperature OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Data Sheet Test Conditions/ Comments Min AR Grade Typ Max Min BR Grade Typ Max Unit −3 dB 10 10 2 0.2 10 10 2 0.2 MHz MHz MHz MHz 0.7 0.4 0.6 5 0.7 0.4 0.6 5 μs μs μs μs 1 0.6 0.8 6 1 0.6 0.8 6 μs μs μs μs 35 35 V/μs 10 V step 10 V step G = 1 + (9.9 kΩ/RG) 1 10,000 1 10,000 V/V 0.01 0.1 % % 1 3 50 10 ppm ppm ppm ppm 1 −50 ppm/°C ppm/°C GΩ||pF GΩ||pF V V V VOUT = ±10 V 0.02 0.2 VOUT = −10 V to +10 V RL ≥ 2 kΩ RL = 600 Ω RL ≥ 600 Ω VOUT = −5 V to +5 V 1 30 5 1 3 50 10 1 30 5 5 −50 0.1 30||3 30||3 VS = ±2.5 V to ±18 V TA = −40°C TA = +85°C RL = 2 kΩ VS = ±2.5 V to ±18 V TA = −40°C to +85°C 30||3 30||3 −VS + 2.3 −VS + 2.5 −VS + 2.1 +VS − 1.8 +VS − 2.0 +VS − 1.8 −VS + 2.3 −VS + 2.5 −VS + 2.1 +VS − 1.8 +VS − 2.0 +VS − 1.8 −VS + 1.2 −VS + 1.2 +Vs − 1.6 +Vs − 1.6 −VS + 1.2 −VS + 1.2 +VS − 1.6 +VS − 1.6 65 20 20 VIN+, VIN− = 0 V −VS 1± 0.0001 Rev. 0 | Page 4 of 28 65 24 +VS 20 20 −VS 1± 0.0001 24 +VS V V mA kΩ μA V V/V Data Sheet Parameter POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance Operational 5 AD8421 Test Conditions/ Comments Min Dual supply Single supply ±2.5 5 AR Grade Typ Max 2 TA = −40°C to +85°C −40 −40 Min ±18 36 2.3 2.6 ±2.5 5 +85 +125 −40 −40 BR Grade Typ 2 Max Unit ±18 36 2.3 2.6 V V mA mA +85 +125 °C °C Total voltage noise = √(eni2 + (eno/G)2 + eRG2). See the Theory of Operation section for more information. Total RTI VOS = (VOSI) + (VOSO/G). 3 These specifications do not include the tolerance of the external gain setting resistor, RG. For G > 1, add RG errors to the specifications given in this table. 4 Input voltage range of the AD8421 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more details. 5 See the Typical Performance Characteristics section for expected operation between 85°C and 125°C. 1 2 ARM AND BRM GRADES Table 2. Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance G=1 G = 10 G = 100 G = 1000 Over Temperature, G = 1 CMRR at 20 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz 1 Input Voltage Noise, eni Output Voltage Noise, eno Peak to Peak, RTI G=1 G = 10 G = 100 to 1000 Current Noise Spectral Density Peak to Peak, RTI VOLTAGE OFFSET 2 Input Offset Voltage, VOSI Over Temperature Average TC Output Offset Voltage, VOSO Over Temperature Average TC Test Conditions/ Comments Min ARM Grade Typ Max Min BRM Grade Typ Max Unit VCM = −10 V to +10 V TA = −40°C to +85°C VCM = −10 V to +10 V 84 104 124 134 80 92 112 132 140 90 dB dB dB dB dB 80 90 100 100 80 90 100 100 dB dB dB dB VIN+, VIN− = 0 V 3 3.2 60 3 3.2 60 nV/√Hz nV/√Hz 2 0.5 0.07 2 0.5 0.07 2.2 μV p-p μV p-p μV p-p 200 18 200 18 f = 0.1 Hz to 10 Hz f = 1 kHz f = 0.1 Hz to 10 Hz VS = ±5 V to ±15 V TA = −40°C to +85°C 70 135 0.9 600 1 9 TA = −40°C to +85°C Rev. 0 | Page 5 of 28 0.09 fA/√Hz pA p-p 50 135 0.9 400 1 9 μV μV μV/°C μV mV μV/°C AD8421 Parameter Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC DYNAMIC RESPONSE Small Signal Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Settling Time 0.001% G=1 G = 10 G = 100 G = 1000 Slew Rate G = 1 to 100 GAIN 3 Gain Range Gain Error G=1 G = 10 to 1000 Gain Nonlinearity G=1 G = 10 to 1000 Gain vs. Temperature3 G=1 G>1 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range 4 Over Temperature Data Sheet Test Conditions/ Comments VS = ±2.5 V to ±18 V Min 90 110 124 130 ARM Grade Typ Max 120 120 130 140 1 Min 100 120 140 140 120 140 150 150 dB dB dB dB 1 1 10 10 2 0.2 10 10 2 0.2 MHz MHz MHz MHz 0.7 0.4 0.6 5 0.7 0.4 0.6 5 μs μs μs μs 1 0.6 0.8 6 1 0.6 0.8 6 μs μs μs μs 35 35 V/μs 50 0.5 TA = −40°C to +85°C 0.1 Unit nA nA pA/°C nA nA pA/°C TA = −40°C to +85°C 2 8 BRM Grade Typ Max 50 0.1 2 3 1 6 1 1.5 −3 dB 10 V step 10 V step G = 1 + (9.9 kΩ/RG) 1 10,000 1 10,000 V/V 0.02 0.2 % % 1 3 50 10 ppm ppm ppm ppm 1 −50 ppm/°C ppm/°C VOUT = ±10 V 0.05 0.3 VOUT = −10 V to +10 V RL ≥ 2 kΩ RL = 600 Ω RL ≥ 600 Ω VOUT = −5 V to +5 V 1 30 5 1 3 50 10 1 30 5 5 −50 0.1 30||3 30||3 VS = ±2.5 V to ±18 V −VS + 2.3 +VS − 1.8 −VS + 2.3 +VS − 1.8 GΩ||pF GΩ||pF V TA = −40°C TA = +85°C −VS + 2.5 −VS + 2.1 +VS − 2.0 +VS − 1.8 −VS + 2.5 −VS + 2.1 +VS − 2.0 +VS − 1.8 V V Rev. 0 | Page 6 of 28 30||3 30||3 Data Sheet Parameter OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output POWER SUPPLY Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance Operational 5 AD8421 Test Conditions/ Comments RL = 2 kΩ VS = ±2.5 V to ±18 V TA = −40°C to +85°C Min ARM Grade Typ Max −VS + 1.2 −VS + 1.2 +VS − 1.6 +VS − 1.6 Min −VS + 1.2 −VS + 1.2 65 20 20 VIN+, VIN− = 0 V −VS ±2.5 5 2 TA = −40°C to +85°C −40 −40 +Vs − 1.6 +Vs − 1.6 65 24 +VS 20 20 −VS 1± 0.0001 Dual supply Single supply BRM Grade Typ Max ±2.5 5 +85 +125 −40 −40 2 V V mA 24 +VS kΩ μA V V/V ±18 36 2.3 2.6 V V mA mA +85 +125 °C °C 1± 0.0001 ±18 36 2.3 2.6 Unit Total voltage noise = √(eni2 + (eno/G)2 + eRG2). See the Theory of Operation section for more information. Total RTI VOS = (VOSI) + (VOSO/G). 3 These specifications do not include the tolerance of the external gain setting resistor, RG. For G > 1, add RG errors to the specifications given in this table. 4 Input voltage range of the AD8421 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more information. 5 See the Typical Performance Characteristics section for expected operation between 85°C and 125°C. 1 2 Rev. 0 | Page 7 of 28 AD8421 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Supply Voltage Output Short-Circuit Current Duration Maximum Voltage at −IN or +IN1 Minimum Voltage at −IN or +IN Maximum Voltage at REF2 Minimum Voltage at REF Storage Temperature Range Operating Temperature Range Maximum Junction Temperature ESD Human Body Model Charged Device Model Machine Model θJA is specified for a device in free air using a 4-layer JEDEC printed circuit board (PCB). Rating ±18 V Indefinite −VS + 40 V +VS − 40 V +VS + 0.3 V −VS − 0.3 V −65°C to +150°C −40°C to +125°C 150°C Table 4. Package 8-Lead SOIC 8-Lead MSOP ESD CAUTION 2 kV 1.25 kV 0.2 kV 1 For voltages beyond these limits, use input protection resistors. See the Theory of Operation section for more information. 2 There are ESD protection diodes from the reference input to each supply, so REF cannot be driven beyond the supplies in the same way that +IN and −IN can. See the Reference Terminal section for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 28 θJA 107.8 138.6 Unit °C/W °C/W Data Sheet AD8421 –IN 1 RG AD8421 8 +VS 2 7 VOUT RG 3 6 REF +IN 4 5 –VS TOP VIEW (Not to Scale) 10123-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2, 3 4 5 6 7 8 Mnemonic −IN RG +IN −VS REF VOUT +VS Description Negative Input Terminal. Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (9.9 kΩ/RG). Positive Input Terminal. Negative Power Supply Terminal. Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level shift the output. Output Terminal. Positive Power Supply Terminal. Rev. 0 | Page 9 of 28 AD8421 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±15 V, VREF = 0 V, RL = 2 kΩ, unless otherwise noted. 600 600 500 500 300 300 200 200 100 100 0 –60 –40 –20 0 20 40 60 INPUT OFFSET VOLTAGE (µV) 0 –400 –200 –100 0 100 200 300 400 OUTPUT OFFSET VOLTAGE (µV) Figure 7. Typical Distribution of Output Offset Voltage Figure 4. Typical Distribution of Input Offset Voltage 1800 1200 1500 1000 1200 800 UNITS 900 600 600 400 300 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 INPUT BIAS CURRENT (nA) 10123-004 200 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 INPUT OFFSET CURRENT (nA) 10123-007 UNITS –300 10123-006 UNITS 400 10123-003 UNITS 400 Figure 8. Typical Distribution of Input Offset Current Figure 5. Typical Distribution of Input Bias Current 1600 1400 1400 1200 1200 1000 UNITS 600 400 200 200 –15 –10 –5 0 5 10 PSRR (µV/V) 15 20 0 –120 –90 –60 –30 0 30 60 90 CMRR (µV/V) Figure 9. Typical Distribution of CMRR (G = 1) Figure 6. Typical Distribution of PSRR (G = 1) Rev. 0 | Page 10 of 28 120 10123-008 0 –20 800 600 400 10123-005 UNITS 1000 800 Data Sheet AD8421 4 15 G=1 G = 100 VS = ±15V 3 COMMON-MODE VOLTAGE (V) VS = ±12V 5 0 –5 –10 VS = ±2.5V 0 –1 0 5 10 15 –3 –4 –3 –2 –1 0 1 2 3 4 OUTPUT VOLTAGE (V) Figure 10. Input Common-Mode Voltage vs. Output Voltage; VS = ±12 V and ±15 V (G = 1) 10123-012 –5 10123-009 –10 OUTPUT VOLTAGE (V) Figure 13. Input Common-Mode Voltage vs. Output Voltage; VS = ±2.5 V and ±5 V (G = 100) 4 40 G=1 VS = ±5V 3 30 VS = 5V G=1 20 2 INPUT CURRENT (mA) VS = ±2.5V 1 0 –1 –2 10 0 –10 –20 –30 –3 –2 –1 0 1 2 3 4 OUTPUT VOLTAGE (V) –40 –35 –30 –25 –20 –15 –10 –5 10123-010 –3 –4 Figure 11. Input Common-Mode Voltage vs. Output Voltage; VS = ±2.5 V and ±5 V (G = 1) 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) 10123-013 COMMON-MODE VOLTAGE (V) 1 –2 –15 –15 Figure 14. Input Overvoltage Performance; G = 1, +VS = 5 V, −VS = 0 V 15 30 VS = ±15V G = 100 VS = ±15V G=1 10 20 INPUT CURRENT (mA) VS = ±12V 5 0 –5 –15 –15 10 0 –10 –20 –10 –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) 10123-011 COMMON-MODE VOLTAGE (V) VS = ±5V 2 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 INPUT VOLTAGE (V) Figure 15. Input Overvoltage Performance; G = 1, VS = ±15 V Figure 12. Input Common-Mode Voltage vs. Output Voltage; VS = ±12 V and ±15 V (G = 100) Rev. 0 | Page 11 of 28 10123-014 COMMON-MODE VOLTAGE (V) 10 AD8421 Data Sheet 160 40 GAIN = 1000 140 GAIN = 100 POSITIVE PSRR (dB) 120 GAIN = 10 10 0 –10 100 GAIN = 1 80 60 –20 40 –30 20 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) 0 0.1 10123-015 INPUT CURRENT (mA) 20 1 Figure 16. Input Overvoltage Performance; +VS = 5 V, −VS = 0 V, G = 100 100 1k FREQUENCY (Hz) 10k 100k 1M 100k 1M Figure 19. Positive PSRR vs. Frequency 160 30 GAIN = 1000 VS = ±15V G = 100 140 GAIN = 100 20 GAIN = 10 NEGATIVE PSRR (dB) 120 INPUT CURRENT (mA) 10 10123-018 30 VS = 5V G = 100 10 0 –10 GAIN = 1 100 80 60 40 –20 –15 –10 –5 0 5 10 15 20 25 INPUT VOLTAGE (V) 0 0.1 1 70 2.0 60 1.5 50 1.0 40 0.5 30 GAIN (dB) 2.5 0 –0.5 20 0 –1.5 –10 –2.0 –20 –6 –4 –2 0 2 4 6 8 10 12 COMMON-MODE VOLTAGE (V) 14 10k Figure 18. Input Bias Current vs. Common-Mode Voltage GAIN = 1000 GAIN = 100 GAIN = 10 10 –1.0 –2.5 –12 –10 –8 100 1k FREQUENCY (Hz) Figure 20. Negative PSRR vs. Frequency 10123-017 BIAS CURRENT (nA) Figure 17. Input Overvoltage Performance; VS = ±15 V, G = 100 10 GAIN = 1 –30 100 1k 10k 100k FREQUENCY (Hz) Figure 21. Gain vs. Frequency Rev. 0 | Page 12 of 28 1M 10M 10123-020 –20 10123-016 –30 –25 10123-019 20 Data Sheet 160 6 GAIN = 1000 REPRESENTATIVE SAMPLES GAIN = 100 140 4 BIAS CURRENT (nA) GAIN = 10 120 GAIN = 1 100 80 60 2 0 –2 –4 –6 1 10 100 1k 10k 100k FREQUENCY (Hz) –8 –40 10123-021 40 0.1 –25 –10 5 20 35 50 65 80 95 110 125 110 125 110 125 TEMPERATURE (°C) 10123-024 CMRR (dB) AD8421 Figure 25. Input Bias Current vs. Temperature Figure 22. CMRR vs. Frequency 100 160 GAIN = 1000 80 REPRESENTATIVE SAMPLES GAIN = 1 140 60 CMRR (dB) 120 GAIN ERROR (µV/V) GAIN = 100 GAIN = 10 100 GAIN = 1 80 40 20 0 –20 –40 60 1 10 100 1k 10k 100k FREQUENCY (Hz) –80 –40 10123-022 40 0.1 –25 5 20 35 50 65 80 95 TEMPERATURE (°C) Figure 23. CMRR vs. Frequency, 1 kΩ Source Imbalance Figure 26. Gain vs. Temperature (G = 1) 2.0 15 REPRESENTATIVE SAMPLES GAIN = 1 10 1.5 5 CMRR (µV/V) 1.0 0.5 0 –5 0 0 5 10 15 20 25 30 35 40 45 50 WARM-UP TIME (Seconds) –15 –40 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) Figure 27. CMRR vs. Temperature (G = 1) Figure 24. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time Rev. 0 | Page 13 of 28 10123-074 –0.5 –10 10123-023 CHANGE IN INPUT OFFSET VOLTAGE (µV) –10 10123-025 –60 AD8421 Data Sheet 40 3.0 –SR 35 VS = ±15V 30 2.0 SLEW RATE (V/µs) VS = ±5V 1.5 1.0 20 15 10 0.5 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 0 –40 10123-026 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 31. Slew Rate vs. Temperature, VS = ±5 V (G = 1) Figure 28. Supply Current vs. Temperature (G = 1) +VS 80 –0.5 ISHORT+ 40 20 0 –20 –40 –60 –80 ISHORT– –120 –40 –25 –10 5 20 35 –1.5 –2.0 –2.5 +2.5 +2.0 +1.5 –40°C +25°C +85°C +105°C +125°C +1.0 +0.5 50 65 80 95 110 125 TEMPERATURE (°C) –VS 10123-027 –100 –1.0 2 4 6 8 10 12 14 16 18 10123-030 INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES 60 20 SUPPLY VOLTAGE (±VS) Figure 32. Input Voltage Limit vs. Supply Voltage Figure 29. Short-Circuit Current vs. Temperature (G = 1) +VS 40 –0.5 OUTPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES 35 –SR 30 +SR 25 20 15 10 5 –1.0 –1.5 –2.0 –40°C +25°C +85°C +105°C +125°C –2.5 +2.5 +2.0 +1.5 +1.0 +0.5 0 –40 –25 –10 5 20 35 50 65 80 95 110 TEMPERATURE (°C) 125 10123-028 SLEW RATE (V/µs) –25 10123-029 5 0 –40 SHORT-CIRCUIT CURRENT (mA) +SR 25 10123-031 SUPPLY CURRENT (mA) 2.5 –VS 0 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (±VS) Figure 33. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ Figure 30. Slew Rate vs. Temperature, VS = ±15 V (G = 1) Rev. 0 | Page 14 of 28 AD8421 +VS 5 –0.5 4 GAIN = 1 –1.0 3 –1.5 NONLINEARITY (ppm) –2.0 –40°C +25°C +85°C +105°C +125°C –2.5 +2.5 +2.0 2 1 0 –1 –2 +1.5 –3 +1.0 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (±VS) –5 –10 10123-032 –VS RL = 2kΩ RL = 10kΩ –4 +0.5 –8 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 600 Ω 10123-035 OUTPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES Data Sheet Figure 37. Gain Nonlinearity (G = 1), RL = 10 kΩ, 2 kΩ 5 15 GAIN = 1 4 3 NONLINEARITY (ppm) OUTPUT VOLTAGE SWING (V) 10 5 –40°C +25°C +85°C +105°C +125°C 0 –5 2 1 RL = 600Ω 0 –1 –2 –3 –10 1k 10k 100k LOAD (Ω) –5 –10 10123-033 –15 100 –4 –2 0 2 4 6 8 10 Figure 38. Gain Nonlinearity (G = 1), RL = 600 Ω +VS 100 –2 80 –4 60 GAIN = 1000 –40°C +25°C +85°C +105°C +125°C –8 +8 +6 40 20 –20 –40 +4 –60 +2 –80 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 OUTPUT CURRENT (A) 0.10 Figure 36. Output Voltage Swing vs. Output Current RL = 600Ω 0 –100 –10 –8 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) Figure 39. Gain Nonlinearity (G = 1000), RL = 600 Ω, VOUT = ±10 V Rev. 0 | Page 15 of 28 10123-072 NONLINEARITY (ppm) –6 10123-034 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –6 OUTPUT VOLTAGE (V) Figure 35. Output Voltage Swing vs. Load Resistance –VS –8 10123-036 –4 AD8421 Data Sheet 10k 100 GAIN = 1000 80 CURRENT NOISE (fA/√Hz) NONLINEARITY (ppm) 60 40 20 RL = 600Ω 0 –20 –40 1k 100 –60 –4 –3 –2 –1 0 1 2 3 4 5 OUTPUT VOLTAGE (V) 10 0.1 10123-073 –100 –5 1 10 100 1k 10k 10123-039 –80 100k FREQUENCY (Hz) Figure 40. Gain Nonlinearity (G = 1000), RL = 600 Ω, VOUT = ±5 V Figure 43. Current Noise Spectral Density vs. Frequency 100 GAIN = 1 GAIN = 10 10 1 10 100 1k 10k 100k FREQUENCY (Hz) 1s/DIV 10123-037 5pA/DIV 1 10123-040 GAIN = 100 GAIN = 1000 Figure 41. RTI Voltage Noise Spectral Density vs. Frequency Figure 44. 0.1 Hz to 10 Hz Current Noise 30 G = 1000, 40nV/DIV OUTPUT VOLTAGE (V p-p) 25 G = 1, 1µV/DIV 20 15 10 1s/DIV 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 42. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1, G = 1000) Figure 45. Large Signal Frequency Response Rev. 0 | Page 16 of 28 10M 10123-045 5 10123-038 VOLTAGE NOISE SPECTRAL DENSITY (nV/√Hz) 1k Data Sheet AD8421 5V/DIV 5V/DIV 720ns TO 0.01% 1.12µs TO 0.001% 3.8µs TO 0.01% 5.76µs TO 0.001% 1µs/DIV Figure 46. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step, VS = ±15 V, RL = 2 kΩ, CL = 100 pF 4µs/DIV 10123-044 0.002%/DIV 10123-041 0.002%/DIV Figure 49. Large Signal Pulse Response and Settling Time (G = 1000), 10 V Step, VS = ±15 V, RL = 2 kΩ, CL = 100 pF 2500 SETTLING TIME (ns) 2000 420ns TO 0.01% 604ns TO 0.001% 0.002%/DIV 1500 SETTLED TO 0.001% 1000 SETTLED TO 0.01% 1µs/DIV 10123-042 500 GAIN = 1 0 2 4 6 8 10 12 14 16 18 20 STEP SIZE (V) 10123-054 5V/DIV Figure 50. Settling Time vs. Step Size (G = 1), RL = 2 kΩ, CL = 100 pF Figure 47. Large Signal Pulse Response and Settling Time (G = 10), 10 V Step, VS = ±15 V, RL = 2 kΩ, CL = 100 pF GAIN = 1 5V/DIV 704ns TO 0.01% 764ns TO 0.001% Figure 48. Large Signal Pulse Response and Settling Time (G = 100), 10 V Step, VS = ±15 V, RL = 2 kΩ, CL = 100 pF 50mV/DIV 1µs/DIV 10123-046 1µs/DIV 10123-043 0.002%/DIV Figure 51. Small Signal Pulse Response (G = 1), RL = 600 Ω, CL = 100 pF Rev. 0 | Page 17 of 28 AD8421 Data Sheet 1µs/DIV 10123-047 50mV/DIV 20pF 50pF NO LOAD 100pF G=1 50mV/DIV Figure 52. Small Signal Pulse Response (G = 10), RL = 600 Ω, CL = 100 pF 1µs/DIV 10123-053 GAIN = 10 Figure 55. Small Signal Response with Various Capacitive Loads (G = 1), RL = Infinity –40 GAIN = 100 –50 RL ≥ 600Ω VOUT = 10V p-p –60 AMPLITUDE (dBc) –70 –80 –90 –100 –110 –120 1µs/DIV –140 –150 10 100 1k 10k FREQUENCY (Hz) 10123-055 20mV/DIV 10123-048 –130 Figure 56. Second Harmonic Distortion vs. Frequency (G = 1) Figure 53. Small Signal Pulse Response (G = 100), RL = 600 Ω, CL = 100 pF –40 GAIN = 1000 –50 –60 NO LOAD RL = 2kΩ RL = 600Ω VOUT = 10V p-p AMPLITUDE (dBc) –70 –80 –90 –100 –110 –120 2µs/DIV –140 –150 10 100 1k 10k FREQUENCY (Hz) Figure 54. Small Signal Pulse Response (G = 1000), RL = 600 Ω, CL = 100 pF Rev. 0 | Page 18 of 28 Figure 57. Third Harmonic Distortion vs. Frequency (G = 1) 10123-056 20mV/DIV 10123-049 –130 Data Sheet –50 NO LOAD RL = 2kΩ RL = 600Ω –20 VOUT = 10V p-p –30 –40 –70 –80 –90 –60 –70 –80 –90 –100 –120 –110 100 1k 10k FREQUENCY (Hz) 10123-075 –130 –120 10 Figure 58. Second Harmonic Distortion vs. Frequency (G = 1000) –40 VOUT = 10V p-p RL ≥ 600Ω –60 –70 –80 –90 –100 1k 10k FREQUENCY (Hz) 10123-076 –110 100 –140 10 100 1k FREQUENCY (Hz) Figure 60. THD vs. Frequency –50 AMPLITUDE (dBc) VOUT = 10V p-p RL = 2kΩ –110 –100 –120 10 =1 = 10 = 100 = 1000 –50 AMPLITUDE (dBc) AMPLITUDE (dBc) –60 G G G G Figure 59. Third Harmonic Distortion vs. Frequency (G = 1000) Rev. 0 | Page 19 of 28 10k 10123-077 –40 AD8421 AD8421 Data Sheet THEORY OF OPERATION +VS I VB I A1 IB COMPENSATION A2 C1 10kΩ +VS C2 10kΩ NODE 1 –IN R1 Q1 4.95kΩ superβ ESD AND OVERVOLTAGE PROTECTION NODE 3 +VS +VS RG +VS 10kΩ R2 4.95kΩ Q2 superβ ESD AND OVERVOLTAGE PROTECTION –VS 10kΩ REF +IN NODE 4 I OUTPUT A3 NODE 2 –VS I –VS 10123-057 IB COMPENSATION DIFFERENCE AMPLIFIER STAGE GAIN STAGE Figure 61. Simplified Schematic ARCHITECTURE The AD8421 is based on the classic 3-op-amp topology. This topology has two stages: a preamplifier to provide differential amplification, followed by a difference amplifier that removes the common-mode voltage. Figure 61 shows a simplified schematic of the AD8421. Topologically, Q1, A1, R1 and Q2, A2, R2 can be viewed as precision current feedback amplifiers. Input Transistors Q1 and Q2 are biased at a fixed current so that any input signal forces the output voltages of A1 and A2 to change accordingly. The differential signal applied to the inputs is replicated across the RG pins. Any current through RG also flows through R1 and R2, creating a gained differential voltage between Node 1 and Node 2. The amplified differential and common-mode signals are applied to a difference amplifier that rejects the common-mode voltage but preserves the amplified differential voltage. The difference amplifier employs innovations that result in very low output errors such as offset voltage and drift, distortion at various loads, as well as output noise. Laser-trimmed resistors allow for a highly accurate in-amp with gain error less than 0.01% and CMRR that exceeds 94 dB (G = 1). The high performance pinout and special attention given to design and layout allow for high CMRR performance across a wide frequency and temperature range. Using superbeta input transistors and bias current compensation, the AD8421 offers extremely high input impedance, low bias current, low offset current, low current noise, and extremely low voltage noise of 3 nV/√Hz. The current-limiting and overvoltage protection scheme allow the input to go 40 V from the opposite rail at all gains without compromising the noise performance. The transfer function of the AD8421 is Users can easily and accurately set the gain using a single standard resistor. GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the AD8421. The gain can be calculated by referring to Table 6 or by using the following gain equation: RG = 9.9 kΩ G −1 The AD8421 defaults to G = 1 when no gain resistor is used. To determine the total gain accuracy of the system, add the tolerance and gain drift of the RG resistor to the specifications of the AD8421. When the gain resistor is not used, gain error and gain drift are minimal. Table 6. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG 10 kΩ 2.49 kΩ 1.1 kΩ 523 Ω 200 Ω 100 Ω 49.9 Ω 20 Ω 10 Ω 4.99 Ω Calculated Gain 1.99 4.98 10.00 19.93 50.50 100.0 199.4 496.0 991.0 1985 RG Power Dissipation The AD8421 duplicates the differential voltage across its inputs onto the RG resistor. Choose an RG resistor size that is sufficient to handle the expected power dissipation at ambient temperature. VOUT = G × (V+IN − V−IN) + VREF where G = 1 + 9.9 kΩ RG Rev. 0 | Page 20 of 28 Data Sheet AD8421 REFERENCE TERMINAL Common-Mode Rejection Ratio over Frequency The output voltage of the AD8421 is developed with respect to the potential on the reference terminal. This can be used to sense the ground at the load, thereby taking advantage of the CMRR to reject ground noise or to introduce a precise offset to the signal at the output. For example, a voltage source can be tied to the REF pin to level shift the output, allowing the AD8421 to drive a singlesupply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or −VS by more than 0.3 V. Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To maintain high CMRR over frequency, closely match the input source impedance and capacitance of each path. Place additional source resistance in the input path (for example, input protection resistors) close to the in-amp inputs, to minimize the interaction of the resistance with parasitic capacitance from the PCB traces. For best performance, maintain a source impedance to the REF terminal that is below 1 Ω. As shown in Figure 61, the reference terminal, REF, is at one end of a 10 kΩ resistor. Additional impedance at the REF terminal adds to this 10 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be calculated as follows: 2(10 kΩ + RREF)/(20 kΩ + RREF) Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades CMRR. INCORRECT CORRECT AD8421 AD8421 REF REF V V + 10123-058 OP1177 – Parasitic capacitance at the gain setting pins (RG) can also affect CMRR over frequency. If the board design has a component at the gain setting pins (for example, a switch or jumper), choose a component such that the parasitic capacitance is as small as possible. Power Supplies and Grounding Use a stable dc voltage to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. Place a 0.1 μF capacitor as close as possible to each supply pin. Because the length of the bypass capacitor leads is critical at high frequency, surface-mount capacitors are recommended. Any parasitic inductance in the bypass ground trace works against the low impedance that is created by the bypass capacitor. As shown in Figure 64, a 10 μF capacitor can be used farther away from the device. For these larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. In most cases, the 10 μF capacitor can be shared by other local precision integrated circuits. +VS Figure 62. Driving the Reference Pin 0.1µF INPUT VOLTAGE RANGE 10µF +IN The 3-op-amp architecture of the AD8421 applies gain in the first stage before removing the common-mode voltage in the difference amplifier stage. Internal nodes between the first and second stages (Node 1 and Node 2 in Figure 61) experience a combination of a gained signal, a common-mode signal, and a diode drop. The voltage supplies can limit the combined signal, even when the individual input and output signals are not limited. Figure 10 through Figure 13 show this limitation in detail. RG VOUT AD8421 LOAD 0.1µF –VS 10µF 10123-060 REF –IN Figure 64. Supply Decoupling, REF, and Output Referred to Local Ground LAYOUT To ensure optimum performance of the AD8421 at the PCB level, care must be taken in the design of the board layout. The pins of the AD8421 are arranged in a logical manner to aid in this task. –IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF AD8421 TOP VIEW (Not to Scale) 5 –VS 10123-059 +IN 4 A ground plane layer helps to reduce parasitic inductances, which minimizes voltage drops with changes in current. The area of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the impedance of the path at high frequency. Large changes in currents in an inductive decoupling path or ground return create unwanted effects due to the coupling of such changes into the amplifier inputs. Because load currents flow from the supplies, the load should be connected at the same physical location as the bypass capacitor grounds. Figure 63. Pin Configuration Diagram Rev. 0 | Page 21 of 28 AD8421 Data Sheet Reference Pin The output voltage of the AD8421 is developed with respect to the potential on the reference terminal. Ensure that REF is tied to the appropriate local ground. INPUT BIAS CURRENT RETURN PATH For applications where the AD8421 encounters voltages beyond the limits in the Absolute Maximum Ratings table, external protection is required. This external protection depends on the duration of the overvoltage event and the noise performance that is required. CORRECT +VS The remaining AD8421 terminals should be kept within the supplies. All terminals of the AD8421 are protected against ESD. Input Voltages Beyond the Maximum Ratings The input bias current of the AD8421 must have a return path to ground. When using a floating source without a current return path (such as a thermocouple), create a current return path as shown in Figure 65. INCORRECT protection required at all gains. For example, if +VS = +5 V and −VS = −8 V, the part can safely withstand voltages from −35 V to +32 V. +VS For short-lived events, transient protectors (such as metal oxide varistors (MOVs)), may be all that is required. +VS AD8421 AD8421 REF + VIN+ – REF I AD8421 RPROTECT + VIN+ – +VS I AD8421 RPROTECT –VS + VIN– – TRANSFORMER +VS +VS –VS TRANSIENT PROTECTION RPROTECT AD8421 + VIN+ – AD8421 REF REF 10MΩ + –VS VIN– – THERMOCOUPLE +VS C AD8421 C REF REF –VS 10123-061 R –VS CAPACITIVELY COUPLED CAPACITIVELY COUPLED Figure 65. Creating an Input Bias Current Return Path INPUT VOLTAGES BEYOND THE SUPPLY RAILS The AD8421 has very robust inputs. It typically does not need additional input protection, as shown in Figure 66. +VS + VIN+ – I AD8421 –VS MOST APPLICATIONS SIMPLE CONTINUOUS PROTECTION +VS RPROTECT + VIN+ – +VS I –VS +VS AD8421 RPROTECT –VS + VIN– – –VS –VS LOW NOISE CONTINUOUS OPTION 2 For longer events, use resistors in series with the inputs, combined with diodes. To avoid degrading bias current performance, low leakage diodes such as the BAV199 or FJH1100 are recommended. The diodes prevent the voltage at the input of the amplifier from exceeding the maximum ratings, and the resistors limit the current into the diodes. Because most external diodes can easily handle 100 mA or more, resistor values do not need to be large and, therefore, have a minimal impact on noise performance. At the expense of some noise performance, another solution is to use series resistors. In the case of overvoltage, current into the AD8421 inputs is internally limited. Although the AD8421 inputs must be kept within the limits defined in the Absolute Maximum Ratings section, the I × R drop across the protection resistor increases the maximum voltage that the system can withstand, as follows: For positive input signals 10123-062 + VIN+ – –VS Figure 67. Input Protection Options for Input Voltages Beyond Absolute Maximum Ratings R 1 fHIGH-PASS = 2πRC AD8421 C AD8421 LOW NOISE CONTINUOUS OPTION 1 +VS C I RPROTECT –VS THERMOCOUPLE +VS + VIN– – 10123-063 –VS TRANSFORMER VMAX_NEW = (40 V + Negative Supply) + IIN × RPROTECT Figure 66. Typical Application; No Input Protection Required For negative input signals The AD8421 inputs are current limited; therefore, input voltages can be up to 40 V from the opposite supply rail, with no input Rev. 0 | Page 22 of 28 VMIN_NEW = (Positive Supply − 40 V) − IOUT × RPROTECT Data Sheet AD8421 Overvoltage performance is shown in Figure 14, Figure 15, Figure 16, and Figure 17. The AD8421 inputs can withstand a current of 40 mA at room temperature for at least a day. This time is cumulative over the life of the device. If long periods of overvoltage are expected, the use of an external protection method is recommended. Under extreme input conditions, the output of the amplifier may invert. RADIO FREQUENCY INTERFERENCE (RFI) RF rectification is often a problem when amplifiers are used in applications that have strong RF signals. The problem is intensified if long leads or PCB traces are required to connect the amplifier to the signal source. The disturbance can appear as a dc offset voltage or a train of pulses. High frequency signals can be filtered with a low-pass filter network at the input of the instrumentation amplifier, as shown in Figure 68. +VS 0.1µF CC 1nF R +IN 33Ω L* CD 10nF REF –IN 33Ω CC 1nF *CHIP FERRITE BEAD. 10123-067 –VS Figure 68. RFI Suppression The choice of resistor and capacitor values depends on the desired trade-off between noise, input impedance at high frequencies, CMRR, signal bandwidth, and RFI immunity. An RC network limits both the differential and common-mode bandwidth, as shown in the following equations: FilterFreq uency DIFF = FilterFreq uency CM = CALCULATING THE NOISE OF THE INPUT STAGE The total noise of the amplifier front end depends on much more than the 3.2 nV/√Hz specification of this data sheet. The three main contributors to noise are: the source resistance, the voltage noise of the instrumentation amplifier, and the current noise of the instrumentation amplifier. Source Resistance Noise 10µF 0.1µF The resistors used for the RFI filter can be the same as those used for input protection. In the following calculations, noise is referred to the input (RTI). In other words, all sources of noise are calculated as if the source appeared at the amplifier input. To calculate the noise referred to the amplifier output (RTO), multiply the RTI noise by the gain of the instru-mentation amplifier. VOUT AD8421 R For best results, place the RFI filter network as close as possible to the amplifier. Layout is critical to ensure that RF signals are not picked up on the traces after the filter. If RF interference is too strong to be filtered sufficiently, shielding is recommended. Any sensor connected to the AD8421 has some output resistance. There may also be resistance placed in series with inputs for protection from either overvoltage or radio frequency interference. This combined resistance is labeled R1 and R2 in Figure 69. Any resistor, no matter how well made, has an intrinsic level of noise. This noise is proportional to the square root of the resistor value. At room temperature, the value is approximately equal to 4 nV/√Hz × √(resistor value in kΩ). SENSOR 1 2πR(2C D + C C ) R1 1 2πRC C R2 where CD ≥ 10 CC. RG AD8421 10123-065 L* 10µF To achieve low noise and sufficient RFI filtering, the use of chip ferrite beads is recommended. Ferrite beads increase their impedance with frequency, thus leaving the signal of interest unaffected while preventing RF interference to reach the amplifier. They also help to eliminate the need for large resistor values in the filter, thus minimizing the system’s input-referred noise. The selection of the appropriate ferrite bead and capacitor values is a function of the interference frequency, input lead length, and RF power. Figure 69. Source Resistance from Sensor and Protection Resistors CD affects the differential signal, and CC affects the commonmode signal. A mismatch between R × CC at the positive input and R × CC at the negative input degrades the CMRR of the AD8421. By using a value of CD that is one order of magnitude larger than CC, the effect of the mismatch is reduced and CMRR performance is improved near the cutoff frequencies. For example, assume that the combined sensor and protection resistance is 4 kΩ on the positive input and 1 kΩ on the negative input. Then the total noise from the input resistance is Rev. 0 | Page 23 of 28 (4 × 4 ) + (4 × 1 ) 2 2 = 64 + 16 = 8.9 nV/√Hz AD8421 Data Sheet Voltage Noise of the Instrumentation Amplifier The voltage noise of the instrumentation amplifier is calculated using three parameters: the device output noise, the input noise, and the RG resistor noise. It is calculated as follows: For example, if the R1 source resistance in Figure 69 is 4 kΩ, and the R2 source resistance is 1 kΩ, the total effect from the current noise is calculated as follows: (4 × 0.2 )2 + (1 × 0.2 )2 Total Voltage Noise = (Output Noise / G ) + (Input Noise ) + (Noise of R 2 2 G Resistor )2 For example, for a gain of 100, the gain resistor is 100 Ω. Therefore, the voltage noise of the in-amp is (60 / 100 ) 2 + 3.2 2 + (4 × 0.1 ) = 0.8 nV/√Hz Total Noise Density Calculation To determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current noise contribution by the sum of squares method. For example, if the R1 source resistance in Figure 69 is 4 kΩ, the R2 source resistance is 1 kΩ, and the gain of the in-amp is 100, the total noise, referred to input, is 2 = 3.5 nV/√Hz Current Noise of the Instrumentation Amplifier Current noise is converted to a voltage by the source resistance. The effect of current noise can be calculated by multiplying the specified current noise of the in-amp by the value of the source resistance. Rev. 0 | Page 24 of 28 8. 9 2 + 3.5 2 + 0.8 2 = 9.6 nV/√Hz Data Sheet AD8421 APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT CONFIGURATION Figure 70 shows an example of how to configure the AD8421 for differential output. +IN AD8421 Because this circuit is susceptible to instability, a capacitor is included to limit the effective op amp bandwidth. This capacitor can be omitted if the amplifier pairing is stable. +OUT –IN 10kΩ 12pF 10kΩ VBIAS The open-loop gain and phase of any amplifier may vary with process variation and temperature. Additional phase lag can be introduced by resistive or capacitive loading. To guarantee stability, the value of the capacitor in Figure 70 should be determined with a sample of circuits by evaluating the small signal pulse response of the circuit with load at the extremes of the output dynamic range. + – OP AMP –OUT 10123-066 REF Although the dc performance and resistor matching of the op amp affect the dc common-mode output accuracy, such errors are likely to be rejected by the next device in the signal chain and, therefore, typically have little effect on overall system accuracy. Figure 70. Differential Output Configuration with Op Amp The differential output voltage is set by the following equation: VDIFF_OUT = V+OUT − V−OUT = Gain × (V+IN − V−IN) The common-mode output is set by the following equation: VCM_OUT = (V+OUT + V−OUT)/2 = VBIAS The advantage of this circuit is that the dc differential accuracy depends on the AD8421, not on the op amp or the resistors. In addition, this circuit takes advantage of the precise control that the AD8421 has of its output voltage relative to the reference voltage. The ambient temperature should also be varied over the expected range to evaluate its effect on stability. The voltage at +OUT may still have some overshoot after the circuit is tuned because the AD8421 output amplifier responds faster than the op amp. A 12 pF capacitor is a good starting point. For best large signal ac performance, use an op amp with a high slew rate to match the AD8421 performance of 35 V/μs. High bandwidth is not essential because the system bandwidth is limited by the RC feedback. Some good choices for op amps are the AD8610, ADA4627-1, AD8510, and the ADA4898-1. Rev. 0 | Page 25 of 28 AD8421 Data Sheet frequency, and set the filter cutoff to settle to ½ LSB in one sampling period for a full-scale step. For additional considerations, refer to the data sheet of the ADC in use. DRIVING AN ADC The Class AB output stage, low noise and distortion, and high bandwidth and slew rate make the AD8421 a good choice for driving an ADC in a data acquisition system that requires frontend gain, high CMRR, and dc precision. Figure 71 shows the AD8421, in a gain-of-10 configuration, driving the AD7685, a 16-bit, 250 kSPS pseudodifferential SAR ADC. The RC low-pass filter that is shown between the AD8421 and the AD7685 has several purposes. It isolates the amplifier output from excessive loading from the dynamic ADC inputs, reduces the noise bandwidth of the amplifier, and provides overload protection for the AD7685 analog inputs. The filter cutoff can be determined empirically. To achieve the best ac performance, keep the impedance magnitude greater than 1 kΩ at the maximum input signal +12V ADR435 +5V 0.1µF ±250mV In a gain-of-10 configuration, the AD8421 has approximately 8 nV/√Hz voltage noise RTI (See the Calculating the Noise of the Input Stage section.) The front-end gain makes the system ten times more sensitive to input signals, with only a 7.5 dB reduction of SNR. The high current output and load regulation of the ADR435 allow the AD7685 to be powered directly from the reference without the need to provide another analog supply rail. The reference pin buffer may be any low power, unity-gain stable, dc precision op amp with less than approximately 25 nV/√Hz of wideband noise, such as the OP1177. Not all proper decoupling is shown in Figure 71. Take care to follow decoupling guidelines for both amplifiers and the ADR435. +12V 10Ω 10kΩ +IN G = 10 REF 100Ω AD8421 1.1kΩ 1µF 2.5V 10kΩ REF VDD IN+ 3nF VIO SDI SCK AD7685 –IN –12V 3- OR 4-WIRE INTERFACE SDO IN– CNV GND 2.5V 10123-070 10µF 5kΩ Figure 71. AD8421 Driving an ADC 0 SNR 81.12dB THD –100.91dB SFDR 90.71dB AMPLITUDE (dB OF FULL SCALE) –20 –40 –60 –80 –100 –120 –160 0 25 50 75 FREQUENCY (kHz) 100 125 10123-071 –140 Figure 72. Typical Spectrum of the AD8421 (G = 10) Driving the AD7685 Rev. 0 | Page 26 of 28 Data Sheet AD8421 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 5 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 73. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA 0.80 0.55 0.40 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 Figure 74. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD8421ARZ AD8421ARZ-R7 AD8421ARZ-RL AD8421BRZ AD8421BRZ-R7 AD8421BRZ-RL AD8421ARMZ AD8421ARMZ-R7 AD8421ARMZ-RL AD8421BRMZ AD8421BRMZ-R7 AD8421BRMZ-RL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead SOIC_N, standard grade 8-Lead SOIC_N, standard grade, 7” Tape and Reel, 8-Lead SOIC_N, standard grade, 13” Tape and Reel 8-Lead SOIC_N, high performance grade 8-Lead SOIC_N, high performance grade, 7” Tape and Reel 8-Lead SOIC_N, high performance grade, 13” Tape and Reel 8-Lead MSOP, standard grade 8-Lead MSOP, standard grade, 7” Tape and Reel 8-Lead MSOP, standard grade, 13” Tape and Reel 8-Lead MSOP, high performance grade 8-Lead MSOP, high performance grade, 7” Tape and Reel 8-Lead MSOP, high performance grade, 13” Tape and Reel Z = RoHS Compliant Part. Rev. 0 | Page 27 of 28 Package Option R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 Branding Y49 Y49 Y49 Y4A Y4A Y4A AD8421 Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10123-0-5/12(0) Rev. 0 | Page 28 of 28