FEATURES Fixed gain of 2000 Access to internal nodes provides flexibility Low noise: 1.5 nV/√Hz input voltage noise High accuracy dc performance Gain drift: 5 ppm/°C Offset drift: 0.3 μV/°C Gain accuracy: 0.05% CMRR: 140 dB min Excellent ac specifications Bandwidth: 3.5 MHz Slew rate: 40 V/μs Power supply range: ±4 V to ±18 V 8-lead SOIC package ESD protection: 5000 V (HBM) Temperature range for specified performance: −40°C to +85°C Operational up to 125°C APPLICATIONS Sensor interface Medical instrumentation Patient monitoring FUNCTIONAL BLOCK DIAGRAM –IN 3kΩ The AD8428 is an ultralow noise instrumentation amplifier designed to accurately measure tiny, high speed signals. It delivers industry-leading gain accuracy, noise, and bandwidth. All gain setting resistors for the AD8428 are internal to the part and are precisely matched. Care is taken in both the chip pinout and layout. This results in excellent gain drift and quick settling to the final gain value after the part is powered on. The high CMRR of the AD8428 prevents unwanted signals from corrupting the signal of interest. The pinout of the AD8428 is designed to avoid parasitic capacitance mismatches that can degrade CMRR at high frequencies. 6kΩ 6kΩ 120kΩ OUT 30.15Ω 3kΩ 6kΩ 6kΩ 120kΩ REF +IN AD8428 –VS +FIL Figure 1. Table 1. Instrumentation Amplifiers by Category1 GeneralPurpose AD8220 AD8221 AD8222 AD8224 AD8228 AD8295 1 GENERAL DESCRIPTION –FIL +VS 09731-001 Data Sheet Low Noise, Low Gain Drift, G = 2000 Instrumentation Amplifier AD8428 Zero Drift AD8231 AD8290 AD8293 AD8553 AD8556 AD8557 Military Grade AD620 AD621 AD524 AD526 AD624 Low Power AD627 AD623 AD8235 AD8236 AD8426 AD8226 AD8227 AD8420 Low Noise AD8428 AD8429 See www.analog.com for the latest instrumentation amplifiers. The AD8428 is one of the fastest instrumentation amplifiers available. The circuit architecture is designed for high bandwidth at high gain. The AD8428 uses a current feedback topology for the initial preamplifier gain stage of 200, followed by a difference amplifier stage of 10. This architecture results in a 3.5 MHz bandwidth at a gain of 2000 for an equivalent gain bandwidth product of 7 GHz. The AD8428 pinout allows access to internal nodes between the first and second stages. This feature can be useful for modifying the frequency response between the two amplification stages, thereby preventing unwanted signals from contaminating the output results. The performance of the AD8428 is specified over the industrial temperature range of −40°C to +85°C. It is available in an 8-lead plastic SOIC package. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. AD8428 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Filter Terminals........................................................................... 13 Applications....................................................................................... 1 Reference Terminal .................................................................... 13 Functional Block Diagram .............................................................. 1 Input Voltage Range................................................................... 14 General Description ......................................................................... 1 Layout .......................................................................................... 14 Revision History ............................................................................... 2 Input Bias Current Return Path ............................................... 15 Specifications..................................................................................... 3 Input Protection ......................................................................... 15 Absolute Maximum Ratings............................................................ 5 Radio Frequency Interference (RFI)........................................ 16 Thermal Resistance ...................................................................... 5 Calculating the Noise of the Input Stage................................. 16 ESD Caution.................................................................................. 5 Applications Information .............................................................. 18 Pin Configuration and Function Descriptions............................. 6 Effect of Passive Network Across the Filter Terminals.......... 18 Typical Performance Characteristics ............................................. 7 Circuits Using the Filter Terminals.......................................... 18 Theory of Operation ...................................................................... 13 Outline Dimensions ....................................................................... 20 Architecture................................................................................. 13 Ordering Guide .......................................................................... 20 REVISION HISTORY 4/12—Rev. 0 to Rev. A Changes to Features Section and Table 1 ...................................... 1 Added B Grade Column to Table 2 ................................................ 3 Changes to Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, and Figure 8....................................................................................... 7 Changes to Filter Terminals Section ............................................ 13 Added Applications Information Section ................................... 18 Changes to Ordering Guide .......................................................... 20 10/11—Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet AD8428 SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 2000, RL = 10 kΩ, unless otherwise noted. Table 2. Parameter COMMON-MODE REJECTION RATIO (CMRR) DC to 60 Hz At 50 kHz NOISE (RTI) Voltage Noise Current Noise VOLTAGE OFFSET Input Offset, VOSI Average TC Offset RTI vs. Supply (PSRR) INPUT CURRENT Input Bias Current Over Temperature Input Offset Current Over Temperature DYNAMIC RESPONSE −3 dB Small Signal Bandwidth Settling Time to 0.01% Settling Time to 0.001% Slew Rate GAIN First Stage Gain Subtractor Stage Gain Total Gain Error Total Gain Nonlinearity Gain Drift INPUT Impedance (Pin to Ground) 1 Input Operating Voltage Range Over Temperature OUTPUT Output Voltage Swing Over Temperature Output Voltage Swing Over Temperature Short-Circuit Current REFERENCE INPUT Input Impedance, RIN Input Current, IIN Voltage Range Reference Gain to Output Reference Gain Error Test Conditions/ Comments RTI, VCM = ±10 V Min A Grade Typ Max 130 110 VIN+, VIN− = 0 V f = 1 kHz f = 0.1 Hz to 10 Hz f = 1 kHz f = 0.1 Hz to 10 Hz Min B Grade Typ Max 140 120 1.3 40 1.5 150 1.5 50 dB dB 1.3 40 1.5 150 100 1 TA = −40°C to +85°C 120 Unit 1.5 50 nV/√Hz nV p-p pA/√Hz pA p-p 25 0.3 μV μV/°C dB 50 130 TA = −40°C to +85°C 250 200 TA = −40°C to +85°C 20 20 nA pA/°C nA pA/°C 10 V step 10 V step 3.5 0.75 1.4 50 3.5 0.75 1.4 50 MHz μs μs V/μs 200 10 0.05 5 5 V/V V/V % ppm ppm/°C GΩ||pF V V 250 50 40 10 40 200 10 VOUT = −10 V to +10 V VOUT = −10 V to +10 V 0.2 5 10 1||2 1||2 VS = ±4 V to ±18 V TA = −40°C to +85°C −VS + 2.5 −VS + 2.5 +VS − 2.5 +VS − 2.5 −VS + 2.5 −VS + 2.5 +VS − 2.5 +VS − 2.5 RL = 2 kΩ TA = −40°C TA = +85°C RL = 10 kΩ TA = −40°C TA = +85°C −VS + 1.7 −VS + 2.0 −VS + 1.6 −VS + 1.7 −VS + 1.8 −VS + 1.4 +VS − 1.2 +VS − 1.3 +VS − 1.1 +VS − 1.0 +VS − 1.2 +VS − 0.9 −VS + 1.7 −VS + 2.0 −VS + 1.6 −VS + 1.7 −VS + 1.8 −VS + 1.4 +VS − 1.2 +VS − 1.3 +VS − 1.1 +VS − 1.0 +VS − 1.2 +VS − 0.9 VIN+, VIN− = 0 V 30 30 132 6.5 132 6.5 −VS +VS 1 0.01 Rev. A | Page 3 of 20 −VS +VS 1 0.01 V V V V V V mA kΩ μA V V/V % AD8428 Parameter FILTER TERMINALS Input Impedance, RIN 2 Voltage Range POWER SUPPLY Operating Range Quiescent Current Over Temperature 1 2 Data Sheet Test Conditions/ Comments Min A Grade Typ Max Min +VS −VS ±18 6.8 8 ±4 6 −VS ±4 6.5 TA = −40°C to +85°C Max Unit +VS kΩ V ±18 6.8 8 V mA mA 6 The differential and common-mode input impedances can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. To calculate the actual impedance, see Figure 1. Rev. A | Page 4 of 20 B Grade Typ 6.5 Data Sheet AD8428 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Supply Voltage Output Short-Circuit Current Duration Maximum Voltage at −IN, +IN1 Maximum Voltage at −FIL, +FIL Differential Input Voltage1 Maximum Voltage at REF Storage Temperature Range Specified Temperature Range Maximum Junction Temperature ESD Human Body Model Charged Device Model Machine Model 1 θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating ±18 V Indefinite ±VS ±VS ±1 V ±VS −65°C to +150°C −40°C to +85°C 140°C Table 4. Thermal Resistance Package 8-Lead SOIC_N ESD CAUTION 5000 V 1250 V 400 V For voltages beyond these limits, use input protection resistors. See the Input Protection section for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 5 of 20 θJA 121 Unit °C/W AD8428 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 8 +VS –FIL 2 7 OUT +FIL 3 6 REF +IN 4 5 –VS TOP VIEW (Not to Scale) 09731-002 AD8428 –IN 1 Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic −IN −FIL +FIL +IN −VS REF OUT +VS Description Negative Input Terminal. Negative Filter Terminal. Positive Filter Terminal. Positive Input Terminal. Negative Power Supply Terminal. Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output. Output Terminal. Positive Power Supply Terminal. Rev. A | Page 6 of 20 Data Sheet AD8428 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 2000, RL = 10 kΩ, unless otherwise noted. 1600 N = 5170 MEAN = 2.12 SD = 7.332 1200 1000 1000 HITS 1200 800 600 400 400 200 200 –40 –20 0 20 40 60 VOSI (µV) N = 5171 MEAN = –10.8 SD = 6.67496 800 600 N = 5171 MEAN = –10.2 SD = 6.52901 0 –60 40 60 1200 1000 1000 HITS 1200 800 800 600 600 400 400 200 200 –40 –20 0 20 40 N = 5171 MEAN = –0.53 SD = 1.41655 1400 60 VOSI (µV) 0 –8 –6 –4 –2 0 2 4 6 8 IOS (nA) 09731-007 N = 5169 MEAN = –2.57 SD = 7.31066 09731-004 HITS 20 1600 1400 Figure 7. Typical Distribution of Input Offset Current Figure 4. Typical Distribution of Input Offset Voltage, VS = ±15 V 1600 1600 N = 5166 MEAN = 0.398 SD = 0.42707 1400 1200 1000 1000 HITS 1200 800 800 600 600 400 400 200 200 –2 –1 0 1 2 VOSI DRIFT (µV/°C) N = 3487 MEAN = –53.9 SD = 86.7774 1400 3 09731-005 HITS 0 Figure 6. Typical Distribution of Input Bias Current 1600 0 –3 –20 IBIAS (nA) Figure 3. Typical Distribution of Input Offset Voltage, VS = ±5 V 0 –60 –40 0 –600 –400 –200 0 200 400 GAIN ERROR (µV/V) Figure 8. Typical Distribution of Gain Error, Gain = 2000, VS = ±15 V, RL = 10 kΩ Figure 5. Typical Distribution of Input Offset Voltage Drift Rev. A | Page 7 of 20 600 09731-008 0 –60 POSITIVE INPUT IBIAS NEGATIVE INPUT IBIAS 1400 09731-003 HITS 1400 09731-006 1600 AD8428 Data Sheet 10 72 66 VS = ±15V 60 54 VS = ±12V 48 5 42 GAIN (dB) INPUT COMMON-MODE VOLTAGE (V) 15 VS = ±5V 0 36 30 24 18 –5 12 6 –10 0 0 5 10 15 OUTPUT VOLTAGE (V) –12 100 1k 14 150 12 140 CMRR (dB) 160 10 8 4 100 0 2 4 6 8 GAIN = 2000 90 VCM = +12V –4 –2 10 12 14 COMMON-MODE VOLTAGE (V) 80 1 10 100 1k 10k 100k 1M 100k 1M FREQUENCY (Hz) Figure 13. CMRR vs. Frequency Figure 10. Input Bias Current vs. Common-Mode Voltage, VS = ±15 V 120 140 GAIN = 2000 110 120 100 90 +PSRR 100 80 CMRR (dB) –PSRR 80 60 70 60 50 40 40 30 20 20 10 0 0.1 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 09731-011 PSRR (dB) 100M 120 110 2 10M 130 6 09731-010 INPUT BIAS CURRENT (nA) 170 VCM = –11.8V –6 1M Figure 12. Gain vs. Frequency 16 0 –14 –12 –10 –8 100k FREQUENCY (Hz) Figure 9. Input Common-Mode Voltage vs. Output Voltage, VS = ±5 V, VS = ±12 V, VS = ±15 V 18 10k 09731-015 –5 09731-016 –10 09731-009 –15 –15 09731-014 –6 Figure 11. PSRR vs. Frequency 0 1 10 100 1k 10k FREQUENCY (Hz) Figure 14. CMRR vs. Frequency, 1 kΩ Source Imbalance Rev. A | Page 8 of 20 Data Sheet AD8428 70 60 4 NORMALIZED AT 25°C CMRR (nV/V) 40 2 1 30 20 10 0 0 –10 –1 –20 0 10 20 30 40 50 60 70 80 90 100 110 120 WARM-UP TIME (Seconds) –30 –40 1.2 9.0 0.8 8.5 0.4 IBIAS– 0 0 –5 –0.4 –10 –0.8 –15 –1.2 –20 –1.6 –25 SUPPLY CURRENT (mA) 5 IBIAS+ 5 20 35 50 65 80 95 110 125 Figure 18. CMRR vs. Temperature, Normalized at 25°C INPUT OFFSET CURRENT (nA) IOS 10 –10 TEMPERATURE (°C) Figure 15. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time 15 –25 09731-020 –2 INPUT BIAS CURRENT (nA) REPRESENTATIVE DATA 50 3 09731-017 CHANGE IN INPUT OFFSET VOLTAGE (µV) 5 8.0 7.5 7.0 6.5 6.0 5.5 –2.0 –10 5 20 35 50 65 80 95 110 –2.4 125 5.0 –40 TEMPERATURE (°C) 200 40 SHORT-CIRCUIT CURRENT (mA) 50 0 –50 –100 –150 20 35 50 65 80 95 110 125 110 125 ISHORT+ 30 20 10 0 –10 –20 ISHORT– –30 –40 REPRESENTATIVE DATA –200 5 20 35 –40 –25 –10 NORMALIZED AT 25°C 50 65 80 95 110 125 TEMPERATURE (°C) 09731-019 GAIN ERROR (µV/V) 50 5 Figure 19. Supply Current vs. Temperature 250 100 –10 TEMPERATURE (°C) Figure 16. Input Bias Current and Input Offset Current vs. Temperature, Normalized at 25°C 150 –25 –50 –40 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) Figure 20. Short-Circuit Current vs. Temperature Figure 17. Gain Error vs. Temperature, Normalized at 25°C Rev. A | Page 9 of 20 09731-022 –25 09731-018 –30 –40 09731-021 NORMALIZED AT 25°C AD8428 Data Sheet +VS 90 –0.4 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES 100 –SR 70 60 50 +SR 40 30 20 10 9 +125°C –0.8 –1.2 +2.0 +1.6 +1.2 +0.8 5 20 35 50 65 80 95 110 125 –VS 6 8 10 11 12 13 14 15 16 17 Figure 24. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ +VS 90 –0.4 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES 100 80 70 –SR 50 40 5 SUPPLY VOLTAGE (±VS) Figure 21. Slew Rate vs. Temperature, VS = ±15 V 60 4 09731-026 –10 09731-023 –25 TEMPERATURE (°C) +SR 30 20 10 –40°C +25°C 7 9 +85°C +125°C –0.8 –1.2 +2.0 +1.6 +1.2 +0.8 +0.4 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) –VS 09731-024 0 –40 5 6 8 10 11 12 13 14 15 16 17 SUPPLY VOLTAGE (±VS) Figure 22. Slew Rate vs. Temperature, VS = ±5 V +VS 4 09731-027 SLEW RATE (V/µs) 7 +85°C +0.4 0 –40 Figure 25. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ 15 –40°C +25°C +85°C +125°C –1.0 –1.5 –40°C +25°C +85°C +125°C 10 OUTPUT VOLTAGE SWING (V) –0.5 –2.0 –2.5 +2.5 +2.0 +1.5 +1.0 5 0 –5 –10 +0.5 –VS 4 6 8 10 12 14 16 SUPPLY VOLTAGE (±VS) 18 09731-025 INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES +25°C –15 100 1k 10k 100k LOAD RESISTANCE (Ω) Figure 26. Output Voltage Swing vs. Load Resistance, VS = ±15 V Figure 23. Input Voltage Limit vs. Supply Voltage Rev. A | Page 10 of 20 09731-028 SLEW RATE (V/µs) 80 –40°C Data Sheet AD8428 +VS +25°C +85°C +125°C –1.0 –1.5 +1.5 +1.0 +0.5 0.1 1 10 OUTPUT CURRENT (mA) Figure 30. RTI Voltage Noise, 0.1 Hz to 10 Hz Figure 27. Output Voltage Swing vs. Output Current, VS = ±15 V 20 1s/DIV 09731-029 20nV/DIV –VS 0.01 09731-032 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –40°C –0.5 16 15 GAIN = 2000 15 14 CURRENT NOISE (pA/√Hz) GAIN NONLINEARITY (ppm) 13 10 5 0 –5 –10 12 11 10 9 8 7 6 5 4 3 –15 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) 10 100 1k 10k 100k FREQUENCY (Hz) GAIN = 2000 10 50pA/DIV 0.1 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) 1s/DIV Figure 29. RTI Voltage Noise Spectral Density vs. Frequency Figure 32. Current Noise, 0.1 Hz to 10 Hz Rev. A | Page 11 of 20 09731-034 1 09731-031 VOLTAGE NOISE (nV/√Hz) 1 Figure 31. Current Noise Spectral Density vs. Frequency Figure 28. Gain Nonlinearity, RL = 10 kΩ 100 1 09731-033 –8 09731-030 2 –20 –10 AD8428 Data Sheet 5V/DIV 752ns TO 0.01% 1408ns TO 0.001% NO LOAD 0.002%/DIV 09731-035 1µs/DIV CL = 770pF 50mV/DIV 1µs/DIV 09731-037 CL = 500pF TIME (µs) Figure 33. Large Signal Pulse Response and Settling Time, 10 V Step, VS = ±15 V Figure 35. Small Signal Pulse Response with Various Capacitive Loads, No Resistive Load 1800 GAIN = 2000 1600 SETTLING TIME (ns) 1400 1200 SETTLED TO 0.001% 1000 800 600 SETTLED TO 0.01% 400 200 0 2 4 6 8 10 12 14 16 STEP SIZE (V) Figure 36. Settling Time vs. Step Size Figure 34. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF Rev. A | Page 12 of 20 18 20 09731-038 1µs/DIV 09731-036 20mV/DIV Data Sheet AD8428 THEORY OF OPERATION I VB A1 A2 C1 –FIL 2 IB COMPENSATION C2 NODE 1 +VS –VS R3 6kΩ R4 6kΩ 120kΩ R7 +VS 7 +VS R1 3kΩ 1 +VS R2 3kΩ Q1 –IN 4 Q2 +IN R5 6kΩ R6 6kΩ +VS –VS –RG RG +RG +VS –VS –VS 120kΩ R8 3 +FIL 30.15Ω –VS OUT A3 NODE 2 6 REF 09731-042 I IB COMPENSATION –VS Figure 37. Simplified Schematic ARCHITECTURE REFERENCE TERMINAL The AD8428 is based on the classic 3-op-amp topology. This topology has two stages: a gain stage (preamplifier) to provide differential amplification by a factor of 200, followed by a difference amplifier (subtractor) stage to remove the common-mode voltage and provide additional amplification by a factor of 10. Figure 37 shows a simplified schematic of the AD8428. The output voltage of the AD8428 is developed with respect to the potential on the reference terminal. This is useful when the output signal must be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8428 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or −VS. The first stage works as follows. To keep its two inputs matched, Amplifier A1 must keep the collector of Q1 at a constant voltage. It does this by forcing −RG to be a constant diode drop from −IN. Similarly, A2 forces +RG to be a constant diode drop from +IN. Therefore, a replica of the differential input voltage is placed across the gain setting resistor, RG. The current that flows across this resistor must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. The second stage is a G = 10 difference amplifier, composed of Amplifier A3 and Resistors R3 through R8. This stage removes the common-mode signal from the amplified differential signal. The transfer function of the AD8428 is For best performance, the source impedance to the REF terminal should be kept well below 1 Ω. As shown in Figure 37, the reference terminal, REF, is at one end of a 120 kΩ resistor. Additional impedance at the REF terminal adds to this 120 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be calculated as follows: 2 × (120 kΩ + RREF)/(240 kΩ + RREF) Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades the CMRR of the amplifier. INCORRECT VOUT = 2000 × (VIN+ − VIN−) + VREF CORRECT FILTER TERMINALS AD8428 REF AD8428 REF V V + OP1177 – Figure 38. Driving the Reference Pin Rev. A | Page 13 of 20 09731-043 The −FIL and +FIL terminals allow access between R3 and R4, and between R5 and R6, respectively. Adding a filter between these two terminals modifies the gain that is applied to the signal before it reaches the second amplifier stage (see the Applications Information section). AD8428 Data Sheet INPUT VOLTAGE RANGE Power Supplies and Grounding The 3-op-amp architecture of the AD8428 applies gain in the first stage before removing the common-mode voltage in the difference amplifier stage. Internal nodes between the first and second stages (Node 1 and Node 2 in Figure 37) experience a combination of an amplified differential signal, a common-mode signal, and a diode drop. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited. Figure 9 shows the allowable input common-mode voltage ranges for various output voltages and supply voltages. Use a stable dc voltage to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 11 for more information. LAYOUT To ensure optimum performance of the AD8428 at the PCB level, care must be taken in the design of the board layout. The pins of the AD8428 are especially arranged to simplify board layout and to help minimize parasitic imbalance between the inputs. Place a 0.1 μF capacitor as close as possible to each supply pin. Because the length of the bypass capacitor leads is critical at high frequency, surface-mount capacitors are recommended. Parasitic inductance in the bypass ground trace works against the low impedance created by the bypass capacitor. As shown in Figure 40, a 10 μF capacitor can be used farther away from the device. For larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. In most cases, the 10 μF capacitor can be shared by other precision integrated circuits. +VS 0.1µF 10µF AD8428 +VS –FIL 2 7 OUT +FIL 3 6 REF +IN 4 5 –VS TOP VIEW (Not to Scale) +IN OUT AD8428 LOAD REF –IN Figure 39. Pinout Diagram 0.1µF Common-Mode Rejection Ratio over Frequency –VS Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To maintain high CMRR over frequency, the input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input paths (for example, for input protection) should be placed close to the in-amp inputs to minimize the interaction of the inputs with parasitic capacitance from the PCB traces. Parasitic capacitance at the filter pins can also affect CMRR over frequency. If the board design has a component at the filter pins, the component should be chosen so that the parasitic capacitance is as small as possible. 10µF 09731-045 8 09731-044 –IN 1 Figure 40. Supply Decoupling, REF, and Output Referred to Local Ground A ground plane layer is helpful to reduce undesired parasitic inductances and to minimize voltage drops with changes in current. The area of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the impedance of the path at high frequency. Large changes in currents in an inductive decoupling path or ground return create unwanted effects due to the coupling of such changes into the amplifier inputs. Because load currents flow from the supplies, the load should be connected at the same physical location as the bypass capacitor grounds. Reference Pin The output voltage of the AD8428 is developed with respect to the potential on the reference terminal. Ensure that REF is tied to the appropriate local ground. Rev. A | Page 14 of 20 Data Sheet AD8428 INPUT BIAS CURRENT RETURN PATH Input Voltages Beyond the Rails The input bias current of the AD8428 must have a return path to ground. When the source, such as a thermocouple, cannot provide a current return path, one should be created, as shown in Figure 41. If voltages beyond the rails are expected, use an external resistor in series with each input to limit current during overload conditions. The limiting resistor at each input can be computed using the following equation: CORRECT +VS RPROTECT ≥ +VS AD8428 REF –VS –VS TRANSFORMER TRANSFORMER +VS + VIN+ – I AD8428 + REF +VS RPROTECT + VIN+ – –VS VIN– – +VS 33Ω I –VS AD8428 +VS RPROTECT RPROTECT AD8428 REF +VS RPROTECT +VS AD8428 I MAX Noise sensitive applications may require a lower protection resistance. Low leakage diode clamps, such as the BAV199, can be used at the inputs to shunt current away from the AD8428 inputs and, therefore, allow smaller protection resistor values. To ensure that current flows primarily through the external protection diodes, place a small value resistor, such as a 33 Ω resistor, between the diodes and the AD8428. AD8428 REF VIN − VSUPPLY 33Ω + VIN– – –VS –VS 10MΩ –VS SIMPLE METHOD –VS THERMOCOUPLE LOW NOISE METHOD 09731-047 INCORRECT Figure 42. Protection for Voltages Beyond the Rails THERMOCOUPLE Large Differential Input Voltage at High Gain +VS C If large differential voltages at high gain are expected, use an external resistor in series with each input to limit current during overload conditions. The limiting resistor at each input can be computed using the following equation: C C R 1 fHIGH-PASS = 2πRC AD8428 REF AD8428 C REF R PROTECT ≥ –VS CAPACITIVELY COUPLED 09731-046 R –VS CAPACITIVELY COUPLED Figure 41. Creating an Input Bias Current Return Path INPUT PROTECTION Do not allow the inputs of the AD8428 to exceed the ratings stated in the Absolute Maximum Ratings section. If these ratings cannot be adhered to, add protection circuitry in front of the AD8428 to limit the maximum current into the inputs (see the IMAX section). ⎞ 1 ⎛⎜ VDIFF − 1 V × − RG ⎟ ⎟ 2 ⎜ I MAX ⎝ ⎠ Noise sensitive applications may require a lower protection resistance. Low leakage diode clamps, such as the BAV199, can be used across the AD8428 inputs to shunt current away from the inputs and, therefore, allow smaller protection resistor values. RPROTECT + I VDIFF – RPROTECT IMAX The maximum current into the AD8428 inputs, IMAX, depends on time and temperature. At room temperature, the device can withstand a current of 10 mA for at least one day. This time is cumulative over the life of the device. Rev. A | Page 15 of 20 AD8428 09731-048 +VS Figure 43. Protection for Large Differential Voltages AD8428 Data Sheet RADIO FREQUENCY INTERFERENCE (RFI) For best results, place the RFI filter network as close to the amplifier as possible. Layout is critical to ensure that RF signals are not picked up on the traces after the filter. If RF interference is too strong to be filtered, shielding is recommended. Because of its high gain and low noise properties, the AD8428 is a highly sensitive amplifier. Therefore, RF rectification can be a problem if the AD8428 is used in applications that have strong RF signal sources present. The problem is intensified if long leads or PCB traces are required to connect the amplifier to the signal source. The disturbance can appear as a dc offset voltage or as a train of pulses. CALCULATING THE NOISE OF THE INPUT STAGE High frequency signals can be filtered with a low-pass filter network at the input of the instrumentation amplifier, as shown in Figure 44. The total noise of the amplifier front end depends on much more than the specifications in this data sheet. The three main contributors to noise are as follows: +VS 0.1µF CC 1nF R CD 10nF OUT AD8428 R REF –IN 33Ω CC 1nF 0.1µF Source Resistance Noise *CHIP FERRITE BEAD. 09731-049 10µF –VS Figure 44. RFI Suppression The filter limits both the differential and common-mode bandwidth, as shown in the following equations: FilterFrequency DIFF = FilterFrequency CM = Source resistance Voltage noise of the instrumentation amplifier Current noise of the instrumentation amplifier In the following calculations, noise is referred to the input (RTI); that is, all sources of noise are calculated as if the source appeared at the amplifier input. To calculate the noise referred to the amplifier output (RTO), multiply the RTI noise by the gain of the instrumentation amplifier. +IN 33Ω L* • • • 10µF 1 2 πR(2C D + CC ) Any sensor connected to the AD8428 has some output resistance. There may also be resistance placed in series with the inputs for protection from either overvoltage or radio frequency interference. This combined resistance is labeled R1 and R2 in Figure 45. Any resistor, no matter how well made, has an intrinsic level of noise. This noise is proportional to the square root of the resistor value. At room temperature, the value is approximately equal to 4 nV/√Hz × √(resistor value in kΩ). SENSOR 1 2πRCC R1 where CD ≥ 10 CC. CD affects the differential signal, and CC affects the commonmode signal. Choose values of R and CC that minimize RFI. A mismatch between R × CC at the positive input and R × CC at the negative input degrades the CMRR of the AD8428. By using a value of CD one order of magnitude larger than CC, the effect of the mismatch is reduced, and performance is improved. R2 AD8428 09731-050 L* Note that the resistors used for the RFI filter can be the same as those used for input protection (see the Input Protection section). Figure 45. Source Resistance from Sensor and Protection Resistors For example, assuming that the combined sensor and protection resistance is 4 kΩ on the positive input and 1 kΩ on the negative input, the total noise from the input resistance is Resistors add noise; therefore, the choice of resistor and capacitor values depends on the desired trade-off between noise, input impedance at high frequencies, and RFI immunity. To achieve low noise and sufficient RFI filtering, the use of inductive ferrite beads is recommended (see Figure 44). Using inductive ferrite beads allows the value of the resistors to be reduced, which helps to minimize the noise at the input. Rev. A | Page 16 of 20 (4 × 4 ) + (4 × 1 ) 2 2 = 64 + 16 = 8.9 nV/ Hz Data Sheet AD8428 Voltage Noise of the Instrumentation Amplifier Total Noise Density Calculation Unlike other instrumentation amplifiers in which an external resistor is used to set the gain, the voltage noise specification of the AD8428 already includes the input noise, output noise, and the RG resistor noise. To determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current noise contribution by the sum of squares method. Current Noise of the Instrumentation Amplifier The contribution of current noise to the input stage in nV/√Hz is calculated by multiplying the source resistance in kΩ by the specified current noise of the instrumentation amplifier in pA/√Hz. For example, if the R1 source resistance in Figure 45 is 4 kΩ and the R2 source resistance is 1 kΩ, the total noise, referred to input, is For example, if the R1 source resistance in Figure 45 is 4 kΩ and the R2 source resistance is 1 kΩ, the total effect from the current noise is calculated as follows: (4 × 1.5) + (1 × 1.5) 2 2 = 36 + 2.25 = 6.2 nV/ Hz Rev. A | Page 17 of 20 8.9 2 + 1.52 + 6.2 2 = 11.0 nV/ Hz AD8428 Data Sheet APPLICATIONS INFORMATION The classic 3-op-amp topology used for instrumentation amplifiers typically places all the gain in the first stage and subtracts the common-mode signals only in the second stage. When operated at high gain, any amplifier is sensitive to large interfering signals that can saturate it, thus making it impossible to recover the signal of interest. The AD8428 splits the total gain of 2000 into two stages: 200 in the preamplification stage and 10 in the subtractor stage. Reducing the gain of the first stage helps to increase the common-mode range vs. differential signal range by avoiding saturation of the preamps. Because this resistor appears inside the feedback of the subtractor stage, it modifies the gain of the subtractor as well. The total gain formula is a simplified version of the transfer function equation (Equation 1). G= RG = 6000 × G 2000 − G The AD8428 defaults to G = 2000 when no gain resistor is used. When setting the amplifier to a different gain, the absolute gain accuracy is only 10%. In addition, the temperature mismatch of the external gain resistor increases the gain drift of the instrumentation amplifier. Gain error and gain drift are at a guaranteed minimum when a gain resistor is not used. For applications that require accuracy at different gains, low noise, and wide bandwidth, the AD8429 should be considered. 10 5 SINGLE STAGE GAIN, G = 2000 AD8428 –5 –10 Low-Pass Filter –15 –15 To help limit undesired differential signals, a first-order, low-pass filter can be implemented by adding a capacitor across the filter terminals of the AD8428, as shown in Figure 47. –5 0 5 10 15 OUTPUT VOLTAGE (V) Figure 46. AD8428 vs. Single Stage Gain Topology, G = 2000 +IN In addition, filtering between stages can help to attenuate signals before they reach the second amplification stage. This filtering helps to prevent saturation of the second stage amplifier as long as the signals are located in frequencies other than the signal of interest. EFFECT OF PASSIVE NETWORK ACROSS THE FILTER TERMINALS The AD8428 filter terminals allow access between the two amplification stages. Adding a passive network between the two terminals can shape the transfer function over the frequency of the amplifier. The general expression for the transfer function is represented by Equation 1. G(s) = 2000 × Z(s) Z(s) + 6000 (1) where Z(s) is the frequency dependent impedance of the network across the filter terminals. CIRCUITS USING THE FILTER TERMINALS Setting the Amplifier to Different Gains In its simplest form, the transfer function equation (Equation 1) implies that the AD8428 can be configured for gains lower than 2000. This can be achieved by attaching a resistor across the filter pins. Unlike the gain configuration of traditional instrumentation amplifiers, this resistor attenuates the signal that was previously amplified by the initial gain of 200. + +FIL CF AD8428 –FIL –IN – OUT 09731-146 –10 09731-246 INPUT COMMON-MODE VOLTAGE (V) (2) RG + 6000 The RG unit is in ohms. The resistor value required to obtain the desired gain can be calculated using the following formula: 15 0 2000 × RG Figure 47. Differential Low-Pass Filter This single-pole filter limits the signal bandwidth, as shown in the following equation: fC = 1 2π(6 kΩ)C F The 6 kΩ factor comes from the internal resistor values. The tolerance of these resistors is 10%; therefore, using capacitors with a tolerance better than 5% does not provide a significant improvement on the absolute tolerance of the cutoff frequency. Limiting the bandwidth of the amplifier also helps to minimize the amount of out-of-band noise present at the output. Note that filtering common-mode signals by adding a capacitor on each filter terminal to ground degrades the performance of the amplifier. This practice is generally discouraged because it degrades CMRR performance. In addition, filtering commonmode signals has little effect on preventing the saturation of the internal nodes. On the contrary, the load added to the preamplifiers causes them to saturate with even smaller common-mode signals. Rev. A | Page 18 of 20 Data Sheet AD8428 Notch Filter In cases where the frequency of the interfering signal is well known, a notch filter can be implemented to help minimize the impact of the known signal on the measurement. The filter can be realized by adding a series LC network between the filter pins, as shown in Figure 48. 72 + +FIL –3dB Figure 48. Notch Filter Example The inductor and capacitor form a resonant circuit that rejects frequencies near the notch. The center frequency can be calculated using the following equation: fN = 1 6000 54 48 42 36 0.01f N 0.1fN fN 10fN 100f N FREQUENCY (Hz) LF CF Figure 49. Notch Filter Attenuation with Q = 0.1 and Q = 1 Around the Center Frequency The accuracy of the center frequency, fN, depends only on the tolerance of the capacitor and inductor values, not on the value of the internal resistors. However, the Q of the circuit depends on both the tolerance of the external components and the absolute tolerance of the internal resistors, which is typically 10%. The Q factor is a filter parameter that indicates how narrow the notch filter is. It is defined as follows: Q = Q = 0.1 –20dB 1 2π L F C F The Q factor of the filter is given by the following equation: Q= 60 09731-249 – MAGNITUDE (dB) –FIL CF Q=1 66 OUT 09731-147 AD8428 fN fB − fA The maximum attenuation that can be achieved with a notch filter is at its center frequency, fN. This maximum attenuation (or depth of the notch) depends on the equivalent series resistance of the inductor and capacitor at the center frequency. Choosing components with high quality factors improves the rejection at the filter’s center frequency. For information about calculating the maximum allowed series resistance at the frequency of interest to obtain the desired attenuation, see the Setting the Amplifier to Different Gains section. Extracting the Common-Mode Voltage of the Input where fA and fB are the frequencies at which there is −3 dB attenuation on each side of the notch. This equation indicates that the higher the Q, the narrower the notch—that is, high values of Q increase the selectivity of the notch. In other words, although high values of Q reduce the effect of the notch on the amplitude and phase in neighboring frequencies, the ability to reject the undesired frequency may also be reduced due to mismatch between it and the actual center frequency. This mismatch can be caused by frequency variations on the affecting source and the tolerance of the filter inductor and capacitor values. In contrast, low values of Q work better to ensure that the interfering frequency is attenuated, but these low values also affect the signal of interest if it is located close to the center frequency of the notch. For example, if the goal is to attenuate the interfering signal by 20 dB, a large Q value reduces the frequency range where the notch is effective, as shown in Figure 49. The common-mode signal present at the input terminals can be extracted by inserting two resistors between the filter terminals and tapping from the center, as shown in Figure 50. The commonmode voltage, VCM, is the average of the voltages present at the two inputs minus a 0.6 V drop. + +IN R R VCM –IN +FIL AD8428 –FIL – OUT 09731-148 LF In contrast, a small Q value increases the range for the same attenuation, which relaxes the tolerance requirements between the inductor and capacitor and the frequency uncertainty of the undesired signal. However, the lower Q value has a significant effect on signal bandwidth one decade before the notch frequency. Figure 50. Extracting the Common-Mode Voltage Use resistor values that are high enough to minimize the impact on gain accuracy. For example, resistor values of 2 MΩ introduce an additional gain error of less than 0.2%. For information about the impact of these resistors on the gain of the amplifier, see the Effect of Passive Network Across the Filter Terminals section. Rev. A | Page 19 of 20 AD8428 Data Sheet OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 4.00 (0.1574) 3.80 (0.1497) Figure 51. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 AD8428ARZ AD8428ARZ-RL AD8428BRZ AD8428BRZ-RL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N, 13” Tape and Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13” Tape and Reel Z = RoHS Compliant Part. ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09731-0-4/12(A) Rev. A | Page 20 of 20 Package Option R-8 R-8 R-8 R-8