AD AD9886KS-100

a
FEATURES
Analog Interface
140 MSPS Maximum Conversion Rate
330 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamp for YUV Applications
Analog Interface for
Flat Panel Displays
AD9886
FUNCTIONAL BLOCK DIAGRAM
AD9886
ANALOG INTERFACE
8
RIN
CLAMP
A/D
GIN
CLAMP
A/D
BIN
CLAMP
A/D
8
8
8
8
8
8
GENERAL DESCRIPTION
The AD9886 is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full-power analog bandwidth of 330 MHz
supports resolutions up to SXGA (1280 × 1024 at 75 Hz).
For ease of design and to minimize cost, the AD9886 is a fully
integrated interface solution for FPDs. The AD9886 includes a
140 MHz triple ADC with internal 1.25 V reference, PLL to
generate a pixel clock from an HSYNC, and programmable
gain, offset, and clamp control. The user provides only a 3.3 V
power supply, analog input, and an HSYNC signal. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9886’s on-chip PLL generates a pixel clock from an
HSYNC. Pixel clock output frequencies range from 12 MHz to
140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of HSYNC. A sampling phase
adjustment is provided. Data, HSYNC and Clock output phase
relationships are maintained. The PLL can be disabled and an
external clock input provided as the pixel clock. The AD9886
also offers full sync processing for composite sync and sync-ongreen applications.
CLAMP
CKINV
CKEXT
8
2
HSYNC
COAST
8
ROUTB
GOUTA
GOUTB
BOUTA
BOUTB
DATACK
HSOUT
VSOUT
SYNC
PROCESSING
AND CLOCK
GENERATION
SOGOUT
REF
FILT
ROUTA
REFOUT
REFIN
SCL
SDA
A1
SERIAL REGISTER AND
POWER MANAGEMENT
A0
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9886–SPECIFICATIONS (V = 3.3 V, V
D
Parameter
Temp
Test
Level
DD
Min
AD9886KS-100
Typ
Max
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
± 0.5
25°C
Full
25°C
Full
Full
I
VI
I
VI
VI
Full
Full
25°C
25°C
Full
Full
Full
Full
VI
VI
V
IV
IV
VI
VI
VI
44
1.20
± 0.5
AD9886KS-140
Typ
Max
8
± 0.5
+1.15/–1.0
+1.15/–1.0
± 1.4
± 1.75
± 0.5
Guaranteed
0.5
135
Full
VI
Full
V
Sampling Phase Tempco
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
IV
IV
IV
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (VIH)
Input Current, Low (V IL)
Input Capacitance
Full
Full
Full
Full
25°C
VI
VI
IV
IV
V
2.5
Full
Full
VI
VI
VD – 0.1
Full
IV
45
Bits
+1.25/–1.0
+1.25/–1.0
± 1.65
± 2.5
LSB
LSB
LSB
LSB
0.5
V p–p
V p–p
ppm/°C
µA
µA
mV
% FS
% FS
1.0
150
50
1
1
50
8.0
56
44
1.25
1.30
1.20
7
50
1
1
50
8.0
56
1.25
1.30
7
± 50
± 50
100
110
400
10
+2.0
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
140
12
7002
10002
110
400
15
12
7003
10003
15
0.8
–1.0
1.0
3
3
VD – 0.1
0.1
50
Binary
–2–
55
45
50
Binary
MSPS
MSPS
ns
µs
µs
µs
µs
µs
µs
µs
µs
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
2.5
0.8
–1.0
1.0
V
ppm/°C
140
10
+2.0
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
100
Unit
Guaranteed
1.0
Temperature Coefficient
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (V OL)
Duty Cycle
DATACK, DATACK
Output Coding
Min
8
REFERENCE OUTPUT
Output Voltage
SWITCHING PERFORMANCE 1
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew, tSKEW
tBUFF
tSTAH
tDHO
tDAL
tDAH
tDSU
tSTASU
tSTOSU
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
= 3.3 V, ADC Clock = Maximum Conversion Rate.)
V
V
µA
µA
pF
0.1
V
V
55
%
REV. 0
AD9886
Parameter
Temp
Test
Level
AD9886KS-100
Min
Typ
Max
AD9886KS-140
Min
Typ
Max
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
ID Supply Current (V D)
IDD Supply Current (VDD)4
IPVD Supply Current (PVD)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
Full
Full
Full
25°C
25°C
25°C
Full
Full
Full
IV
IV
IV
V
V
V
VI
VI
VI
3.0
2.2
3.0
3.0
2.2
3.0
25°C
25°C
25°C
25°C
Full
V
V
V
V
V
330
2
1.5
46
45
330
2
1.5
46
45
MHz
ns
ns
dB
dB
Full
V
60
60
dBc
V
20
20
°C/W
V
40
40
°C/W
3.3
3.3
3.3
140
34
15
564
13
43
3.6
3.6
3.6
850
25
82.5
3.3
3.3
3.3
155
48
16
715
13
43
3.6
3.6
3.6
850
25
82.5
Unit
V
V
V
mA
mA
mA
mW
mA
mW
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)5
(Without Harmonics)
fIN = 40.7 MHz
Crosstalk
THERMAL CHARACTERISTICS
θJC Junction-to-Case
Thermal Resistance
θJA Junction-to-Ambient
Thermal Resistance
NOTES
1
Drive Strength = 11.
2
VCO Range = 01, Charge Pump Current = 001, PLL Divider = 1693.
3
VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1600.
4
DEMUX = 1, DATACK and DATACK Load = 10 pF, Data Load = 5 pF.
5
Using external pixel clock.
Specifications subject to change without notice.
REV. 0
–3–
AD9886
EXPLANATION OF TEST LEVELS
Test Level
ABSOLUTE MAXIMUM RATINGS*
VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . –25°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C
I
100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and
characterization testing.
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD9886KS-140
AD9886KS-100
AD9886/PCB
0°C to 70°C
0°C to 70°C
25°C
Plastic Quad Flatpack
Plastic Quad Flatpack
Evaluation Board
S-160
S-160
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9886 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD9886
121 GND
122 GND
123 VD
126 REFOUT
125 REFIN
124 VD
129 SCANIN
128 GND
127 VD
130 GND
131 GND
132 VDD
133 GND
134 DATACLK
136 SCDT
135 DATACLKB
137 NC
139 HSOUT
138 VSOUT
140 SOGOUT
141 VDD
142 GND
143 RED A<7>
144 RED A<6>
148 RED A<2>
147 RED A<3>
146 RED A<4>
145 RED A<5>
149 RED A<1>
150 RED A<0>
151 VDD
152 GND
153 RED B<7>
154 RED B<6>
155 RED B<5>
156 RED B<4>
1
120
PIN 1
IDENTIFIER
2
3
4
119
118
117
5
6
116
7
114
8
113
9
112
10
111
110
115
11
12
13
109
14
107
15
106
16
105
17
104
103
108
18
19
102
20
101
AD9886
21
22
100
TOP VIEW
(Not to Scale)
23
99
24
98
97
25
96
26
95
27
94
28
93
29
30
31
92
32
33
89
88
34
87
35
86
36
85
37
84
38
83
39
40
82
91
90
79
80
78
77
75
76
74
73
72
71
70
69
68
67
65
66
64
63
61
62
60
59
58
56
57
55
54
53
52
51
50
49
47
48
46
45
44
43
GND
GND
VDD
GND
SCANOUT
NC
NC
NC
NC
SCANCLK
VD
GND
NC
VD
VD
NC
NC
GND
NC
NC
GND
NC
NC
GND
NC
NC
VD
VD
GND
VD
NC
NC
NC
GND
PVD
GND
PVD
FILT
PVD
GND
42
81
41
VDD
GND
GREEN A<7>
GREEN A<6>
GREEN A<5>
GREEN A<4>
GREEN A<3>
GREEN A<2>
GREEN A<1>
GREEN A<0>
VDD
GND
GREEN B<7>
GREEN B<6>
GREEN B<5>
GREEN B<4>
GREEN B<3>
GREEN B<2>
GREEN B<1>
GREEN B<0>
VDD
GND
BLUE A<7>
BLUE A<6>
BLUE A<5>
BLUE A<4>
BLUE A<3>
BLUE A<2>
BLUE A<1>
BLUE A<0>
VDD
GND
BLUE B<7>
BLUE B<6>
BLUE B<5>
BLUE B<4>
BLUE B<3>
BLUE B<2>
BLUE B<1>
BLUE B<0>
157 RED B<3>
160 RED B<0>
159 RED B<1>
158 RED B<2>
PIN CONFIGURATION
NC = NO CONNECT
REV. 0
–5–
RMIDSCV
RAIN
RCLAMPV
VD
GND
VD
VD
GND
GND
GMIDSCV
GAIN
GCLAMPV
SOGIN
VD
GND
VD
VD
GND
GND
BMIDSCV
BAIN
BCLAMPV
VD
GND
VD
GND
CKINV
CLAMP
SDA
SCL
A0
A1
PVD
PVD
GND
GND
COAST
CKEXT
HSYNC
VSYNC
AD9886
Table I. Complete Pinout List
Pin
Pin
Name
Function
Value
Pin
Number
Analog Video
Inputs
RAIN
GAIN
BAIN
Analog Input for Converter R
Analog Input for Converter G
Analog Input for Converter B
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
119
110
100
External
Sync/Clock
Inputs
HSYNC
VSYNC
SOGIN
CLAMP
COAST
CKEXT
CKINV
Horizontal SYNC Input
Vertical SYNC Input
Input for Sync-on-Green
Clamp Input (External CLAMP Signal)
PLL COAST Signal Input
External Pixel Clock Input (to Bypass the PLL) or 10 kΩ to VDD
ADC Sampling Clock Invert
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
82
81
108
93
84
83
94
Sync Outputs
HSOUT
VSOUT
SOGOUT
HSYNC Output Clock (Phase-Aligned with DATACK)
VSYNC Output Clock (Phase-Aligned with DATACK)
Sync on Green Slicer Output
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
139
138
140
Voltage
Reference
REFOUT
REFIN
Internal Reference Output (Bypass with 0.1 µF to Ground)
Reference Input (1.25 V ± 10%)
1.25 V
1.25 ± 10%
126
125
Clamp Voltages
RMIDSCV
RCLAMPV
GMIDSCV
GCLAMPV
BMIDSCV
BCLAMPV
Red Channel Midscale Clamp Voltage Output
Red Channel Midscale Clamp Voltage Output
Green Channel Midscale Clamp Voltage Output
Green Channel Midscale Clamp Voltage Output
Blue Channel Midscale Clamp Voltage Output
Blue Channel Midscale Clamp Voltage Output
PLL Filter
FILT
Connection for External Filter Components for Internal PLL
Power Supply
VD
VDD
PVD
GND
Analog Power Supply
Output Power Supply
PLL Power Supply
Ground
3.3 V ± 10%
3.3 V ± 10%
3.3 V ± 10%
0V
Serial Port
(2-Wire
Serial Interface)
SDA
SCL
A0
A1
Serial Port Data I/O
Serial Port Data Clock (100 kHz max)
Serial Port Address Input 1
Serial Port Address Input 2
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
92
91
90
89
Data Outputs
Red B[7:0]
Green B[7:0]
Blue B[7:0]
Red A[7:0]
Green A[7:0]
Blue A[7:0]
Port B/Odd Outputs of Converter “Red,” Bit 7 Is the MSB
Port B/Odd Outputs of Converter “Green,” Bit 7 Is the MSB
Port B/Odd Outputs of Converter “Blue,” Bit 7 Is the MSB
Port A/Even Outputs of Converter “Red,” Bit 7 Is the MSB
Port A/Even Outputs of Converter “Green,” Bit 7 Is the MSB
Port A/Even Outputs of Converter “Blue,” Bit 7 Is the MSB
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
153–160
13–20
33–40
143–150
3–10
23–30
Data Clock
Outputs
DATACK
DATACK
Data Output Clock for the Analog and Digital Interface
Data Output Clock Complement for the Analog Interface Only
3.3 V CMOS
3.3 V CMOS
134
135
Type
0.0 V to 0.75 V
0.0 V to 0.75 V
0.0 V to 0.75 V
120
118
111
109
101
99
78
Sync Detect
SCDT
Sync Detect Output
3.3 V CMOS
136
Scan Function
SCANIN
SCANOUT
SCANCLK
Input for SCAN Function
Output for SCAN Function
Clock for SCAN Function
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
129
45
50
No Connect
NC
These Pins Should be Left Unconnected
–6–
46–49, 53,
56, 57, 59,
60, 62, 63,
65, 66,
71–73, 137
REV. 0
AD9886
This logic input may be used to define the
time during which the input signal is clamped
to the reference dc level (ground for RGB or
midscale for YUV). It should be exercised
when the reference dc level is known to be
present on the analog input channels, typically during the back porch of the graphics
signal. The CLAMP pin is enabled by setting
control bit EXTCLMP to 1 (the default
power-up is 0). When disabled, this pin is
ignored and the clamp timing is determined
internally by counting a delay and duration
from the trailing edge of the HSYNC input.
The logic sense of this pin is controlled by
CLAMPOL. When not used, this pin must be
grounded and EXTCLMP programmed to 0.
PIN FUNCTION DETAIL
Inputs
RAIN
Analog Input for RED Channel
GAIN
Analog Input for GREEN Channel
BAIN
Analog Input for BLUE Channel
High-impedance inputs that accept the RED,
GREEN, and BLUE channel graphics signals,
respectively. (The three channels are identical and can be used for any colors, but colors
are assigned for convenient reference.)
They accommodate input signals ranging
from 0.5 V to 1.0 V full scale. Signals should
be ac-coupled to these pins to support clamp
operation.
HSYNC
Horizontal Sync Input
COAST
This input receives a logic signal that establishes the horizontal timing reference and
provides the frequency reference for pixel
clock generation.
This input may be used to cause the pixel
clock generator to stop synchronizing with
HSYNC and continue producing a clock at
its current frequency and phase. This is useful
when processing signals from sources that fail
to produce horizontal sync pulses when in the
vertical interval. The COAST signal is generally not required for PC-generated signals.
The logic sense of this pin is controlled by
serial register 0Fh Bit 7 (HSYNC Polarity).
Only the leading edge of HSYNC is active,
the trailing edge is ignored. When HSYNC
Polarity = 0, the falling edge of HSYNC is
used. When HSYNC Polarity = 1, the rising
edge is active.
The logic sense of this pin is controlled by
COAST Polarity.
When not used, this pin may be grounded
and COAST Polarity programmed to 1, or tied
HIGH (to VD through a 10 kΩ resistor) and
COAST Polarity programmed to 0. COAST
Polarity defaults to 1 at power-up.
The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold
of 1.5 V.
Electrostatic Discharge (ESD) protection
diodes will conduct heavily if this pin is driven
more than 0.5 V above the maximum tolerance voltage (3.3 V), or more than 0.5 V
below ground.
VSYNC
CKEXT
Vertical Sync Input
It is enabled by programming EXTCLK to 1.
When an external clock is used, all other internal functions operate normally. When unused,
this pin should be tied through a 10 kΩ resistor
to GROUND, and EXTCLK programmed to
0. The clock phase adjustment still operates
when an external clock source is used.
Sync-on-Green Input
This input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high-speed comparator with an internally generated threshold, which is set to 0.15 V above
the negative peak of the input signal.
CLAMP
REV. 0
External Clock Input (Optional)
This pin may be used to provide an external
clock to the AD9886, in place of the clock
internally generated from HSYNC.
This is the input for vertical sync.
SOGIN
Clock Generator Coast Input (Optional)
CKINV
Sampling Clock Inversion (Optional)
When connected to an ac-coupled graphics
signal with embedded sync, it will produce a
noninverting digital output on SOGOUT.
(This is usually a composite sync signal,
containing both vertical and horizontal sync
information that must be separated before
passing the horizontal sync signal to HSYNC).
This pin may be used to invert the pixel
sampling clock, which has the effect of
shifting the sampling phase 180°. This is in
support of Alternate Pixel Sampling mode,
wherein higher-frequency input signals (up
to 280 Mpps) may be captured by first sampling the odd pixels, then capturing the even
pixels on the subsequent frame.
When not used, this input should be left
unconnected. For more details on this function and how it should be configured, refer to
the Sync on Green section.
This pin should be exercised only during
blanking intervals (typically vertical blanking)
as it may produce several samples of corrupted
data during the phase shift.
External Clamp Input
CKINV should be grounded when not used.
–7–
AD9886
Outputs
DRA7-0
Data Output, Red Channel, Port A
DRB7-0
Data Output, Red Channel, Port B
DGA7-0
Data Output, Green Channel, Port A
DGB7-0
Data Output, Green Channel, Port B
DBA7-0
Data Output, Blue Channel, Port A
DBB7-0
Data Output, Blue Channel, Port B
HSOUT
A reconstructed and phase-aligned version of
the Hsync input. Both the polarity and duration of this output can be programmed via
serial bus registers.
By maintaining alignment with DATACK,
DATACK, and Data, data timing with
respect to horizontal sync can always be
determined.
These are the main data outputs. Bit 7 is
the MSB.
SOGOUT
Each channel has two ports. When the part is
operated in single-channel mode (DEMUX =
0), all data are presented to Port A, and Port B
is placed in a high-impedance state.
(Note: Besides slicing off SOG, the output
from this pin receives no additional processing on the AD9886. VSYNC separation is
performed via the sync separator.)
REFOUT
The delay from pixel sampling time to output
is fixed. When the sampling time is changed
by adjusting the PHASE register, the output
timing is shifted as well. The DATACK,
DATACK, and HSOUT outputs are also
moved, so the timing relationship among the
signals is maintained.
DATACK
Data Output Clock Complement
Internal Reference Output
Output from the internal 1.25 V bandgap
reference. This output is intended to drive
relatively light loads. It can drive the AD9886
Reference Input directly, but should be externally buffered if it is used to drive other loads
as well.
In dual channel mode, the first pixel after
HSYNC is routed to Port A. The second
pixel goes to Port B, the third to A, etc. This
can be reversed by setting OUTPHASE to 1.
Data Output Clock
Sync-On-Green Slicer Output
This pin can be programmed to output
either the output from the Sync-On-Green
slicer comparator or an unprocessed but
delayed version of the HSYNC input. See
the Sync Block Diagram to view how this
pin is connected.
Programming DEMUX to 1 established dualchannel mode, wherein alternate pixels are
presented to Port A and Port B of each channel. These will appear simultaneously, two
pixels presented at the time of every second
input pixel, when PAR is set to 1 (parallel
mode). When PAR = 0, pixel data appear
alternately on the two ports, one new sample
with each incoming pixel (interleaved mode).
DATACK
Horizontal Sync Output
The absolute accuracy of this output is ± 4%,
and the temperature coefficient is ± 50 ppm,
which is adequate for most AD9886 applications. If higher accuracy is required, an
external reference may be employed instead.
If an external reference is used, connect this
pin to ground through a 0.1 µF capacitor.
REFIN
Reference Input
The reference input accepts the master reference voltage for all AD9886 internal circuitry
(1.25 V ± 10%). It may be driven directly by
the REFOUT pin. Its high impedance presents a very light load to the reference source.
Differential data clock output signals to be
used to strobe the output data and HSOUT
into external logic.
They are produced by the internal clock generator and are synchronous with the internal
pixel sampling clock.
This pin should always be bypassed to Ground
with a 0.1 µF capacitor.
When the AD9886 is operated in singlechannel mode, the output frequency is equal
to the pixel sampling frequency. When operating in dual channel mode, the clock frequency
is one-half the pixel frequency, as is the output
data frequency.
FILT
External Filter Connection
For proper operation, the pixel clock generator PLL requires an external filter. Connect
the filter shown Figure 7 to this pin. For
optimal performance, minimize noise and
parasitics on this node.
When the sampling time is changed by adjusting the PHASE register, the output timing
is shifted as well. The Data, DATACK,
DATACK, and HSOUT outputs are all
moved, so the timing relationship among the
signals is maintained.
Either or both signals may be used, depending on the timing mode and interface design
employed.
–8–
REV. 0
AD9886
Power Supply
VD
Serial Port (Two-Wire)
Main Power Supply
These pins supply power to the main elements of the circuit. It should be as quiet and
filtered as possible.
VDD
Digital Output Power Supply
A large number of output pins (up to 52)
switching at high speed (up to 140 MHz)
generates a lot of power supply transients
(noise). These supply pins are identified
separately from the VD pins so special care
can be taken to minimize output noise transferred into the sensitive analog circuitry.
If the AD9886 is interfacing with lowervoltage logic, VDD may be connected to a
lower supply voltage (as low as 2.5 V) for
compatibility.
PVD
SCANIN
Data Input for SCAN Function
Data can be loaded serially into the 48-bit
SCAN register through this pin, clocking it in
with the SCANCLK pin. It then comes out of
the 48 data outputs in parallel. This function
is useful for loading known data into a graphics controller chip for testing purposes.
SCANOUT
Data Output for SCAN Function
The data in the 48-bit SCAN register can be
read through this pin. Data is read on a FIFO
basis and is clocked via the SCANCLK pin.
SCANCLK
Data Clock for SCAN Function
This pin clocks the data through the SCAN
register. It controls both data input and
data output.
Ground
The ground return for all circuitry on chip.
It is recommended that the AD9886 be
assembled on a single solid ground plane,
with careful attention to ground current paths.
REV. 0
Serial Port Data I/O
Serial Port Data Clock
Serial Port Address Input 1
Serial Port Address Input 2
For a full description of the 2-wire serial register and how it works, refer to the Control
Register section.
SCAN Function
Clock Generator Power Supply
The most sensitive portion of the AD9886 is
the clock generation circuitry. These pins
provide power to the clock PLL and help the
user design for optimal performance. The
designer should provide “quiet,” noise-free
power to these pins.
GND
SDA
SCL
A0
A1
–9–
AD9886
DESIGN GUIDE
General Description
HSYNC, VSYNC Inputs
The AD9886 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The circuit is ideal for providing a computer
interface for HDTV monitors or as the front end to highperformance video scan converters.
Implemented in a high-performance CMOS process, the interface can capture signals with pixel rates of up to 140 MHz and
with an Alternate Pixel Sampling mode, up to 280 MHz.
The AD9886 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control,
and output data formatting. All controls are programmable via
a 2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less sensitive to the physical and electrical environment.
With a typical power dissipation of less than 750 mW and an
operating temperature range of 0°C to 70°C, the device requires
no special environmental considerations.
Input Signal Handling
The AD9886 has three high-impedance analog input pins for
the Red, Green, and Blue channels. They will accommodate
signals ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or via BNC connectors.
The AD9886 should be located as close as practical to the
input connector. Signals should be routed via matched-impedance traces (normally 75 Ω) to the IC input pins.
At that point the signal should be resistively terminated (75 Ω
to the signal ground return) and capacitively coupled to the
AD9886 inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The ultrawide bandwidth inputs of the AD9886
(330 MHz) can track the input signal continuously as it moves
from one pixel level to the next, and digitize the pixel during a
long, flat pixel time. In many systems, however, there are mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. It has been shown that a small inductor in series
with the input is effective in rolling off the input bandwidth
slightly, and providing a high quality signal over a wider range
of conditions. Using a Fair-Rite #2508051217Z0 High-Speed
Signal Chip Bead inductor in the circuit of Figure 1 gives good
results in most applications.
47nF
RGB
INPUT
RAIN
GAIN
BAIN
75⍀
The AD9886 takes a horizontal sync signal, which is used to
generate the pixel clock and clamp timing. It is possible to operate the AD9886 without applying HSYNC (using an external
clock, external clamp, and single port output mode) but a number
of features of the chip will be unavailable, so it is recommended
that HSYNC be provided. This can be either a sync signal
directly from the graphics source, or a preprocessed TTL or
CMOS level signal.
The HSYNC input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no termination is required or desired.
Serial Control Port
The serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150 Ω series resistors placed between the pull-up resistors and
the input pins.
Output Signal Handling
The digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as
low as 2.5 V for compatibility with other 2.5 V logic.
Clamping
RGB Clamping
To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board A/D
converters.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. Then white is at approximately
1.0 V. Some common RGB line amplifier boxes use emitterfollower buffers to split signals and increase drive capability.
This introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9886.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced which results in the A/D converters
producing a black output (code 00h) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
In most graphics systems, black is transmitted between active
video lines. Going back to CRT displays, when the electron
beam has completed writing a horizontal line on the screen (at
the right side), the beam is quickly deflected to the left side of
the screen (called horizontal retrace) and a black signal is provided to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(HSYNC) is produced briefly to signal the CRT that it is time
to begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of HSYNC. Fortunately, there is virtually
always a period following HSYNC called the back porch where
a good black reference is provided. This is the time when clamping should be done.
Figure 1. Analog Input Interface Circuit
–10–
REV. 0
AD9886
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time (with EXTCLMP = 1).
The polarity of this signal is set by the Clamp Polarity bit.
A simpler method of clamp timing employs the AD9886 internal clamp timing generator. The Clamp Placement register is
programmed with the number of pixel times that should pass
after the trailing edge of HSYNC before clamping starts. A
second register (Clamp Duration) sets the duration of the
clamp. These are both 8-bit values, providing considerable
flexibility in clamp generation. The clamp timing is referenced
to the trailing edge of HSYNC because, although HSYNC
duration can vary widely, the back porch (black reference)
always follows HSYNC. A good starting point for establishing
clamping is to set the clamp placement to 08h (providing eight
pixel periods for the graphics signal to stabilize after sync) and
set the clamp duration to 14h (giving the clamp 20 pixel periods
to reestablish the black reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capacitor affects the performance of the clamp. If it is too small, there
will be a significant amplitude change during a horizontal line
time (between clamping intervals). If the capacitor is too large,
it will take excessively long for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within 1/2 LSB in 10 lines with a clamp duration of 20 pixel
periods on a 60 Hz SXGA signal.
YUV Clamping
YUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be at
the midpoint of the video signal rather than the bottom. For
these signals it can be necessary to clamp to the midscale range
of the A/D converter range (10h) rather than bottom of the A/D
converter range (00h).
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the series bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in Register 0Fh and are Bits 0–2.
RMIDSCV
RCLAMPV
0.1␮F
GMIDSCV
GCLAMPV
0.1␮F
BMIDSCV
BCLAMPV
0.1␮F
Figure 2. Typical Clamp Configuration for RBG/YUV
Applications
Gain and Offset Control
The AD9886 can accommodate input signals with inputs ranging from 0.5 V to 1.0 V full scale. The full-scale range is set in
three 8-bit registers (Red Gain, Green Gain, and Blue Gain).
Note that increasing the gain setting results in an image with
less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (Red Offset,
Green Offset, Blue Offset) provide independent settings for
each channel.
The offset controls provide a ± 63 LSB adjustment range. This
range is connected with the full-scale range, so if the input range
is doubled (from 0.5 V to 1.0 V) then the offset step size is also
doubled (from 2 mV per step to 4 mV per step).
Figure 3 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional
to the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same amount
as the zero-scale level.
OFFSET = 7Fh
OFFSET = 3Fh
1.0V
INPUT RANGE
The midscale reference voltage that each A/D converter clamps
to is provided independently on the RMIDSCV, GMIDSCV, and
BMIDSCV pins. Each converter must have its own midscale reference because both offset adjustment and gain adjustment for
each converter will affect the dc level of midscale.
During clamping, each A/D converter is clamped to its respective midscale reference input. These inputs are pins RCLAMPV,
GCLAMPV, and BCLAMPV for the red, green, and blue converters
respectively. The typical connections for both RGB and YUV
clamping are shown below in Figure 2. Note: if midscale clamping is not required, all of the midscale voltage outputs should
still be connected to ground through a 0.1 µF capacitor.
REV. 0
OFFSET = 00h
0.5V
OFFSET = 7Fh
OFFSET = 3Fh
0.0V
OFFSET = 00h
00h
FFh
GAIN
Figure 3. Gain and Offset Control
–11–
AD9886
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
Sync-on-Green
The Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level from the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level to
~150 mV above the negative peak. The Sync-on-Green input
must be ac-coupled to the green analog input through its own
capacitor as shown in Figure 4. The value of the capacitor must
be 1 nF ± 20%. If Sync-on-Green is not used, this connection is
not required. (Note: The Sync-on-Green signal is always negative polarity.)
Considerable care has been taken in the design of the AD9886’s
clock generation circuit to minimize jitter. As indicated in Figure 6, the clock jitter of the AD9886 is less than 5% of the total
pixel time in all operating modes, making the reduction in the
valid sampling time due to jitter negligible.
14
47nF
12
PIXEL CLOCK JITTER (p-p) – %
RAIN
47nF
BAIN
47nF
GAIN
1nF
SOG
Figure 4. Typical Clamp Configuration for RGB/YUV
Applications
8
6
4
2
Clock Generation
A Phase Locked Loop (PLL) is employed to generate the pixel
clock. In this PLL, the Hsync input provides a reference frequency. A Voltage Controlled Oscillator (VCO) generates a
much higher pixel clock frequency. This pixel clock is divided
by the PLL divide value (Registers 01H and 02H) and phase
compared with the Hsync input. Any error is used to shift the
VCO frequency and maintain lock between the two signals.
0
INVALID SAMPLE TIMES
Figure 5. Pixel Sampling Times
0
31.5 36.0 36.0 50.0 56.25 44.9 75.0 85.5
FREQUENCY – MHz
135.0
Figure 6. Pixel Clock Jitter vs. Frequency
The stability of this clock is a very important element in providing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (see Figure 5). The ratio of the slewing time
to the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate. Clearly,
if the dynamic characteristics of the system remain fixed, the
slewing and settling time is likewise fixed. This time must be
subtracted from the total pixel period, leaving the stable period.
At higher pixel frequencies, the total cycle time is shorter, and
the stable pixel time becomes shorter as well.
PIXEL CLOCK
10
The PLL characteristics are determined by the loop filter
design, by the PLL charge pump current and by the VCO range
setting. The loop filter design is illustrated in Figure 7. Recommended settings of VCO range and charge pump current for
VESA standard display modes are listed in Table IV.
PVD
CP0.0039␮F
0.039␮F CZ
3.3k⍀ RZ
FILT
Figure 7. PLL Loop Filter Detail
Four programmable registers are provided to optimize the performance of the PLL. These registers are:
1. The 12-Bit Divisor Register. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock frequencies in the range of 12 MHz to 140 MHz. The Divisor
Register controls the exact multiplication factor. This register
may be set to any value between 221 and 4095. (The divide
ratio that is actually used is the programmed divide ratio
plus one.)
2. The 2-Bit VCO Range Register. To lower the sensitivity of
the output frequency to noise on the control signal, the VCO
operating frequency range is divided into four overlapping
regions. The VCO Range register sets this operating range.
Because there are only four possible regions, only the two
least-significant bits of the VCO Range register are used.
The frequency ranges for the lowest and highest regions
are shown in Table II.
–12–
REV. 0
AD9886
4. The 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sampling point within a clock cycle. The Phase Adjust register
provides 32 phase-shift steps of 11.25° each. The Hsync
signal with an identical phase shift is available through the
HSOUT pin. Phase adjustment is still available if the pixel
clock is being provided externally.
Table II. VCO Frequency Ranges
PV1
PV0
Pixel Clock
Range (MHz)
KVCO Gain
(MHz/V)
0
0
1
1
0
1
0
1
12–35
35–70
70–110
110–140
150
150
150
180
The COAST pin is used to allow the PLL to continue to run
at the same frequency, in the absence of the incoming Hsync
signal. This may be used during the vertical sync period, or
any other time that the Hsync signal is unavailable. The
polarity of the COAST signal may be set through the Coast
Polarity Register. Also, the polarity of the Hsync signal may
be set through the HSYNC Polarity Register. For both
HSYNC and COAST, a value of “1” inverts the signal.
3. The 3-Bit Charge Pump Current Register. This register
allows the current that drives the low pass loop filter to be
varied. The possible current values are listed in Table III.
Table III. Charge Pump Current/Control Bits
Ip2
Ip1
Ip0
Current (␮A)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
100
150
250
350
500
750
1500
Table IV. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Refresh
Rate
Horizontal
Frequency
Pixel Rate
VCORNGE
CURRENT
640 × 480
60 Hz
72 Hz
75 Hz
85 Hz
31.5 kHz
37.7 kHz
37.5 kHz
43.3 kHz
25.175 MHz
31.500 MHz
31.500 MHz
36.000 MHz
00
00
00
00
101
101
110
110
SVGA
800 × 600
56 Hz
60 Hz
72 Hz
75 Hz
85 Hz
35.1 kHz
37.9 kHz
48.1 kHz
46.9 kHz
53.7 kHz
36.000 MHz
40.000 MHz
50.000 MHz
49.500 MHz
56.250 MHz
00
01
01
01
01
101
101
101
101
110
XGA
1024 × 768
60 Hz
70 Hz
75 Hz
80 Hz
85 Hz
48.4 kHz
56.5 kHz
60.0 kHz
64.0 kHz
68.3 kHz
65.000 MHz
75.000 MHz
78.750 MHz
85.500 MHz
94.500 MHz
01
10
10
10
10
110
101
101
101
101
SXGA
1280 × 1024
60 Hz
75 Hz
85 Hz
64.0 kHz
80.0 kHz
91.1 kHz
108.000 MHz
135.000 MHz
157.500 MHz*
10
11
10
110
110
110
UXGA
1600 × 1200
60 Hz
65 Hz
70 Hz
75 Hz
85 Hz
75.0 kHz
81.3 kHz
87.5 kHz
93.8 kHz
106.3 kHz
162.000 MHz*
175.500 MHz*
189.000 MHz*
202.500 MHz*
229.500 MHz*
10
10
10
10
11
110
110
110
110
110
Standard
Resolution
VGA
*Graphics sampled at one-half the incoming pixel rate using Alternate Pixel Sampling mode.
REV. 0
–13–
AD9886
OFFSET
7
GAIN
8
DAC
DAC
SCANCLK
REF
SCANIN
IN
CLAMP
TSU = 3ns
8
ADC
x1.2
THOLD = 0ns
Figure 11. SCAN Setup and Hold
VOFF
Alternate Pixel Sampling Mode
A Logic 1 input on Clock Invert (CKINV, Pin 94) inverts the
nominal ADC clock. CKINV can be switched between frames
to implement the alternate pixel sampling mode. This allows
higher effective image resolution to be achieved at lower pixel
rates but with lower frame rates.
Figure 8. ADC Block Diagram (Single Channel Output)
OFFSET
RANGE
INPUT RANGE
VOFF
(128 CODES)
VOFF
(128 CODES)
0V
INPUT RANGE
0.5V
OFFSET RANGE
1V
0V
Figure 9. Relationship of Offset Range to Input Range
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
Figure 12. Odd and Even Pixels in a Frame
SCAN Function
The SCAN function is intended as a pseudo JTAG function for
manufacturing test for the board. The ordinary operation of the
AD9886 is disabled during SCAN.
To enable the SCAN function, set register 14h, bit 2 to 1. To
SCAN in data to all 48 digital outputs, apply 48 serial bits of
data and 48 clocks (typically 5 MHz, max of 20 MHz) to the
SCANIN and SCANCLK pins respectively. The data is shifted
in on the rising edge of SCANCLK. The first serial bit shifted
in will appear at the RED A<7> output after one clock cycle.
After 48 clocks, the first bit is shifted all the way to the BLU
B<0>. The 48th bit will now be at the RED A<7> output. If
SCANCLK continues after 48 cycles, the data will continue to be
shifted from RED A<7> to BLU B<0> and will come out of the
SCANOUT pin as serial data on the falling edge of SCANCLK.
This is illustrated in Figure 10. A setup time (Tsu) of 3 ns
should be plenty and no hold time (Thold) is required (≥ 0 ns).
This is illustrated in Figure 11.
On one frame, only even pixels are digitized. On the subsequent
frame, odd pixels are sampled. By reconstructing the entire
frame in the graphics controller, a complete image can be reconstructed. This is very similar to the interlacing process that is
employed in broadcast television systems, but the interlacing is
vertical instead of horizontal. The frame data is still presented to
the display at the full desired refresh rate (usually 60 Hz) so no
flicker artifacts added.
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
Figure 13. Odd Pixels from Frame 1
SCANCLK
SCANIN
BIT 1
RED A<7>
BLUE B<0>
SCANOUT
X
BIT 2
BIT 3
BIT 47
BIT 48
X
BIT 1
BIT 1
BIT 1
BIT 46
BIT 47
BIT 48
X
X
X
X
X
X
BIT 1
BIT 2
X
X
X
X
BIT 1
BIT 2
Figure 10. SCAN Timing
–14–
REV. 0
AD9886
t PER
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
t CYCLE
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
DATACK
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
DATACK\
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
t SKEW
Figure 14. Even Pixels from Frame 2
DATA
HSOUT
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
Figure 17. Output Timing
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
Hsync Timing
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
Horizontal sync is processed in the AD9886 to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
Figure 15. Combine Frame Output from Graphics Controller
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360° in 32 steps via the Phase Adjust
register (to optimize the pixel sampling time). Display systems use
Hsync to align memory and display write cycles, so it is important
to have a stable timing relationship between Hsync output
(HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9886. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be programmed either active high or active low (Register 04H, Bit 4).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via Register 07H. HSOUT is the sync signal that should be used to drive
the rest of the display system.
Coast Timing
Figure 16. Subsequent Frame from Controller
Timing (Analog Interface)
The following timing diagrams show the operation of the
AD9886 analog interface in all clock modes. The part establishes timing by having the sample that corresponds to the pixel
digitized when the leading edge of HSYNC occurs sent to the
“A” data port. In Dual Channel Mode, the next sample is sent
to the “B” port. Future samples are alternated between the “A”
and “B” data ports. In Single Channel Mode, data is only sent
to the “A” data port, and the “B” port is placed in a high
impedance state.
The Output Data Clock signal is created so that its rising edge
always occurs between “A” data transitions, and can be used to
latch the output data externally.
There is a pipeline in the AD9886, which must be flushed before
valid data becomes available. In all single channel modes, four
data sets are presented before valid data is available. In all dual
channel modes, two data sets are presented before valid “A”
port data is available.
REV. 0
In most computer systems, the Hsync signal is provided continuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used.
In some systems, however, Hsync is disturbed during the Vertical Sync period (Vsync). In some cases, Hsync pulses disappear.
In other systems, such as those that employ Composite Sync
(Csync) signals or embed Sync-On-Green (SOG), Hsync includes
equalization pulses or other distortions during Vsync. To avoid
upsetting the clock generator during Vsync, it is important to
ignore these distortions. If the pixel clock PLL sees extraneous
pulses, it will attempt to lock to this new frequency, and will
have changed frequency by the end of the Vsync period. It will
then take a few lines of correct Hsync timing to recover at the
beginning of a new frame, resulting in a “tearing” of the image
at the top of the display.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
–15–
AD9886
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PxCK
HS
5-PIPE DELAY
ADCCK
DATACK
D0
DOUTA
D1
D2
D3
D4
D5
D6
D7
HSOUT
Figure 18. Single-Channel Mode
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PxCK
HS
5-PIPE DELAY
ADCCK
DATACK
DOUTA
D0
D2
D4
D6
HSOUT
Figure 19. Single-Channel Mode, 2 Pixels/Clock (Even Pixels)
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PxCK
HS
5.5-PIPE DELAY
ADCCK
DATACK
DOUTA
D1
D3
D5
D7
HSOUT
Figure 20. Single-Channel Mode, 2 Pixels/Clock (Odd Pixels)
–16–
REV. 0
AD9886
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PxCK
HS
5-PIPE DELAY
ADCCK
DATACK
DOUTA
D2
D0
DOUTB
D1
D4
D3
D6
D5
D7
HSOUT
Figure 21. Dual-Channel Mode, Interleaved Outputs
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PxCK
HS
6-PIPE DELAY
ADCCK
DATACK
DOUTA
D2
D0
DOUTB
D1
D4
D3
D6
D5
D7
HSOUT
Figure 22. Dual-Channel Mode, Parallel Outputs
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PxCK
HS
5-PIPE DELAY
ADCCK
DATACK
DOUTA
DOUTB
D4
D0
D2
D6
HSOUT
Figure 23. Dual-Channel Mode, Interleaved Outputs, 2 Pixels/Clock (Even Pixels)
REV. 0
–17–
AD9886
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PxCK
HS
5.5-PIPE DELAY
ADCCK
DATACK
DOUTA
D1
D5
D3
DOUTB
D7
HSOUT
Figure 24. Dual-Channel Mode, Interleaved Outputs, 2 Pixels/Clock (Odd Pixels)
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PxCK
HS
6-PIPE DELAY
ADDCK
DATACK
DOUTA
D0
D4
DOUTB
D2
D6
HSOUT
Figure 25. Dual-Channel Mode, Parallel Outputs, 2 Pixels/Clock (Even Pixels)
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PxCK
HS
6.5-PIPE DELAY
ADCCK
DATACK
DOUTA
D1
D5
DOUTB
D3
D7
HSOUT
Figure 26. Dual-Channel Mode, Parallel Outputs, 2 Pixels/Clock (Odd Pixels)
–18–
REV. 0
AD9886
2-Wire Serial Register Map
The AD9886 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is
employed to write and read the Control Registers through the 2-line serial interface port.
Table V. Control Register Map
Hex
Address
Write and
Read or
Read Only
Bits
00H
RO
7:0
01H
R/W
7:0
01101001
PLL Div MSB This register is for Bits [11:4] of the PLL divider. Larger values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. (This will give the PLL more time to
lock.) See Note 1 .
02H
R/W
7:4
1101****
PLL Div LSB
Bits [7:4] LSBs of the PLL divider word. See Note 1.
03H
R/W
7:2
1*******
*01*****
VCO/CPMP
Bit 7—Must be set to 1 for proper device operation.
Bits [6:5] VCO Range. Selects VCO frequency range. (See PLL
description.)
Bits [4:2] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description.)
Default
Value
Register
Name
Chip Revision
***001**
Function
Bits 7 through 4 represent functional revisions to the analog interface.
Bits 3 through 0 represent nonfunctional related revisions.
Revision 0 = 0000 0000
04H
R/W
7:3
01000***
Phase Adjust
ADC Clock phase adjustment. Larger values mean more delay.
(1 LSB = T/32.)
05H
R/W
7:0
10000000
Clamp
Placement
Places the Clamp signal an integer number of clock periods after the trailing edge of the Hsync signal.
06H
R/W
7:0
10000000
Clamp
Duration
Number of clock periods that the Clamp signal is actively clamping.
07H
R/W
7:0
00100000
Hsync Output
Pulsewidth
Sets the number of pixel clocks that HSOUT will remain active.
08H
R/W
7:0
10000000
Red Gain
Controls ADC input range (Contrast) of each respective channel.
Bigger values give less contrast.
09H
R/W
7:0
10000000
Green Gain
0AH
R/W
7:0
10000000
Blue Gain
0BH
R/W
7:1
1000000*
Red Offset
0CH
R/W
7:1
1000000*
Green Offset
0DH
R/W
7:1
1000000*
Blue Offset
0EH
R/W
7:3
1*******
Mode
Control 1
*1******
**0*****
***1****
****1***
REV. 0
Controls dc offset (Brightness) of each respective channel. Bigger
values decrease brightness.
Bit 7—Channel Mode. Determines Single Channel or Dual Channel
Output Mode. (Logic 0 = Single Channel Mode, Logic 1 = Dual
Channel Mode.)
Bit 6—Output Mode. Determine Interleaved or Parallel Output Mode.
(Logic 0 = Interleaved Mode, Logic 1 = Parallel Mode.)
Bit 5—A/B Invert. Determines which port outputs the first data byte
after Hsync. (Logic 0 = A Port, Logic 1 = B Port.)
Bit 4—Hsync Output polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync.)
Bit 3—Vsync Output Invert. (Logic 0 = No Invert, Logic 1 = Invert.)
–19–
AD9886
Table V. Control Register Map (Continued)
Hex
Address
Write and
Read or
Read Only
Bits
Default
Value
Register
Name
0FH
W/R
7:0
1*******
PLL and
Clamp Control
*1******
**0*****
***1****
****0***
*****0**
******0*
*******0
10H
W/R
5:2
**11****
*****1**
RO
7:1
Bit 7—HSYNC Polarity. Changes polarity of incoming Hsync
signal. (Logic 0 = Active Low, Logic 1 = Active High.)
Bit 6—Coast Polarity. Changes polarity of external COAST signal.
(Logic = 0 = Active Low, Logic 1 = Active High.)
Bit 5—Clamp Function. Chooses between HSYNC for Clamp signal
or another external signal to be used for clamping. (Logic 0 = HSYNC,
Logic 1 = Clamp.)
Bit 4—Clamp Polarity. Valid only with external CLAMP signal.
(Logic 0 = Active Low, Logic 1 selects Active High.)
Bit 3—EXTCLK. Shuts down PLL and allows external clock to drive
the part. (Logic 0 = use internal PLL, Logic 1 = bypassing of the
internal PLL.)
Bit 2—Red Clamp Select—Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 120).
Bit 1—Green Clamp Select—Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 111).
Bit 0—Blue Clamp Select—Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 101).
Bit 5, 4—Output Drive: Selects between high, medium, and low
output drive strength. (Logic 11 or 10 = High, 01 = Medium, and
00 = Low.)
Bit 3—PDO: High Impedance Outputs. (Logic 0 = Normal, Logic
1 = High Impedance.)
Bit 2—Sync Detect (SyncDT) Polarity. This bit sets the polarity
for the SyncDT output pin. (Logic 1 = Active High, Logic 0 =
Active Low.)
****0***
11H
Function
Sync Detect/
Active
Interface
Bit 7—Analog Interface Hsync Detect. It is set to Logic 1 if Hsync
is present on the analog interface, else it is set to Logic 0.
Bit 6—Analog Interface Sync-on-Green Detect. It is set to Logic 1
if sync is present on the green video input, else it is set to 0.
Bit 5—Analog Interface Vsync Detect. It is set to Logic 1 if Vsync
is present on the analog interface, else it is set to Logic 0.
Bit 4—Digital Interface clock Detect. It is set to Logic 1 if the
clock is present on the digital interface, else it is set to Logic 0.
Bit 3—AI: Active Interface. This bit indicates which interface is
active. (Logic 0 = Digital Interface, Logic 1 = Analog Interface.)
Bit 2—AHS: Active Hsync. This bit indicates which analog HSYNC
is being used. (Logic 0 = HSYNC Input Pin, Logic 1 = HSYNC
from Sync-on-Green.)
Bit 1—AVS: Active Vsync. This bit indicates which analog VSYNC
is being used. (Logic 0 = VSYNC input pin, Logic 1 = VSYNC from
sync separator.)
–20–
REV. 0
AD9886
Table V. Control Register Map (Continued)
Hex
Address
Write and
Read or
Read Only
Bits
Default
Value
Register
Name
12H
W/R
7:0
0*******
Active
Interface
Bit 7—AIO: Active Interface Override. If set to Logic 1, the user
can select the active interface via Bit 6. If set to Logic 0, the active
interface is selected via Bit 3 in Register 11H.
Bit 6—AIS: Active Interface Select. Logic 0 selects the analog interface as active. Logic 1 selects the digital interface as active. Note:
The indicated interface will be active only if Bit 7 is set to Logic 1
or if both interfaces are active (Bits 6 or 7 and 4 = Logic 1 in
Register 11H).
Bit 5—Active Hsync Override. If set to Logic 1, the user can select
the Hsync to be used via Bit 4. If set to Logic 0, the active interface
is selected via Bit 2 in Register 11H.
Bit 4—Active Hsync Select. Logic 0 selects Hsync as the active
sync. Logic 1 selects Sync-on-Green as the active sync. Note: The
indicated Hsync will be used only if Bit 5 is set to Logic 1 or if
both syncs are active (Bits 6, 7 = Logic 1 in Register 11H.)
Bit 3—Active Vsync Override. If set to Logic 1, the user can select
the Vsync to be used via Bit 2. If set to Logic 0, the active interface
is selected via Bit 1 in Register 11H.
Bit 2—Active Vsync Select. Logic 0 selects Raw Vsync as the
output Vsync. Logic 1 selects Sync Separated Vsync as the output
Vsync. Note: The indicated Vsync will be used only if Bit 3 is set
to Logic 1.
Bit 1—Coast Select. Logic 0 selects the coast input pin to be used for
the PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
Bit 0—PWRDN. Full Chip Power-Down, active low. (Logic 0 =
Full Chip Power-Down, Logic 1 = Normal.)
*0******
**0*****
***0****
****0***
*****0**
******0*
*******1
Function
13H
W/R
7:0
00100000
Sync
Separator
Threshold
Sync Separator Threshold—Sets how many pixel clocks the sync
separator will count to before toggling high or low. This should be
set to some number greater than the maximum Hsync or equalization pulsewidth.
14H
W/R
7:0
***1****
*****0**
******0*
Control Bits
Bit 4—Test Bit. (Must be set to 1 for proper operation of chip.)
Bit 2—Scan Enable. (Logic 0 = Not Enabled, Logic 1 = Enabled.)
Bit 1—Coast Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 6 in Register 0Fh.)
Bit 0– Hsync Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 7 in Register 0Fh.)
*******0
15H
W/R
7:0
Test Register
Reserved for future use.
16H
W/R
7:0
Test Register
Reserved for future use.
17H
RO
7:0
Test Register
Reserved for future use.
18H
RO
7:0
Test Register
Reserved for future use.
NOTE
1
The AD9886 only updates the PLL divide ratio when the LSBs are written to (Register 02h).
REV. 0
–21–
AD9886
The PLL gives the best jitter performance at high frequencies. For this reason, in order to output low pixel
rates and still get good jitter performance, the PLL actually operates at a higher frequency but then divides down
the clock rate afterwards. Table VI shows the pixel rates
for each VCO range setting. The PLL output divisor is
automatically selected with the VCO range setting.
TWO-WIRE SERIAL CONTROL REGISTER DETAIL
CHIP IDENTIFICATION
00
7–0 Chip Revision
Bits 7 through 4 represent functional revisions to the
analog interface. Changes in these bits will generally
indicate that software and/or hardware changes will be
required for the chip to work properly. Bits 3 through 0
represent nonfunctional related revisions and are reset to
0000 whenever the MSBs are changed. Changes in these
bits are considered transparent to the user.
Table VI. VCO Ranges
PLL DIVIDER CONTROL
01
7–0 PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. (The operational divide ratio is PLLDIV + 1.)
The PLL derives a master clock from an incoming Hsync
signal. The master clock frequency is then divided by an
integer value, such that the output is phase-locked to
Hsync. This PLLDIV value determines the number of
pixel times (pixels plus horizontal blanking overhead) per
line. This is typically 20% to 30% more than the number
of active pixels in the display.
4–2 CURRENT Charge Pump Current
CURRENT
Current (␮A)
000
001
010
011
100
101
110
111
50
100
150
250
350
500
750
1500
CURRENT must be set to correspond with the desired
operating frequency (incoming pixel rate).
The power-up default value is CURRENT = 001.
04
7–3 Clock Phase Adjust
A five-bit value that adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25° shift
in sampling phase.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The power-up default value is 16.
CLAMP TIMING
05
7–0 Clamp Placement
The four least significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
An eight-bit register that sets the position of the internally
generated clamp.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
When EXTCLMP = 0, a clamp signal is generated internally, at a position established by the clamp placement and
for a duration set by the clamp duration. Clamping is
started (Clamp Placement) pixel periods after the trailing
edge of Hsync. The clamp placement may be programmed
to any value between 1 and 255. A value of 0 is not
supported.
The AD9886 updates the full divide ratio only when this
register is written to.
CLOCK GENERATOR CONTROL
03
7 TEST Set to One
03
12–35
35–70
70–110
110–140
Table VII. Charge Pump Currents
However, many computer systems do not conform precisely to the recommendations, and these numbers should
be used only as a guide. The display system manufacturer
should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV will usually produce
one or more vertical noise bars on the display. The greater
the error, the greater the number of bars produced.
7–4 PLL Divide Ratio LSBs
00
01
10
11
Three bits that establish the current driving the loop filter
in the clock generator.
VESA has established some standard timing specifications,
which will assist in determining the value for PLLDIV as
a function of horizontal and vertical display resolution
and frame rate (Table IV).
02
Pixel Rate Range
The power-up default value is = 01.
03
The 12-bit value of the PLL divider supports divide ratios
from 2 to 4095. The higher the value loaded in this register, the higher the resulting clock frequency with respect
to a fixed Hsync frequency.
The AD9886 updates the full divide ratio only when the
LSBs are changed. Writing to this register by itself will not
trigger an update.
VCORNGE
The clamp should be placed during a time that the input
signal presents a stable black-level reference, usually the
back porch period between Hsync and the image.
6–5 VCO Range Select
Two bits that establish the operating range of the clock
generator.
When EXTCLMP = 1, this register is ignored.
VCORNGE must be set to correspond with the desired
operating frequency (incoming pixel rate).
–22–
REV. 0
AD9886
06
7–0 Clamp Duration
0D
An 8-bit register that sets the duration of the internally
generated clamp.
When EXTCLMP = 0, a clamp signal is generated internally, at a position established by the clamp placement
and for a duration set by the clamp duration. Clamping is
started (clamp placement) pixel periods after the trailing
edge of Hsync, and continues for (clamp duration) pixel
periods. The clamp duration may be programmed to any
value between 1 and 255. A value of 0 is not supported.
MODE CONTROL 1
0E 7 Channel Mode
A bit that determines whether all pixels are presented to a
single port (A), or alternating pixels are demultiplexed to
Ports A and B.
Table VIII. Channel Mode Settings
For the best results, the clamp duration should be set to
include the majority of the black reference signal time that
follows the Hsync signal trailing edge. Insufficient clamping time can produce brightness changes at the top of the
screen, and a slow recovery from large changes in the
Average Picture Level (APL), or brightness.
DEMUX
Function
0
1
All Data Goes to Port A
Alternate Pixels Go to Port A and Port B
When DEMUX = 0, Port B outputs are in a high-impedance state. The maximum data rate for single port mode
is 100 MHz. The timing diagrams show the effects of this
option.
When EXTCLMP = 1, this register is ignored.
Hsync Pulsewidth
07
7–0 Hsync Output Pulsewidth
An 8-bit register that sets the duration of the Hsync
output pulse.
7–1 Blue Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the
GREEN channel. See REDOFST (0B).
The power-up default value is 1.
0E
The leading edge of the Hsync output is triggered by the
internally generated, phase-adjusted PLL feedback clock.
The AD9886 then counts a number of pixel clocks equal
to the value in this register. This triggers the trailing edge
of the Hsync output, which is also phase-adjusted.
6 Output Mode
A bit that determines whether all pixels are presented to
Port A and Port B simultaneously on every second
DATACK rising edge, or alternately on port A and Port B
on successive DATACK rising edges.
Table IX. Output Mode Settings
INPUT GAIN
08
7–0 Red Channel Gain Adjust
An 8-bit word that sets the gain of the RED channel.
The AD9886 can accommodate input signals with a
full-scale range of between 0.5 V and 1.5 V p-p. Setting
REDGAIN to 255 corresponds to an input range of 1.0 V.
A REDGAIN of 0 establishes an input range of 0.5 V.
Note that INCREASING REDGAIN results in the picture
having LESS CONTRAST (the input signal uses fewer
of the available converter codes). See Figure 3.
09
7–0 Green Channel Gain Adjust
An 8-bit word that sets the gain of the GREEN channel.
See REDGAIN (08).
0A
PARALLEL
Function
0
1
Data Is Interleaved
Data Is Simultaneous On Every Other
Data Clock
When in single port mode (DEMUX = 0), this bit is
ignored. The timing diagrams show the effects of this
option.
The power-up default value is PARALLEL = 1.
0E
5 Output Port Phase
One bit that determines whether even pixels or odd pixels
go to Port A.
7–0 Blue Channel Gain Adjust
An 8-bit word that sets the gain of the BLUE channel.
See REDGAIN (08).
Table X. Output Port Phase Settings
INPUT OFFSET
0B 7–1 Red Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the RED
channel. One LSB of offset adjustment equals approximately
one LSB change in the ADC offset. Therefore, the absolute
magnitude of the offset adjustment scales as the gain of the
channel is changed. A nominal setting of 31 results in the
channel nominally clamping the back porch (during the
clamping interval) to Code 00. An offset setting of 63 results
in the channel clamping to Code 31 of the ADC. An offset
setting of 0 clamps to code –31 (off the bottom of the
range). Increasing the value of Red Offset DECREASES
the brightness of the channel.
0C
First Pixel After Hsync
0
1
Port A
Port B
In normal operation (OUTPHASE = 0), when operating
in dual-port output mode (DEMUX = 1), the first sample
after the Hsync leading edge is presented at Port A. Every
subsequent ODD sample appears at Port A. All EVEN
samples go to Port B.
When OUTPHASE = 1, these ports are reversed and the
first sample goes to Port B.
When DEMUX = 0, this bit is ignored as data always
comes out of only Port A.
7–1 Green Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the
GREEN channel. See REDOFST (0B).
REV. 0
OUTPHASE
–23–
AD9886
0E
4 HSYNC Output Polarity
Active HIGH means that the clock generator will ignore
Hsync inputs when COAST is HIGH, and continue operating at the same nominal frequency until COAST goes
LOW.
One bit that determines the polarity of the HSYNC output and the SOG output. Table XI shows the effect of this
option. SYNC indicates the logic state of the sync pulse.
Table XI. HSYNC Output Polarity Settings
This function needs to be used along with the COAST
polarity override bit (Register 14, Bit 1).
Setting
SYNC
The power-up default value is CSTPOL = 1.
0
1
Logic 1 (Positive Polarity)
Logic 0 (Negative Polarity)
0F
5 Clamp Input Signal Source
A bit that determines the source of clamp timing.
The default setting for this register is 1. (This option
works on both the analog and digital interfaces.)
0E
0F
Table XV. Clamp Input Signal Source Settings
3 VSYNC Output Invert
EXTCLMP
One bit that inverts the polarity of the VSYNC output.
Table XII shows the effect of this option.
0
Internally-Generated Clamp
1
Externally-Provided Clamp Signal
Table XII. VSYNC Output Polarity Settings
A 0 enables the clamp timing circuitry controlled by
CLPLACE and CLDUR. The clamp position and duration is counted from the leading edge of Hsync.
Setting
VSYNC Output
0
1
No Invert
Invert
Function
The default setting for this register is 1. (This option
works on both the analog and digital interfaces.)
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is
active. The polarity of CLAMP is determined by the
CLAMPOL bit.
7 HSPOL HSYNC Input Polarity
The power-up default value is EXTCLMP = 0.
A bit that must be set to indicate the polarity of the HSYNC
signal that is applied to the PLL HSYNC input.
0F
4 CLAMP Input Signal Polarity
A bit that determines the polarity of the externally provided CLAMP signal.
Table XIII. HSYNC Input Polarity Settings
HSPOL
Function
0
1
Active LOW
Active HIGH
Table XVI. CLAMP Input Signal Polarity Settings
Active LOW is the traditional negative-going Hsync pulse.
All timing is based on the leading edge of Hsync, which is
the FALLING edge. The rising edge has no effect.
EXTCLMP
Function
0
1
Active LOW
Active HIGH
A Logic 0 means that the circuit will clamp when CLAMP
is HIGH, and it will pass the signal to the ADC when
CLAMP is LOW.
Active HIGH is inverted from the traditional Hsync, with
a positive-going pulse. This means that timing will be
based on the leading edge of Hsync, which is now the
RISING edge.
A Logic 1 means that the circuit will clamp when CLAMP
is LOW, and it will pass the signal to the ADC when
CLAMP is HIGH.
The device will operate if this bit is set incorrectly, but the
internally generated clamp position, as established by
CLPOS, will not be placed as expected, which may generate clamping errors.
The power-up default value is CLAMPOL = 1.
0F
3 External Clock Select
A bit that determines the source of the pixel clock.
The power-up default value is HSPOL = 1.
0F
Table XVII. External Clock Select Settings
6 COAST Input Polarity
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
Table XIV. COAST Input Polarity Settings
CSTPOL
Function
0
1
Active LOW
Active HIGH
EXTCLK
Function
0
Internally Generated Clock
1
Externally Provided Clock Signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
A Logic 1 enables the external CKEXT input pin. In this
mode, the PLL Divide Ratio (PLLDIV) is ignored. The
clock phase adjust (PHASE) is still functional.
Active LOW means that the clock generator will ignore
Hsync inputs when COAST is LOW, and continue operating at the same nominal frequency until COAST goes
HIGH.
The power-up default value is EXTCLK = 0.
–24–
REV. 0
AD9886
0F
(even port only). A Logic 1 selects 2 pixels per clock (both
ports). See the Digital Interface Timing Diagrams, Figures 29 to 32, for a visual representation of this function.
Note: This function operates exactly like the DEMUX
function on the analog interface.
2 Red Clamp Select
A bit that determines whether the red channel is clamped
to ground or to midscale. For RGB video, all three channels are referenced to ground. For YcbCr (or YUV), the
Y channel is referenced to ground, but the CbCr channels
are referenced to midscale. Clamping to midscale actually
clamps to Pin 118, RCLAMPV.
Table XXII. Pix Select Settings
Table XVIII. Red Clamp Select Settings
Clamp
Function
0
1
Clamp to Ground
Clamp to Midscale (Pin 118)
The default setting for this register is 0.
0F
Table XIX. Green Clamp Select Settings
0F
0
1
Clamp to Ground
Clamp to Midscale (Pin 109)
0
1
1 Pixel per Clock
2 Pixels per Clock
5, 4 Output Drive
These two bits select the drive strength for the high-speed
digital outputs (all data output and clock output pins).
Higher drive strength results in faster rise/fall times and in
general makes it easier to capture data. Lower drive strength
results in slower rise/fall times and helps to reduce EMI
and digitally generated power supply noise. The exact
timing specifications for each of these modes are specified
in the Table IV.
A bit that determines whether the green channel is clamped
to ground or to midscale.
Function
Function
The default for this register is 0, 1 pixel per clock.
10
1 Green Clamp Select
Clamp
Pix Select
Table XXIII. Output Drive Strength Settings
The default setting for this register is 0.
Bit 5
Bit 4
Result
0 Blue Clamp Select
1
1
0
1
0
X
High Drive Strength
Medium Drive Strength
Low Drive Strength
A bit that determines whether the blue channel is clamped
to ground or to midscale.
The default for this register is 11, high drive strength. (This
option works on both the analog and digital interfaces.)
Table XX. Blue Clamp Select Settings
Clamp
Function
0
1
Clamp to Ground
Clamp to Midscale (Pin 99)
10
3 PDO—Power-Down Outputs
A bit that can put the outputs in a high impedance mode.
This applies only to the 48 data output pins and the two
data clock outputs pins.
The default setting for this register is 0.
Table XXIV. Power-Down Outputs Settings
MODE CONTROL 2
10
7 Clk Inv Data Output Clock Invert
A control bit for the inversion of the output data clocks,
(Pins 134, 135). This function works only for the digital
interface. When not inverted, data is output on the rising
edge of the data clock. See timing diagrams to see how
this affects timing.
Table XXI. Clock Output Invert Settings
Clk Inv
Function
0
1
Not Inverted
Inverted
10
0
1
Normal Operation
Three-State
2 Sync Detect Polarity
This pin controls the polarity of the Sync Detect output
pin (Pin 136).
Table XXV. Sync Detect Polarity Settings
6 Pix Select
This bit selects either 1 or 2 pixels per clock mode for the
digital interface. It determines whether the data comes out
of a single port (even port only), at the full data rate or
out of two ports (both even and odd ports) at one-half the
full data rate per port. A Logic 0 selects 1 pixel per clock
REV. 0
Function
The default for this register is 0. (This option works on
both the analog and digital interfaces.)
The default for this register is 0, not inverted.
10
CKINV
Polarity
Function
0
1
Activity = Logic 1 Output
Activity = Logic 0 Output
The default for this register is 0. (This option works on
both the analog and digital interfaces.)
–25–
AD9886
register. If both interfaces are detected, the user can
determine which has priority via Bit 6 in register 12H.
The user can override this function via Bit 7 in Register
12H. If the override bit is set to Logic 1, then this bit will
be forced to whatever the state of Bit 6 in Register 12H is
set to.
SYNC DETECTION AND CONTROL
11
7 Analog Interface HSYNC Detect
This bit is used to indicate when activity is detected on
the HSYNC input pin (Pin 82). If HSYNC is held high or
low, activity will not be detected.
Table XXVI. HSYNC Detection Results
Table XXX. Active Interface Results
11
Detect
Function
0
1
No Activity Detected
Activity Detected
Figure 38 shows where this function is implemented.
Bits 7, 6,
or 5
(Analog
Detection)
Bit 4
(Digital
Detection)
Override
AI
6 Analog Interface Sync-on-Green Detect
0
0
0
0
1
1
X
1
0
1
X
0
0
0
1
Soft
Power-Down
(Seek Mode)
1
0
Bit 6 in 12H
Bit 6 in 12H
This bit is used to indicate when sync activity is detected
on the Sync-on-Green input pin (Pin 108).
Table XXVII. Sync-on-Green Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
AI = 0 means Analog Interface.
AI = 1 means Digital Interface.
The override bit is in Register 12H, Bit 7.
Figure 38 shows where this function is implemented.
11
This bit is used to determine which HSYNC should be
used for the analog interface, the HSYNC input or Syncon-Green. It uses Bits 7 and 6 in this register for inputs
in determining which should be active. Similar to the previous bit, if both HSYNC and SOG are detected the user
can determine which has priority via Bit 4 in Register
12H. The user can override this function via Bit 5 in
Register 12H. If the override bit is set to Logic 1, this
bit will be forced to whatever the state of Bit 4 in Register
12H is set to.
Warning: If no sync is present on the green video input,
normal video may still trigger activity.
11
5 Analog Interface VSYNC Detect
This bit is used to indicate when activity is detected on
the VSYNC input pin (Pin 81). If VSYNC is held high or
low, activity will not be detected.
Table XXVIII. VSYNC Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
Table XXXI. Active HSYNC Results
Figure 38 shows where this function is implemented.
11
4 Digital Interface Clock Detect
This bit is used to indicate when activity is detected on
the digital interface clock input.
Table XXIX. Digital Interface Clock Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
The sync processing block diagram shows where this
function is implemented.
11
2 AHS—Active HSYNC
Bit 7
(HSYNC
Detect)
Bit 6
(SOG
Detect)
Override
AHS
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
Bit 4 in 12H
1
0
Bit 4 in 12H
Bit 4 in 12H
AHS = 0 means use the HSYNC pin input for HSYNC.
AHS = 1 means use the SOG pin input for HSYNC.
The override bit is in Register 12H, Bit 5.
11
1 AVS—Active VSYNC
This bit is used to determine which VSYNC should be
used for the analog interface; the VSYNC input or output
from the sync separator. It uses Bit 5 in this register as the
input for determining which should be active. Similar to
the previous bit, if both HSYNC and SOG are detected
the user can determine which has priority via Bit 4 in
register 12H. The user can override this function via Bit 3
in Register 12H. If the override bit is set to Logic 1, this
bit will be forced to whatever the state of Bit 2 in Register
12H is set to.
3 Active Interface
This bit is used to indicate which interface should be
active, analog or digital. It checks for activity on the
analog interface and for activity on the digital interface,
then determines which should be active according to
Table XXX. Specifically, analog interface detection is
determined by OR-ing Bits 7, 6, and 5 in this register.
Digital interface detection is determined by Bit 4 in this
–26–
REV. 0
AD9886
Table XXXII. Active VSYNC Results
Bit 5
(VSYNC
Detect)
Override
0
1
X
0
0
1
Table XXXVI. Active HSYNC Select Settings
Select
Result
AVS
0
1
HSYNC Input
Sync-on-Green Input
0
1
Bit 2 in 12H
The default for this register is 0.
12
12
7 AIO—Active Interface Override
This bit is used to override the automatic interface selection (Bit 3 in Register 11H). To override, set this bit to
Logic 1. When overriding, the active interface is set via
Bit 6 in this register.
Table XXXVII. Active VSYNC Override Settings
Table XXXIII. Active Interface Override Settings
AIO
Result
0
1
Autodetermines the Active Interface
Override, Bit 6 Determines the Active Interface
12
Result
0
1
Autodetermines the Active VSYNC
Override, Bit 2 Determines the Active VSYNC
Table XXXVIII. Active VSYNC Select Settings
6 AIS—Active Interface Select
Result
0
1
Analog Interface
Digital Interface
Select
Result
0
1
VSYNC Input
Sync Separator Output
The default for this register is 0.
Table XXXIV. Active Interface Select Settings
AIS
2 Active VSYNC Select
This bit is used to select the active VSYNC when the
override bit is set (Bit 3).
This bit is used under two conditions. It is used to select
the active interface when the override bit is set (Bit 7).
Alternately, it is used to determine the active interface
when not overriding but both interfaces are detected.
12
1 COAST Select
This bit is used to select the active COAST source. The
choices are the COAST input pin or VSYNC. If VSYNC
is selected the additional decision of using the VSYNC
input pin or the output from the sync separator needs to
be made (Bits 3, 2).
The default for this register is 0.
12
Override
The default for this register is 0.
The default for this register is 0.
12
3 Active VSYNC Override
This bit is used to override the automatic VSYNC selection
(Bit 1 in register 11H). To override, set this bit to Logic 1.
When overriding, the active interface is set via Bit 2 in
this register.
AVS = 0 means Sync separator.
AVS = 1 means VSYNC input.
The override bit is in Register 12H, Bit 3.
5 Active Hsync Override
Table XXXIX. COAST Select Settings
This bit is used to override the automatic Hsync selection
(Bit 2 in Register 11H). To override, set this bit to Logic
1. When overriding, the active Hsync is set via Bit 4 in
this register.
Select
Result
0
1
COAST Input Pin
VSYNC (See Above Text)
Table XXXV. Active Hsync Override Settings
Override
Result
0
1
Autodetermines the Active Interface
Override, Bit 4 Determines the Active Interface
The default for this register is 0.
12
The default for this register is 0.
12
0 PWRDN
This bit is used to put the chip in full power-down. This
powers down both interfaces. See the section on Power
Management for details of which blocks are actually
powered down. Note, the chip will be unable to detect
incoming activity while fully powered-down.
4 Active Hsync Select
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set (Bit 5). Alternately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
Table XL. Power-Down Settings
Select
Result
0
1
Power-Down
Normal Operation
The default for this register is 1.
REV. 0
–27–
AD9886
interface. When the serial interface is not active, the logic levels
on SCL and SDA are pulled HIGH by external pull-up resistors.
DIGITAL CONTROL
13
7:0 Sync Separator Threshold
This register is used to set the responsiveness of the sync
separator. It sets how many pixel clock pulses the sync
separator must count to before toggling high or low. It
works like a low-pass filter to ignore Hsync pulses in order
to extract the Vsync signal. This register should be set to
some number greater than the maximum Hsync pulsewidth.
The default for this register is 32.
This register is used to enable the scan function. When
enabled, data can be loaded into the AD9886 outputs
serially with the scan function. The scan function utilizes
three pins (SCANIN, SCANOUT, and SCANCLK). These
pins are described in Table I.
The first eight bits of data transferred after a start signal comprising a 7-bit slave address (the first seven bits) and a single R/W
bit (the eighth bit). The R/W bit indicates the direction of data
transfer, read from (1) or write to (0) the slave device. If the
transmitted slave address matches the address of the device (set
by the state of the SA1-0 input pins in Table XLIV, the AD9886
acknowledges by bringing SDA LOW on the 9th SCL pulse. If
the addresses do not match, the AD9886 does not acknowledge.
Result
Scan Function Disabled
1
Scan Function Enabled
The default for scan enable is 0 (disabled).
14
1 Coast Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going into
the PLL.
Table XLIV. Serial Port Addresses
Table XLII. Coast Input Polarity Override Settings
Override Bit
Result
0
Coast Polarity Determined by Chip
1
Coast Polarity Determined by User
The default for coast polarity override is 0 (polarity
determined by chip).
14
Hsync Polarity Determined by Chip
1
Hsync Polarity Determined by User
Bit 5
A4
Bit 4
A3
Bit 3
A2
Bit 2
A1
Bit 1
A0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
If the AD9886 does not acknowledge the master device during a
write sequence, the SDA remains HIGH so the master can
generate a stop signal. If the master device does not acknowledge
the AD9886 during a read sequence, the AD9886 interprets this
as “end of data.” The SDA remains HIGH so the master can
generate a stop signal.
Table XLIII. HSYNC Input Polarity Override Settings
0
Bit 6
A5
For each byte of data read or written, the MSB is the first bit of
the sequence.
This register is used to override the internal circuitry that
determines the polarity of the Hsync signal going into
the PLL.
Result
Bit 7
A6
(MSB)
Data Transfer via Serial Interface
0 HSYNC Input Polarity Override
Override Bit
Start Signal
Slave Address Byte
Base Register Address Byte
Data Byte to Read or Write
Stop Signal
When the serial interface is inactive (SCL and SDA are HIGH)
communications are initiated by sending a start signal. The start
signal is a HIGH-to-LOW transition on SDA while SCL is
HIGH. This signal alerts all slaved devices that a data transfer
sequence is coming.
Table XLI. Scan Enable Settings
0
There are six components to serial bus operation:
•
•
•
•
•
CONTROL BITS
14
2 Scan Enable
Scan Enable
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA must
change only when SCL is LOW. If SDA changes state while SCL
is HIGH, the serial interface interprets that action as a start or
stop sequence.
The default for Hsync polarity override is 0 (polarity
determined by chip).
2-WIRE SERIAL CONTROL PORT
A 2-wire serial interface control interface is provided. Up to four
AD9886 devices may be connected to the 2-wire serial interface,
with each device having a unique address.
Writing data to specific control registers of the AD9886 requires
that the 8-bit address of the control register of interest be written
after the slave address has been established. This control register
address is the base address for subsequent write operations. The
base address autoincrements by one for each byte of data written
after the data byte intended for the base address. If more bytes
are transferred than there are available addresses, the address will
not increment and remain at its maximum value of 1Dh. Any base
address higher than 1Dh will not produce an acknowledge signal.
The 2-wire serial interface comprises a clock (SCL) and a bidirectional data (SDA) pin. The Analog Flat Panel Interface acts
as a slave for receiving and transmitting data over the serial
–28–
REV. 0
AD9886
SDA
tBUFF
tDSU
tDHO
tSTOSU
tSTASU
tSTAH
tDAL
SCL
tDAH
Figure 27. Serial Port Read/Write Timing
Data is read from the control registers of the AD9886 in a similar
manner. Reading requires two data transfer operations:
The base address must be written with the R/W bit of the slave
address byte LOW to set up a sequential read operation.
Reading (the R/W bit of the slave address byte HIGH) begins at
the previously established base address. The address of the read
register autoincrements after each byte is transferred.
To terminate a read/write sequence to the AD9886, a stop signal must be sent. A stop signal comprises a LOW-to-HIGH
transition of SDA while SCL is HIGH.
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This
is used to change the mode of communication (read, write)
between the slave and master without releasing the serial interface lines.
Serial Interface Read/Write Examples
Write to one control register
➥Start signal
➥Slave Address byte (R/W bit = LOW)
➥Base Address byte
➥Data byte to base address
➥Stop signal
Read from one control register
➥Start signal
➥Slave Address byte (R/W bit = LOW)
➥Base Address byte
➥Start signal
➥Slave Address byte (R/W bit = HIGH)
➥Data byte from base address
➥Stop signal
Read from four consecutive control registers
➥Start signal
➥Slave Address byte (R/W bit = LOW)
➥Base Address byte
➥Start signal
➥Slave Address byte (R/W bit = HIGH)
➥Data byte from base address
➥Data byte from (base address + 1)
➥Data byte from (base address + 2)
➥Data byte from (base address + 3)
➥Stop signal
SDA
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACK
SCL
Figure 28. Serial Interface—Typical Byte Transfer
Write to four consecutive control registers
➥Start signal
➥Slave Address byte (R/W bit = LOW)
➥Base Address byte
➥Data byte to base address
➥Data byte to (base address + 1)
➥Data byte to (base address + 2)
➥Data byte to (base address + 3)
➥Stop signal
REV. 0
BIT 7
–29–
AD9886
ACTIVITY
DETECT
SYNC STRIPPER
NEGATIVE PEAK
CLAMP
AD9886
SYNC SEPARATOR
COMP
SYNC
INTEGRATOR
1/S
SOG
VSYNC
MUX 1
HSYNC IN
SOG OUT
PLL
ACTIVITY
DETECT
POLARITY
DETECT
HSYNC OUT
HSYNC
MUX 2
CLOCK
GENERATOR
HSYNC OUT
PIXEL CLOCK
COAST
POLARITY
DETECT
VSYNC IN
VSYNC OUT
ACTIVITY
DETECT
MUX 4
DE
Figure 29. Sync Processing Block Diagram
Table XLV. Control of the Sync Block Muxes via the
Serial Register
Mux
Nos.
Serial Bus
Control Bit
1 and 2
12H: Bit 4
4
12H: Bit 2
Control
Bit
State
Result
0
1
0
1
Pass Hsync
Pass Sync-on-Green
Pass Vsync
Pass Sync Separator Signal
Sync Slicer
The purpose of the sync slicer is to extract the sync signal from
the green graphics channel. A sync signal is not present on all
graphics systems, only those with “sync-on-green.” The sync
signal is extracted from the green channel in a two step process.
First, the SOG input is clamped to its negative peak (typically
0.3 V below the black level). Next, the signal goes to a comparator with a trigger level that is 0.15 V above the clamped level.
The “sliced” sync is typically a composite sync signal containing
both Hsync and Vsync.
Sync Separator
A sync separator extracts the Vsync signal from a composite
sync signal. It does this through a low-pass filter-like or integratorlike operation. It works on the idea that the Vsync signal stays
active for a much longer time than the Hsync signal, so it rejects
any signal shorter than a threshold value, which is somewhere
between an Hsync pulsewidth and a Vsync pulsewidth.
The sync separator on the AD9886 is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the
polarity of the composite sync signal. (Polarities are determined
elsewhere on the chip.) The basic idea is that the counter counts
up when Hsync pulses are present. But since Hsync pulses are
relatively short in width, the counter only reaches a value of N
before the pulse ends. It then starts counting down eventually
reaching 0 before the next Hsync pulse arrives. The specific
value of N will vary for different video modes, but will always be
less than 255. For example with a 1 µs width Hsync, the counter
will only reach 5 (1µs/200 ns = 5). Now, when Vsync is present
on the composite sync the counter will also count up. However,
since the Vsync signal is much longer, it will count to a higher
number M. For most video modes, M will be at least 255. So,
Vsync can be detected on the composite sync signal by detecting
when the counter counts to higher than N. The specific count
that triggers detection (T) can be programmed through the
serial register (0fh).
Once Vsync has been detected, there is a similar process to detect
when it goes inactive. At detection, the counter first resets to 0,
then starts counting up when Vsync goes away. Similar to the
previous case, it will detect the absence of Vsync when the
counter reaches the threshold count (T). In this way, it will
reject noise and/or serration pulses. Once Vsync is detected to
be absent, the counter resets to 0 and begins the cycle again.
–30–
REV. 0
AD9886
PCB LAYOUT RECOMMENDATIONS
The AD9886 is a high-precision, high-speed analog device. As
such, to get the maximum performance out of the part it is
important to have a well laid-out board. The following is a guide
for designing a board using the AD9886.
Analog Interface Inputs
Using the following layout techniques on the graphics inputs is
extremely important:
Minimize the trace length running into the graphics inputs. This
is accomplished by placing the AD9886 as close as possible to
the graphics VGA connector. Long input trace lengths are undesirable because they will pick up more noise from the board and
other external sources.
Place the 75 Ω termination resistors as close to the AD9886
chip as possible. Any additional trace length between the termination resistors and the input of the AD9886 increases the
magnitude of reflections, which will corrupt the graphics signal.
Use 75 Ω matched impedance traces. Trace impedances other
than 75 Ω will also increase the chance of reflections.
The AD9886 has very high input bandwidth (330 MHz). While
this is desirable for acquiring a high resolution PC graphics
signal with fast edges, it means that it will also capture any high
frequency noise present. Therefore, it is important to reduce the
amount of noise that gets coupled to the inputs. Avoid running
any digital traces near the analog inputs.
phase and frequency. This can be avoided by careful attention
to regulation, filtering, and bypassing. It is highly desirable to
provide separate regulated supplies for each of the analog circuitry groups (VD and PVD).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which can in turn produce changes in the
regulated analog supply voltage. This can be mitigated by regulating the analog supply, or at least PVD, from a different, cleaner
power source (for example, from a 12 V supply).
It is also recommend to use a single ground plane for the entire
board. Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using
multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result.
In some cases, using separate ground planes is unavoidable. For
those cases, it is recommend to at least place a single ground
plane under the AD9886. The location of the split should be at
the receiver of the digital outputs. For this case it is even more
important to place components wisely because the current loops
will be much longer (current takes the path of least resistance).
An example of a current loop: power plane => AD9886 =>
digital output trace => digital data receiver => digital ground
plane => analog ground plane.
Due to the high bandwidth of the AD9886, sometimes low-pass
filtering the analog inputs can help to reduce noise. (For many
applications, filtering is unnecessary.) Experiments have shown
that placing a series ferrite bead prior to the 75 Ω termination
resistor is helpful in filtering out excess noise. Specifically, the
part used was the # 2508051217Z0 from Fair-Rite, but each
application may work best with a different bead value. Alternately,
placing a 100 Ω to 120 Ω resistor between the 75 Ω termination
resistor and the input coupling capacitor can also benefit.
PLL
Digital Interface Inputs
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance, which require
more current that causes more internal digital noise.
Many of the same techniques that are recommended for the
analog interface inputs should also be used for the digital interface inputs. Most important is to minimize trace lengths, and
then to make the input traces impedances match the input termination (typically 50 Ω).
Power Supply Bypassing
It is recommended to bypass each power supply pin with a
0.1 µF capacitor. The exception is in the case where two or
more supply pins are adjacent to each other. For these groupings of powers/grounds, it is only necessary to have one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the AD9886,
as that interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane => capacitor => power pin. Do not make the power
connection between the capacitor and the power pin. Placing a
via underneath the capacitor pads, down to the power plane, is
generally the best approach.
It is particularly important to maintain low noise and good
stability of PVD (the clock generator supply). Abrupt changes in
PVD can result in similarly abrupt changes in sampling clock
REV. 0
Place the PLL loop filter components as close to the FILT pin
as possible.
Do not place any digital or other high frequency traces near
these components.
Use the values suggested in the data sheet with 10% tolerances
or less.
Outputs (Both Data and Clocks)
Shorter traces reduce the possibility of reflections.
Adding a series resistor of value 50 Ω–200 Ω can suppress reflections, reduce EMI, and reduce the current spikes inside of the
AD9886. If series resistors are used, place them as close to the
AD9886 pins as possible (try not to add vias or extra length to
the output trace in order to get the resistors closer).
If possible, limit the capacitance that each of the digital outputs
drives to less than 10 pF. This can easily be accomplished by
keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance will
increase the current transients inside of the AD9886 creating
more digital noise on its power supplies.
Digital Inputs
The digital inputs on the AD9886 were designed to work with
3.3 V signals.
Any noise that gets onto the Hsync input trace will add jitter to
the system. Therefore, minimize the trace length and do not run
any digital or other high frequency traces near it.
–31–
AD9886
When using an external reference. The REFOUT output, while
unused, still needs to be bypassed with a 0.1 µF capacitor in
order to avoid ringing.
Voltage Reference
Bypass with a 0.1 µF capacitor. Place as close to the AD9886
pin as possible. Make the ground connection as short as possible.
C02383–2.5–1/01 (rev. 0)
REFOUT is easily connected to REFIN with a short trace. Avoid
making this trace any longer than it needs to be.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
160-Lead MQFP
(S-160)
1.238 (31.45)
1.228 (31.20) SQ
1.219 (30.95)
1.106 (28.10)
1.102 (28.00) SQ
1.098 (27.90)
0.160 (4.07)
MAX
0.041 (1.03)
0.035 (0.88)
0.029 (0.73)
120
121
81
80
0.998
(25.35)
BSC SQ
TOP VIEW
(PINS DOWN)
SEATING
PLANE
0.004 (0.10)
MAX
PIN 1
160
0.010 (0.25)
MIN
0.145 (3.67)
0.135 (3.42)
0.125 (3.17)
41
40
1
0.026 (0.65)
BSC*
LEAD PITCH
0.015 (0.38)
0.012 (0.30) LEAD WIDTH
0.009 (0.22)
PRINTED IN U.S.A.
* THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.0047 (0.12) FROM ITS
IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
–32–
REV. 0