SHARC Processor ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC SUMMARY KEY FEATURES—PROCESSOR CORE High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip Integrated multiprocessing features 240-lead thermally enhanced MQFP_PQ4 package, 225-ball plastic ball grid array (PBGA), 240-lead hermetic CQFP package RoHS compliant packages 40 MIPS, 25 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Dual data address generators with modulo and bit-reverse addressing) Efficient program sequencing with zero-overhead looping: Single-cycle loop setup IEEE JTAG Standard 1149.1 Test Access Port and on-chip emulation 32-bit single-precision and 40-bit extended-precision IEEE floating-point data formats or 32-bit fixed-point data format CORE PROCESSOR DAG1 8 4 32 TWO INDEPENDENT DUAL-PORTED BLOCKS PROCESSOR PORT I/O PORT ADDR DATA ADDR DATA DATA ADDR ADDR DATA DAG2 8 4 24 JTAG BLOCK 1 INSTRUCTION CACHE 32 48-BIT B LOCK 0 TIMER DUAL-PORTED SRAM PROGRAM SEQUENCER PM ADDRESS BUS DM ADDRESS BUS IOD 48 24 IOA 17 EXTERNAL PORT ADDR BUS MUX 32 7 TEST AND EMULATION 32 MULTIPROCESSOR INTERFACE PM DATA BUS BUS CONNECT (PX) DM DATA BUS 48 DATA BUS MUX 40/32 S DATA REGISTER FILE MULT 16 40-BIT BARREL SHIFTER HOST PORT DMA CONTROLLER IOP REGISTERS (MEMORY MAPPED) ALU 48 4 6 CONTROL, STATUS AND DATA BUFFERS SERIAL PORTS (2) LINK PORTS (6) 6 36 I/O PROCESSOR Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC PARALLEL COMPUTATIONS Single-cycle multiply and ALU operations in parallel with dual memory read/writes and instruction fetch Multiply with add and subtract for accelerated FFT butterfly computation UP TO 4M BIT ON-CHIP SRAM HOST PROCESSOR INTERFACE TO 16- AND 32-BIT MICROPROCESSORS Host can directly read/write ADSP-2106x internal memory and IOP registers MULTIPROCESSING Glueless connection for scalable DSP multiprocessing architecture Distributed on-chip bus arbitration for parallel bus connect of up to six ADSP-2106xs plus host Six link ports for point-to-point connectivity and array multiprocessing 240 MBps transfer rate over parallel bus 240 MBps transfer rate over link ports Dual-ported for independent access by core processor and DMA OFF-CHIP MEMORY INTERFACING 4 gigawords addressable Programmable wait state generation, page-mode DRAM support DMA CONTROLLER SERIAL PORTS 10 DMA channels for transfers between ADSP-2106x internal memory and external memory, external peripherals, host processor, serial ports, or link ports Background DMA transfers at up to 40 MHz, in parallel with full-speed processor execution Two 40 Mbps synchronous serial ports with companding hardware Independent transmit and receive functions Table 1. ADSP-2106x SHARC Processor Family Features Feature ADSP-21060 ADSP-21062 ADSP-21060L ADSP-21062L ADSP-21060C ADSP-21060LC SRAM 4M bits 2M bits 4M bits 2M bits 4M bits 4M bits Operating Voltage 5V 5V 3.3 V 3.3 V 5V 3.3 V Instruction Rate 33 MHz 40 MHz 33 MHz 40 MHz 33 MHz 40 MHz 33 MHz 40 MHz 33 MHz 40 MHz 33 MHz 40 MHz Package MQFP_PQ4 PBGA MQFP_PQ4 PBGA MQFP_PQ4 PBGA MQFP_PQ4 PBGA CQFP CQFP Rev. H | Page 2 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CONTENTS Summary ............................................................... 1 Electrical Characteristics (3.3 V) ............................. 18 General Description ................................................. 4 Internal Power Dissipation (3.3 V) .......................... 19 SHARC Family Core Architecture ............................ 4 External Power Dissipation (3.3 V) .......................... 20 Memory and I/O Interface Features ........................... 5 Absolute Maximum Ratings ................................... 20 Development Tools ............................................... 8 ESD Caution ...................................................... 21 Additional Information .......................................... 9 Package Marking Information ................................ 21 Related Signal Chains ............................................ 9 Timing Specifications ........................................... 21 Pin Function Descriptions ........................................ 10 Test Conditions .................................................. 48 Target Board Connector for EZ-ICE Probe ................ 13 Environmental Conditions .................................... 51 ADSP-21060/ADSP-21062 Specifications ..................... 15 225-Ball PBGA Ball Configuration .............................. 52 Operating Conditions (5 V) .................................... 15 240-Lead MQFP_PQ4/CQFP Pin Configuration ............ 54 Electrical Characteristics (5 V) ................................ 15 Outline Dimensions ................................................ 56 Internal Power Dissipation (5 V) ............................. 16 Surface-Mount Design .......................................... 61 External Power Dissipation (5 V) ............................. 17 Ordering Guide ..................................................... 62 ADSP-21060L/ADSP-21062L Specifications .................. 18 Operating Conditions (3.3 V) ................................. 18 REVISION HISTORY 3/13—Rev. G to Rev. H Updated Development Tools .......................................8 Corrected the power dissipation equation from PTOTAL = PEXT + (IDDIN2 5.0 V) to PTOTAL = PEXT + (IDDIN2 3.3 V) External Power Dissipation (3.3 V) ............................. 20 Rev. H | Page 3 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC GENERAL DESCRIPTION The ADSP-2106x SHARC®—Super Harvard Architecture Computer—is a 32-bit signal processing microcomputer that offers high levels of DSP performance. The ADSP-2106x builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus. • Serial ports and link ports • JTAG Test Access Port ADSP-2106x 4 The ADSP-2106x SHARC represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including up to 4M bit SRAM memory (see Table 1), a host processor interface, DMA controller, serial ports and link port, and parallel bus connectivity for glueless DSP multiprocessing. LINK DEVICES (6 MAX) (OPTIONAL) Table 2. Benchmarks (at 40 MHz) Benchmark Algorithm 1024 Point Complex FFT (Radix 4, with reversal) FIR Filter (per tap) IIR Filter (per biquad) Divide (y/x) Inverse Square Root DMA Transfer Rate Speed 0.46 s 25 ns 100 ns 150 ns 225 ns 240 Mbytes/s EBOOT ADDR LBOOT DATA FLAG3–0 ADDR31–0 ADDR TIMEXP DATA47–0 DATA MEMORYMAPPED OE DEVICES WE (OPTIONAL) ACK LxCLK LxACK LxDAT3–0 SERIAL DEVICE (OPTIONAL) TCLK0 RCLK0 TFS0 RSF0 DT0 DR0 SERIAL DEVICE (OPTIONAL) TCLK1 RCLK1 TFS1 RSF1 DT1 DR1 Cycles 18,221 RPBA ID2–0 RESET 1 4 6 9 BOOT EPROM (OPTIONAL) IRQ2–0 RD WR ACK CS MS3–0 PAGE SBTS ADRCLK DMAR1–2 DATA 3 CS BMS ADDRESS Fabricated in a high speed, low power CMOS process, the ADSP-2106x has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle. Table 2 shows performance benchmarks for the ADSP-2106x. CLKIN CONTROL 1 ⫻ CLOCK DMA DEVICE (OPTIONAL) DATA DMAG1–2 CS HBR HBG REDY HOST PROCESSOR INTERFACE (OPTIONAL) BR1–6 ADDR PA DATA JTAG 6 Figure 2. ADSP-2106x System Sample Configuration SHARC FAMILY CORE ARCHITECTURE The ADSP-2106x continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. The block diagram on Page 1 illustrates the following architectural features: • Computation units (ALU, multiplier and shifter) with a shared data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle • Interval timer • On-chip SRAM • External port for interfacing to off-chip memory and peripherals • Host port and multiprocessor Interface The ADSP-2106x includes the following architectural features of the ADSP-21000 family core. Independent, Parallel Computation Units The arithmetic/logic unit (ALU), multiplier and shifter all perform single-cycle instructions. The three units are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. These computation units support IEEE 32-bit singleprecision floating-point, extended precision 40-bit floatingpoint, and 32-bit fixed-point data formats. Data Register File A general–purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results. This 10-port, 32-register (16 primary, 16 secondary) register file, combined with the ADSP-21000 Harvard architecture, allows unconstrained data flow between computation units and internal memory. • DMA controller Rev. H | Page 4 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Single-Cycle Fetch of Instruction and Two Operands The ADSP-2106x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on Page 1). With its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from the cache), all in a single cycle. Instruction Cache The ADSP-2106x includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and FFT butterfly processing. Data Address Generators with Hardware Circular Buffers The ADSP-2106x’s two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-2106x contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance and simplifying implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-2106x can conditionally execute a multiply, an add, a subtract and a branch, all in a single instruction. MEMORY AND I/O INTERFACE FEATURES The ADSP-2106x processors add the following architectural features to the SHARC family core. A 16-bit floating-point storage format is supported, which effectively doubles the amount of data that can be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data, using the DM bus for transfers, and the other block stores instructions and data, using the PM bus for transfers. Using the DM bus and PM bus in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. Single-cycle execution is also maintained when one of the data operands is transferred to or from off-chip, via the ADSP-2106x’s external port. On-Chip Memory and Peripherals Interface The ADSP-2106x’s external port provides the processor’s interface to off-chip memory and peripherals. The 4-gigaword offchip address space is included in the ADSP-2106x’s unified address space. The separate on-chip buses—for PM addresses, PM data, DM addresses, DM data, I/O addresses, and I/O data—are multiplexed at the external port to create an external system bus with a single 32-bit address bus and a single 48-bit (or 32-bit) data bus. Addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The ADSP-2106x provides programmable memory wait states and external memory acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold and disable time requirements. Host Processor Interface Dual-Ported On-Chip Memory The ADSP-21062/ADSP-21062L contains two megabits of onchip SRAM, and the ADSP-21060/ADSP-21060L contains 4M bits of on-chip SRAM. The internal memory is organized as two equal sized blocks of 1M bit each for the ADSP-21062/ ADSP-21062L and two equal sized blocks of 2M bits each for the ADSP-21060/ADSP-21060L. Each can be configured for different combinations of code and data storage. Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor or DMA controller. The dual-ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle. On the ADSP-21062/ADSP-21062L, the memory can be configured as a maximum of 64k words of 32-bit data, 128k words of 16-bit data, 40k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, or 48-bit words. Rev. H | On the ADSP-21060/ADSP-21060L, the memory can be configured as a maximum of 128k words of 32-bit data, 256k words of 16-bit data, 80k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to four megabits. All of the memory can be accessed as 16-bit, 32-bit or 48-bit words. The ADSP-2106x’s host interface allows easy connection to standard microprocessor buses, both 16-bit and 32-bit, with little additional hardware required. Asynchronous transfers at speeds up to the full clock rate of the processor are supported. The host interface is accessed through the ADSP-2106x’s external port and is memory-mapped into the unified address space. Four channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor requests the ADSP-2106x’s external bus with the host bus request (HBR), host bus grant (HBG), and ready (REDY) signals. The host can directly read and write the internal memory of the ADSP-2106x, and can access the DMA channel setup and mailbox registers. Vector interrupt support is provided for efficient execution of host commands. Page 5 of 64 | March 2013 ADDRESS DATA DATA RESET ADDRESS ADSP-2106x #3 CLKIN CONTROL ADSP-2106x #6 ADSP-2106x #5 ADSP-2106x #4 CONTROL ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADDR31–0 DATA47–0 RPBA 3 ID2–0 CONTROL 011 BR1–2, BR4–6 5 BR3 ADSP-2106x #2 CLKIN ADDR31–0 RESET DATA47–0 RPBA 3 ID2–0 CONTROL 010 CPA BR1, BR3–6 BR2 5 ADSP-2106x #1 CLKIN RESET ADDR DATA47–0 DATA RDx ID2–0 WRx ACK MS3–0 CONTROL RPBA 3 001 ADDR31–0 OE WE ACK CS BMS PAGE CS ADDR SBTS BUS PRIORITY RESET CLOCK GLOBAL MEMORY AND PERIPHERAL (OPTIONAL) BOOT EPROM (OPTIONAL) DATA CS HBR HBG REDY CPA BR2–6 BR1 HOST PROCESSOR INTERFACE (OPTIONAL) ADDR 5 DATA Figure 3. Shared Memory Multiprocessing System Rev. H | Page 6 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC control two DMA channels using DMA request/grant lines (DMAR1–2, DMAG1–2). Other DMA features include interrupt generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers. DMA Controller The ADSP-2106x’s on-chip DMA controller allows zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. Multiprocessing The ADSP-2106x offers powerful features tailored to multiprocessor DSP systems. The unified address space (see Figure 4) allows direct interprocessor accesses of each ADSP-2106x’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-2106xs and a host processor. Master processor changeover incurs only one cycle of overhead. Bus arbitration is selectable as either fixed or rotating priority. Bus lock allows indivisible read-modify-write sequences for semaphores. A vector interrupt is provided for interprocessor commands. Maximum throughput for interprocessor data transfer is 240M bytes/s over the link ports or external port. Broadcast writes allow simultaneous transmission of data to all ADSP-2106xs and can be used to implement reflective semaphores. DMA transfers can occur between the ADSP-2106x’s internal memory and external memory, external peripherals, or a host processor. DMA transfers can also occur between the ADSP2106x’s internal memory and its serial ports or link ports. DMA transfers between external memory and external peripheral devices are another option. External bus packing to 16-, 32-, or 48-bit words is performed during DMA transfers. Ten channels of DMA are available on the ADSP-2106x—two via the link ports, four via the serial ports, and four via the processor’s external port (for either host processor, other ADSP-2106xs, memory, or I/O transfers). Four additional link port DMA channels are shared with Serial Port 1 and the external port. Programs can be downloaded to the ADSP-2106x using DMA transfers. Asynchronous off-chip peripherals can ADDRESS ADDRESS 0x0000 0000 0x0040 0000 IOP REGISTERS INTERNAL MEMORY SPACE NORMAL WORD ADDRESSING (32-BIT DATA WORDS 48-BIT INSTRUCTION WORDS) 0x0002 0000 BANK 0 0x0004 0000 MS0 SRAM (OPTIONAL) SHORT WORD ADDRESSING (16-BIT DATA WORDS) 0x0008 0000 INTERNAL MEMORY SPACE WITH ID = 001 BANK 1 MS1 BANK 2 MS2 BANK 3 MS3 0x0010 0000 INTERNAL MEMORY SPACE WITH ID = 010 0x0018 0000 MULTIPROCESSOR MEMORY SPACE EXTERNAL MEMORY SPACE INTERNAL MEMORY SPACE WITH ID = 011 0x0012 0000 INTERNAL MEMORY SPACE WITH ID = 100 0x0028 0000 INTERNAL MEMORY SPACE WITH ID = 101 0x0030 0000 INTERNAL MEMORY SPACE WITH ID = 110 0x0038 0000 BROADCAST WRITE TO ALL ADSP-21061s NONBANKED 0x003F FFFF 0x0FFF FFFF NOTE: BANK SIZES ARE SELECTED BY MSIZE BITS IN THE SYSCON REGISTER Figure 4. Memory Map Rev. H | Page 7 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Link Ports The ADSP-2106x features six 4-bit link ports that provide additional I/O capabilities. The link ports can be clocked twice per cycle, allowing each to transfer eight bits of data per cycle. Linkport I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. The link ports can operate independently and simultaneously, with a maximum data throughput of 240M bytes/s. Link port data is packed into 32- or 48-bit words, and can be directly read by the core processor or DMA-transferred to on-chip memory. Each link port has its own double-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are programmable as either transmit or receive. Program Booting The internal memory of the ADSP-2106x can be booted at system power-up from an 8-bit EPROM, a host processor, or through one of the link ports. Selection of the boot source is controlled by the BMS (boot memory select), EBOOT (EPROM Boot), and LBOOT (link/host boot) pins. 32-bit and 16-bit host processors can be used for booting. The processor also supports a no-boot mode in which instruction execution is sourced from the external memory. DEVELOPMENT TOOLS Analog Devices supports its processors with a complete line of software and hardware development tools, including integrated development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products, emulators, and a wide variety of software add-ins. Integrated Development Environments (IDEs) For C/C++ software writing and editing, code generation, and debug support, Analog Devices offers two IDEs. The newest IDE, CrossCore Embedded Studio, is based on the EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors, including multicore devices. CrossCore Embedded Studio seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For more information visit www.analog.com/cces. The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore Embedded Studio. This IDE includes the Analog Devices VDK real time operating system and an open source TCP/IP stack. For more information visit www.analog.com/visualdsp. Note that VisualDSP++ will not support future Analog Devices processors. emulation capabilities and other evaluation and development features. Also available are various EZ-Extenders®, which are daughter cards delivering additional specialized functionality, including audio and video processing. For more information visit www.analog.com and search on “ezkit” or “ezextender”. EZ-KIT Lite Evaluation Kits For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation version of the available IDE(s), a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user’s PC, enabling the chosen IDE evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of the on-board Flash device to store user-specific boot code, enabling standalone operation. With the full version of CrossCore Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices processors. Software Add-Ins for CrossCore Embedded Studio Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through the CrossCore Embedded Studio IDE once the add-in is installed. Board Support Packages for Evaluation Hardware Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called Board Support Packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download area of the product web page. Middleware Packages Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/IP stacks. For more information see the following web pages: • www.analog.com/ucos3 • www.analog.com/ucfs • www.analog.com/ucusbd • www.analog.com/lwip EZ-KIT Lite Evaluation Board For processor evaluation, Analog Devices provides wide range of EZ-KIT Lite® evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip Rev. H | Page 8 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Algorithmic Modules To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are available for use with both CrossCore Embedded Studio and VisualDSP++. For more information visit www.analog.com and search on “Blackfin software modules” or “SHARC software modules”. The Application Signal Chains page in the Circuits from the LabTM site (http://www.analog.com/signalchains) provides: • Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications • Drill down links for components in each chain to selection guides and application information • Reference designs applying best practice design techniques Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports connection of the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2106x architecture and functionality. For detailed information on the ADSP-21000 family core architecture and instruction set, refer to the ADSP-2106x SHARC User’s Manual, Revision 2.1. RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the Glossary of EE Terms on the Analog Devices website. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. Rev. H | Page 9 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC PIN FUNCTION DESCRIPTIONS The ADSP-2106x pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to VDD or GND, except for ADDR31–0, DATA47–0, FLAG3–0, and inputs that have internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx, TCLKx, RCLKx, LxDAT3–0, LxCLK, LxACK, TMS, and TDI)—these pins can be left floating. These pins have a logic-level hold circuit that prevents the input from floating internally. Table 3. Pin Descriptions Pin ADDR31–0 Type I/O/T Function External Bus Address. The ADSP-2106x outputs addresses for external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs addresses for read/write of the internal memory or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a host processor or multiprocessing bus master is reading or writing its internal memory or IOP registers. DATA47–0 I/O/T External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit singleprecision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short word data is transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over bits 23–16. Pull-up resistors on unused DATA pins are not necessary. O/T Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of external MS3–0 memory. Memory bank size must be defined in the ADSP-2106x’s system control register (SYSCON). The MS3–0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring, the MS3–0 lines are inactive; they are active however when a conditional memory access instruction is executed, whether or not the condition is true. MS0 can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system the MS3–0 lines are output by the bus master. RD I/O/T Memory Read Strobe. This pin is asserted (low) when the ADSP-2106x reads from external memory devices or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-2106xs) must assert RD to read from the ADSP-2106x’s internal memory. In a multiprocessing system, RD is output by the bus master and is input by all other ADSP-2106xs. I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x writes to external memory devices WR or to the internal memory of other ADSP-2106xs. External devices must assert WR to write to the ADSP2106x’s internal memory. In a multiprocessing system, WR is output by the bus master and is input by all other ADSP-2106xs. PAGE O/T DRAM Page Boundary. The ADSP-2106x asserts this pin to signal that an external DRAM page boundary has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system, PAGE is output by the bus master ADRCLK O/T Clock Output Reference. In a multiprocessing system, ADRCLK is output by the bus master. SW I/O/T Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous memory devices (including other ADSP-2106xs). The ADSP-2106x asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW is asserted at the same time as the address output. A host processor using synchronous writes must assert this pin when writing to the ADSP-2106x(s). A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave) Rev. H | Page 10 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 3. Pin Descriptions (Continued) Pin ACK Type I/O/S Function Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-2106x deasserts ACK as an output to add waitstates to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-2106x deasserts the bus master’s ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it was last driven. I/S Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data, SBTS selects, and strobes in a high impedance state for the following cycle. If the ADSP-2106x attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-2106x deadlock, or used with a DRAM controller. IRQ2–0 I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive. FLAG3–0 I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be tested as a condition. As an output, they can be used to signal external peripherals. TIMEXP O Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero. HBR I/A Host Bus Request. This pin must be asserted by a host processor to request control of the ADSP-2106x’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address, data, select and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus requests BR6–1 in a multiprocessing system. HBG I/O Host Bus Grant. Acknowledges a bus request, indicating that the host processor may take control of the external bus. HBG is asserted (held low) by the ADSP-2106x until HBR is released. In a multiprocessing system, HBG is output by the ADSP-2106x bus master and is monitored by all others. CS I/A Chip Select. Asserted by host processor to select the ADSP-2106x. REDY O (O/D) Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchronous access of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted. DMAR2–1 I/A DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 8). DMAG2–1 O/T DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 8). BR6–1 I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-ship. An ADSP-2106x only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins should be pulled high; the processor’s own BRx line must not be pulled high or low because it is an output. ID2–0 O (O/D) Multiprocessing ID. Determines which multiprocessing bus request (BR1– BR6) is used by ADSP-2106x. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor systems. These lines are a system configuration selection that should be hardwired or changed at reset only. RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x. CPA I/O (O/D) Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain output that is connected to all ADSP-2106xs in the system. The CPA pin has an internal 5 k pull-up resistor. If core access priority is not required in a system, the CPA pin should be left unconnected. DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k internal pull-up resistor. DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k internal pull-up resistor. TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k internal pull-up resistor. RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k internal pull-up resistor. A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave) Rev. H | Page 11 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 3. Pin Descriptions (Continued) Pin TFSx RFSx LxDAT3–0 Type I/O I/O I/O Function Transmit Frame Sync (Serial Ports 0, 1). Receive Frame Sync (Serial Ports 0, 1). Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 k internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register. LxCLK I/O Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 k internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register. LxACK I/O Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 k internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register. EBOOT I EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See the table in the BMS pin description below. This signal is a system configuration selection that should be hardwired. LBOOT I Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. When LBOOT is low, the ADSP-2106x is configured for host processor booting or no booting. See the table in the BMS pin description below. This signal is a system configuration selection that should be hardwired. I/OT Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1, LBOOT = 0). BMS In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting will occur and that ADSP-2106x will begin executing instructions from external memory. See table below. This input is a system configuration selection that should be hardwired. *Three-statable only in EPROM boot mode (when BMS is an output). EBOOT LBOOT BMS Booting Mode 1 0 Output EPROM (Connect BMS to EPROM chip select.) 0 0 1 (Input) Host Processor 0 1 1 (Input) Link Port 0 0 0 (Input) No Booting. Processor executes from external memory. 0 1 0 (Input) Reserved 1 1 x (Input) Reserved CLKIN I Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN. CLKIN should not be halted, changed, or operated below the minimum specified frequency. RESET I/A Processor Reset. Resets the ADSP-2106x to a known state and begins program execution at the program memory location specified by the hardware reset vector address. This input must be asserted (low) at power-up. TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan. TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k internal pull-up resistor. TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k internal pull-up resistor. TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path. TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2106x. TRST has a 20 k internal pull-up resistor. EMU O Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only. ICSA O Reserved, leave unconnected. VDD P Power Supply; nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices. (30 pins). GND G Power Supply Return. (30 pins). NC Do Not Connect. Reserved pins which must be left open and unconnected. A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave) Rev. H | Page 12 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TARGET BOARD CONNECTOR FOR EZ-ICE PROBE The ADSP-2106x EZ-ICE® Emulator uses the IEEE 1149.1JTAG test access port of the ADSP-2106x to monitor and control the target board processor during emulation. The EZ-ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST, TDI, TDO, EMU, and GND signals be made accessible on the target system via a 14-pin connector (a 2-row 7-pin strip header) such as that shown in Figure 5. The EZ-ICE probe plugs directly onto this connector for chip-on-board emulation. You must add this connector to your target board design if you intend to use the ADSP-2106x EZ-ICE. The total trace length between the EZ-ICE connector and the furthest device sharing the EZ-ICE JTAG pin should be limited to 15 inches maximum for guaranteed operation. This length restriction must include EZ-ICE JTAG signals that are routed to one or more ADSP-2106x devices, or a combination of ADSP-2106x devices and other JTAG devices on the chain. The JTAG signals are terminated on the EZ-ICE probe as shown in Table 4. Table 4. Core Instruction Rate/CLKIN Ratio Selection Signal TMS TCK TRST1 TDI TDO CLKIN EMU 1 GND 1 2 3 4 5 TMS 7 8 BTCK TCK 9 BTRST 10 TRST 9 11 12 BTDI GND Connecting CLKIN to Pin 4 of the EZ-ICE header is optional. The emulator only uses CLKIN when directed to perform operations such as starting, stopping, and single-stepping multiple ADSP-2106xs in a synchronous manner. If you do not need these operations to occur synchronously on the multiple processors, simply tie Pin 4 of the EZ-ICE header to ground. 6 BTMS TDI 13 14 TRST is driven low until the EZ-ICE probe is turned on by the emulator at software start-up. After software start-up, is driven high. Figure 6 shows JTAG scan path connections for systems that contain multiple ADSP-2106x processors. EMU GND KEY (NO PIN) Termination Driven Through 22 Resistor (16 mA Driver) Driven at 10 MHz Through 22 Resistor (16 mA Driver) Active Low Driven Through 22 Resistor (16 mA Driver) (Pulled-Up by On-Chip 20 k Resistor) Driven by 22 Resistor (16 mA Driver) One TTL Load, Split Termination (160/220) One TTL Load, Split Termination (160/220) Active Low 4.7 k Pull-Up Resistor, One TTL Load (Open-Drain Output from the DSP) TDO TOP VIEW Figure 5. Target Board Connector for ADSP-2106x EZ-ICE Emulator (Jumpers in Place) The 14-pin, 2-row pin strip header is keyed at the Pin 3 location—Pin 3 must be removed from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 0.1 inches. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec. The BTMS, BTCK, BTRST, and BTDI signals are provided so that the test access port can also be used for board-level testing. When the connector is not being used for emulation, place jumpers on the Bxxx pins as shown in Figure 5. If you are not going to use the test access port for board testing, tie BTRST to GND and tie or pull up BTCK to VDD. The TRST pin must be asserted (pulsed low) after power-up (through BTRST on the connector) or held low for proper operation of the ADSP2106x. None of the Bxxx pins (Pins 5, 7, 9, and 11) are connected on the EZ-ICE probe. Rev. H | If synchronous multiprocessor operations are needed and CLKIN is connected, clock skew between the multiple ADSP-2106x processors and the CLKIN pin on the EZ-ICE header must be minimal. If the skew is too large, synchronous operations may be off by one or more cycles between processors. For synchronous multiprocessor operation TCK, TMS, CLKIN, and EMU should be treated as critical signals in terms of skew, and should be laid out as short as possible on your board. If TCK, TMS, and CLKIN are driving a large number of ADSP-2106xs (more than eight) in your system, then treat them as a “clock tree” using multiple drivers to minimize skew. (See Figure 7 and “JTAG Clock Tree” and “Clock Distribution” in the “High Frequency Design Considerations” section of the ADSP-2106x User’s Manual, Revision 2.1.) If synchronous multiprocessor operations are not needed (i.e., CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU and TRST are not critical signals in terms of skew. For complete information on the SHARC EZ-ICE, see the ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference. Page 13 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TR ST TRST EMU EM U TRST TMS TCK TDO TDI TCK TDO TDI TRST EMU TCK EZ-ICE JTAG CONNECTOR OTHER JTAG CONTROLLER TDO TDI TMS TDI ADSP-2106x n TMS JTAG DEVICE (OPTIONAL) ADSP-2106x #1 TCK TMS EMU TRST TDO CLKIN OPTIONAL Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems * TDI EMU * TDI TDO TDI TDO TDI TDO TDI TDO TDI TDO TDI TDO 5k⍀ 5k⍀ TCK TMS TRST TDO CLKIN EMU *OPEN-DRAIN DRIVER OR EQUIVALENT, i.e., Figure 7. JTAG Clock Tree for Multiple ADSP-2106x Systems Rev. H | Page 14 of 64 | March 2013 SYSTEM CLKIN ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADSP-21060/ADSP-21062 SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS (5 V) A Grade Parameter VDD TCASE VIH11 VIH22 VIL 1, 2 Description Supply Voltage Case Operating Temperature High Level Input Voltage @ VDD = Max High Level Input Voltage @ VDD = Max Low Level Input Voltage @ VDD = Min Min 4.75 –40 2.0 2.2 –0.5 Max 5.25 +85 VDD + 0.5 VDD + 0.5 +0.8 C Grade Min 4.75 –40 2.0 2.2 –0.5 Max 5.25 +100 VDD + 0.5 VDD + 0.5 +0.8 K Grade Min 4.75 –40 2.0 2.2 –0.5 Max 5.25 +85 VDD + 0.5 VDD + 0.5 +0.8 Unit V C V V V 1 Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1. 2 Applies to input pins: CLKIN, RESET, TRST. ELECTRICAL CHARACTERISTICS (5 V) Parameter VOH1, 2 VOL1, 2 IIH3, 4 IIL3 IILP4 IOZH5, 6, 7, 8 IOZL5, 9 IOZHP9 IOZLC7 IOZLA10 IOZLAR8 IOZLS6 CIN11, 12 Description High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current Low Level Input Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Input Capacitance Test Conditions @ VDD = Min, IOH = –2.0 mA @ VDD = Min, IOL = 4.0 mA @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = 1.5 V @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = 0 V fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V 1 Min 4.1 Max 0.4 10 10 150 10 10 350 1.5 350 4.2 150 4.7 Unit V V μA μA μA μA μA μA mA μA mA μA pF Applies to output and bidirectional pins: DATA47–0, ADDR31-0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS, TDO, EMU, ICSA. 2 See Figure 31, Output Drive Currents 5 V, for typical drive current capabilities. 3 Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK. 4 Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI. 5 Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx, TDO, EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.) 6 Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1. 7 Applies to CPA pin. 8 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL is not requesting bus mastership). 9 Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK. 10 Applies to ACK pin when keeper latch enabled. 11 Applies to all signal pins. 12 Guaranteed but not tested. Rev. H | Page 15 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC INTERNAL POWER DISSIPATION (5 V) These specifications apply to the internal power portion of VDD only. For a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissipation Measurements.” Specifications are based on the operating scenarios. Operation Instruction Type Instruction Fetch Core memory Access Internal Memory DMA Peak Activity (IDDINPEAK) Multifunction Cache 2 Per Cycle (DM and PM) 1 Per Cycle High Activity (IDDINHIGH) Multifunction Internal Memory 1 Per Cycle (DM) 1 Per 2 Cycles Low Activity (IDDINLOW) Single Function Internal Memory None 1 Per 2 Cycles To estimate power consumption for a specific application, use the following equation where% is the amount of time your program spends in that state: %PEAK IDDINPEAK +%HIGH IDDINHIGH +%LOW IDDINLOW + %IDLE IDDIDLE = Power Consumption Parameter IDDINPEAK Supply Current (Internal)1 IDDINHIGH Supply Current (Internal)2 IDDINLOW Supply Current (Internal)2 IDDIDLE Supply Current (Idle)3 Test Conditions tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max VDD = Max Max 745 850 575 670 340 390 200 1 Unit mA mA mA mA mA mA mA The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical applications are less than specified. 2 IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code. 3 Idle denotes ADSP-2106x state during execution of IDLE instruction. Rev. H | Page 16 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC EXTERNAL POWER DISSIPATION (5 V) Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Internal power dissipation is calculated in the following way: drive high and low at a maximum rate of 1/(2tCK). The write strobe can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects can switch on each cycle. Example: Estimate PEXT with the following assumptions: • A system with one bank of external data memory RAM (32-bit) PINT = IDDIN VDD • Four 128K 8 RAM chips are used, each with a load of 10 pF The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: • External data memory writes occur every other cycle, a rate of 1/(4tCK), with 50% of the pins switching • the number of output pins that switch during each cycle (O) • The instruction cycle rate is 40 MHz (tCK = 25 ns) • the maximum frequency at which they can switch (f) The PEXT equation is calculated for each class of pins that can drive: • their load capacitance (C) A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: • their voltage swing (VDD) and is calculated by: PTOTAL = PEXT + (IDDIN2 5.0 V) PEXT = O C VDD2 f Note that the conditions causing a worst-case PEXT are different from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. The load capacitance should include the processor’s package capacitance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can Table 5. External Power Calculations (5 V Devices) Pin Type Address MS0 WR Data ADDRCLK No. of Pins 15 1 1 32 1 % Switching 50 0 – 50 – Rev. H | C 44.7 pF 44.7 pF 44.7 pF 14.7 pF 4.7 pF Page 17 of 64 | f 10 MHz 10 MHz 20 MHz 10 MHz 20 MHz March 2013 VDD2 25 V 25 V 25 V 25 V 25 V = PEXT = 0.084 W = 0.000 W = 0.022 W = 0.059 W = 0.002 W PEXT = 0.167 W ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADSP-21060L/ADSP-21062L SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS (3.3 V) A Grade Parameter VDD TCASE VIH11 VIH22 VIL 1, 2 Description Supply Voltage Case Operating Temperature High Level Input Voltage @ VDD = Max High Level Input Voltage @ VDD = Max Low Level Input Voltage @ VDD = Min Min 3.15 –40 2.0 2.2 –0.5 Max 3.45 +85 VDD + 0.5 VDD + 0.5 +0.8 C Grade Min 3.15 –40 2.0 2.2 –0.5 Max 3.45 +100 VDD + 0.5 VDD + 0.5 +0.8 K Grade Min 3.15 –40 2.0 2.2 –0.5 Max 3.45 +85 VDD + 0.5 VDD + 0.5 +0.8 Unit V C V V V 1 Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1. 2 Applies to input pins: CLKIN, RESET, TRST. ELECTRICAL CHARACTERISTICS (3.3 V) Parameter VOH1, 2 VOL1, 2 IIH3, 4 IIL3 IILP4 IOZH5, 6, 7, 8 IOZL5, 9 IOZHP9 IOZLC7 IOZLA10 IOZLAR8 IOZLS6 CIN11, 12 Description High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current Low Level Input Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Three-State Leakage Current Input Capacitance Test Conditions @ VDD = Min, IOH = –2.0 mA @ VDD = Min, IOL = 4.0 mA @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = VDD Max @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = 1.5 V @ VDD = Max, VIN = 0 V @ VDD = Max, VIN = 0 V fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V 1 Min 2.4 Max 0.4 10 10 150 10 10 350 1.5 350 4.2 150 4.7 Unit V V μA μA μA μA μA μA mA μA mA μA pF Applies to output and bidirectional pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2, BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS, TDO, EMU, ICSA. 2 See Figure 35, Output Drive Currents 3.3 V, for typical drive current capabilities. 3 Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK. 4 Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI. 5 Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx, TDO, EMU. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.) 6 Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1. 7 Applies to CPA pin. 8 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL is not requesting bus mastership). 9 Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK. 10 Applies to ACK pin when keeper latch enabled. 11 Applies to all signal pins. 12 Guaranteed but not tested. Rev. H | Page 18 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC INTERNAL POWER DISSIPATION (3.3 V) These specifications apply to the internal power portion of VDD only. For a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissipation Measurements.” Specifications are based on the operating scenarios. Operation Instruction Type Instruction Fetch Core memory Access Internal Memory DMA Peak Activity (IDDINPEAK) Multifunction Cache 2 Per Cycle (DM and PM) 1 Per Cycle High Activity (IDDINHIGH) Multifunction Internal Memory 1 Per Cycle (DM) 1 Per 2 Cycles Low Activity (IDDINLOW) Single Function Internal Memory None 1 Per 2 Cycles To estimate power consumption for a specific application, use the following equation where % is the amount of time your program spends in that state: %PEAK IDDINPEAK + %HIGH IDDINHIGH + %LOW IDDINLOW + %IDLE IDDIDLE = Power Consumption Parameter IDDINPEAK Supply Current (Internal)1 IDDINHIGH Supply Current (Internal)2 IDDINLOW Supply Current (Internal)2 IDDIDLE Supply Current (Idle)3 Test Conditions tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max tCK = 30 ns, VDD = Max tCK = 25 ns, VDD = Max VDD = Max Max 540 600 425 475 250 275 180 1 Unit mA mA mA mA mA mA mA The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical applications are less than specified. 2 IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code. 3 Idle denotes ADSP-2106xL state during execution of IDLE instruction. Rev. H | Page 19 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC EXTERNAL POWER DISSIPATION (3.3 V) drive high and low at a maximum rate of 1/(2tCK). The write strobe can switch every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects can switch on each cycle. Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Internal power dissipation is calculated in the following way: Example: Estimate PEXT with the following assumptions: • A system with one bank of external data memory RAM (32-bit) PINT = IDDIN VDD • Four 128K 8 RAM chips are used, each with a load of 10 pF The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: • External data memory writes occur every other cycle, a rate of 1/(4tCK), with 50% of the pins switching • the number of output pins that switch during each cycle (O) • The instruction cycle rate is 40 MHz (tCK = 25 ns) • the maximum frequency at which they can switch (f) The PEXT equation is calculated for each class of pins that can drive: • their load capacitance (C) A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation: • their voltage swing (VDD) and is calculated by: PTOTAL = PEXT + (IDDIN2 3.3 V) PEXT = O C VDD2 f Note that the conditions causing a worst-case PEXT are different from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. The load capacitance should include the processor’s package capacitance (CIN). The switching frequency includes driving the load high and then back low. Address and data pins can Table 6. External Power Calculations (3.3 V Devices) Pin Type Address MS0 WR Data ADDRCLK No. of Pins 15 1 1 32 1 C 44.7 pF 44.7 pF 44.7 pF 14.7 pF 4.7 pF % Switching 50 0 – 50 – f 10 MHz 10 MHz 20 MHz 10 MHz 20 MHz VDD2 10.9 V 10.9 V 10.9 V 10.9 V 10.9 V = PEXT = 0.037 W = 0.000 W = 0.010 W = 0.026 W = 0.001 W PEXT = 0.074 W ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed Table 7 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Absolute Maximum Ratings ADSP-21060/ADSP-21060C ADSP-21062 5V –0.3 V to +7.0 V –0.5 V to VDD + 0.5 V –0.5 V to VDD + 0.5 V 200 pF –65C to +150C 280C 130C Parameter Supply Voltage (VDD) Input Voltage Output Voltage Swing Load Capacitance Storage Temperature Range Lead Temperature (5 seconds) Junction Temperature Under Bias Rev. H | Page 20 of 64 | March 2013 ADSP-21060L/ADSP-21060LC ADSP-21062L 3.3 V –0.3 V to +4.6 V –0.5 V to VDD +0.5 V –0.5 V to VDD + 0.5 V 200 pF –65C to +150C 280C 130C ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ESD CAUTION TIMING SPECIFICATIONS ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. The ADSP-2106x processors are available at maximum processor speeds of 33 MHz (–133), and 40 MHz (–160). The timing specifications are based on a CLKIN frequency of 40 MHz tCK = 25 ns). The DT derating factor enables the calculation for timing specifications within the min to max range of the tCK specification (see Table 9). DT is the difference between the derated CLKIN period and a CLKIN period of 25 ns: DT = tCK – 25 ns PACKAGE MARKING INFORMATION Figure 8 and Table 8 provide information on detail contained within the package marking for the ADSP-2106x processors (actual marking format may vary). For a complete listing of product availability, see Ordering Guide on Page 62. Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times. For voltage reference levels, see Figure 28 on Page 48 under Test Conditions. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. (O/D) = Open Drain, (A/D) = Active Drive. a ADSP-2106x tppZccc Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. vvvvvv.x n.n yyww country_of_origin S Figure 8. Typical Package Brand Table 8. Package Brand Information Brand Key t pp Z ccc vvvvvv.x n.n yyww Field Description Temperature Range Package Type Lead (Pb) Free Option See Ordering Guide Assembly Lot Code Silicon Revision Date Code Rev. H | Page 21 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Clock Input Table 9. Clock Input Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) 1 ADSP-21060 ADSP-21062 40 MHz, 5 V Min Max ADSP-21060 ADSP-21062 33 MHz, 5 V Min Max ADSP-21060L ADSP-21062L 40 MHz, 3.3 V Min Max ADSP-21060L ADSP-21062L 33 MHz, 3.3 V Min Max 25 7 5 30 7 5 25 8.75 5 30 8.751 5 100 100 3 100 3 3 Unit 100 ns ns ns ns 3 For the ADSP-21060LC, this specification is 9.5 ns min. tCK CLKIN tCKH tCKL Figure 9. Clock Input Reset Table 10. Reset Parameter Timing Requirements tWRST RESET Pulse Width Low1 tSRST RESET Setup Before CLKIN High2 Min 5 V and 3.3 V Max 4tCK 14 + DT/2 tCK 1 Unit ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). 2 Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset. CLKIN tSRST tWRST RESET Figure 10. Reset Rev. H | Page 22 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Interrupts Table 11. Interrupts Parameter Timing Requirements tSIR IRQ2–0 Setup Before CLKIN High1 tHIR IRQ2–0 Hold Before CLKIN High1 tIPW IRQ2–0 Pulse Width2 1 2 5 V and 3.3 V Max Min 18 + 3DT/4 12 + 3DT/4 2+tCK Unit ns ns ns Only required for IRQx recognition in the following cycle. Applies only if tSIR and tHIR requirements are not met. CLKIN tSIR tHIR IRQ2–0 tIPW Figure 11. Interrupts Timer Table 12. Timer Parameter Switching Characteristic tDTEX CLKIN High to TIMEXP Min 5 V and 3.3 V Max Unit 15 ns CLKIN tDTEX tDTEX TIMEXP Figure 12. Timer Rev. H | Page 23 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Flags Table 13. Flags Parameter Timing Requirements tSFI FLAG3–0 IN Setup Before CLKIN High1 tHFI FLAG3–0 IN Hold After CLKIN High1 tDWRFI FLAG3–0 IN Delay After RD/WR Low1 tHFIWR FLAG3–0 IN Hold After RD/WR Deasserted1 Switching Characteristics FLAG3–0 OUT Delay After CLKIN High tDFO tHFO FLAG3–0 OUT Hold After CLKIN High tDFOE CLKIN High to FLAG3–0 OUT Enable tDFOD CLKIN High to FLAG3–0 OUT Disable 1 Min 5 V and 3.3 V Max 8 + 5DT/16 0 – 5DT/16 5 + 7DT/16 0 16 4 3 14 Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2. CLKIN tDFOE tDFO tDFO tHFO FLAG3–0 OUT FLAG OUTPUT CLKIN tSFI tHFI FLAG3–0 IN tDWRFI tHFIWR RD/WR FLAG INPUT Figure 13. Flags Rev. H | Page 24 of 64 | March 2013 tDFOD Unit ns ns ns ns ns ns ns ns ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and DMAGx strobe timing parameters only applies to asynchronous access mode. Memory Read—Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is the Table 14. Memory Read—Bus Master 5 V and 3.3 V Parameter Min Max Timing Requirements tDAD Address Selects Delay to Data Valid1, 2 18 + DT+W tDRLD RD Low to Data Valid1 12 + 5DT/8 + W 3 tHDA Data Hold from Address, Selects 0.5 tHDRH Data Hold from RD High3 2.0 tDAAK ACK Delay from Address, Selects2, 4 14 + 7DT/8 + W 4 ACK Delay from RD Low 8 + DT/2 + W tDSAK Switching Characteristics tDRHA Address Selects Hold After RD High 0+H 2 tDARL Address Selects to RD Low 2 + 3DT/8 tRW RD Pulse Width 12.5 + 5DT/8 + W tRWR RD High to WR, RD, DMAGx Low 8 + 3DT/8 + HI Address, Selects Setup Before ADRCLK High2 0 + DT/4 tSADADC W = (number of wait states specified in WAIT register) × tCK. HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0). 1 Unit ns ns ns ns ns ns ns ns ns ns ns Data delay/setup: user must meet tDAD or tDRLD or synchronous spec tSSDATI. The falling edge of MSx, SW, BMS is referenced. 3 Data hold: user must meet tHDA or tHDRH or synchronous spec tHSDATI. See Example System Hold Time Calculation on Page 48 for the calculation of hold times given capacitive and dc loads. 4 ACK is not sampled on external memory accesses that use the internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes external, either, or both (both, if the internal wait state is zero). For the second and subsequent cycles of a wait stated external memory access, synchronous specifications tSACKC and tHACK must be met for wait state modes external, either, or both (both, after internal wait states have completed). 2 ADDRESS MSx, SW BMS tDARL tDRHA tRW RD tHDA tDRLD tDAD tHDRH DATA tDSAK tRWR tDAAK ACK WR, DMAG tSADADC ADRCLK (OUT) Figure 14. Memory Read—Bus Master Rev. H | Page 25 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Memory Write—Bus Master Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RD, WR, and DMAGx strobe timing parameters only applies to asynchronous access mode. Table 15. Memory Write—Bus Master 5 V and 3.3 V Parameter Min Max Timing Requirements tDAAK ACK Delay from Address, Selects1, 2 14 + 7DT/8 + W tDSAK ACK Delay from WR Low1 8 + DT/2 + W Switching Characteristics tDAWH Address Selects to WR Deasserted2 17 + 15DT/16 + W tDAWL Address Selects to WR Low2 3 + 3DT/8 WR Pulse Width 12 + 9DT/16 + W tWW tDDWH Data Setup Before WR High 7 + DT/2 + W tDWHA Address Hold After WR Deasserted 0.5 + DT/16 + H tDATRWH Data Disable After WR Deasserted3 1 + DT/16 +H 6 + DT/16+H tWWR WR High to WR, RD, DMAGx Low 8 + 7DT/16 + H tDDWR Data Disable Before WR or RD Low 5 + 3DT/8 + I WR Low to Data Enabled –1 + DT/16 tWDE tSADADC Address, Selects Setup Before ADRCLK High2 0 + DT/4 W = (number of wait states specified in WAIT register) × tCK. H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0). HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0). 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ACK is not sampled on external memory accesses that use the internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes external, either, or both (both, if the internal wait state is zero). For the second and subsequent cycles of a wait stated external memory access, synchronous specifications tSACKC and tHACK must be met for wait state modes external, either, or both (both, after internal wait states have completed). 2 The falling edge of MSx, SW, BMS is referenced. 3 See Example System Hold Time Calculation on Page 48 for calculation of hold times given capacitive and dc loads. Rev. H | Page 26 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADDRESS MSx, SW BMS tDAWH tDAWL tDWHA tWW WR tWWR tDDWH tWDE tDATRWH DATA tDSAK tDAAK ACK RD, DMAG tSADADC ADRCLK (OUT) Figure 15. Memory Write—Bus Master Rev. H | Page 27 of 64 | March 2013 tDDWR ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Synchronous Read/Write—Bus Master Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP-2106x (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see Memory Read—Bus Master on Page 25 and Memory Write— Bus Master on Page 26). When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous read/writes (see Synchronous Read/Write—Bus Slave on Page 30). The slave ADSP-2106x must also meet these (bus master) timing requirements for data and acknowledge setup and hold times. Table 16. Synchronous Read/Write—Bus Master Parameter Timing Requirements tSSDATI tHSDATI tDAAK tSACKC tHACK Switching Characteristics tDADRO tHADRO tDPGC tDRDO tDWRO tDRWL tSDDATO tDATTR tDADCCK tADRCK tADRCKH tADRCKL Min Data Setup Before CLKIN Data Hold After CLKIN ACK Delay After Address, Selects1, 2 ACK Setup Before CLKIN2 ACK Hold After CLKIN 5 V and 3.3 V Max 3 + DT/8 3.5 – DT/8 14 + 7DT/8 + W 6.5+DT/4 –1 – DT/4 Address, MSx, BMS, SW Delay After CLKIN1 Address, MSx, BMS, SW Hold After CLKIN PAGE Delay After CLKIN RD High Delay After CLKIN WR High Delay After CLKIN RD/WR Low Delay After CLKIN Data Delay After CLKIN Data Disable After CLKIN3 ADRCLK Delay After CLKIN ADRCLK Period ADRCLK Width High ADRCLK Width Low 7 – DT/8 –1 – DT/8 9 + DT/8 –2 – DT/8 –3 – 3DT/16 8 + DT/4 0 – DT/8 4 + DT/8 tCK (tCK /2 – 2) (tCK /2 – 2) 1 16 + DT/8 4 – DT/8 4 – 3DT/16 12.5 + DT/4 19 + 5DT/16 7 – DT/8 10 + DT/8 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns The falling edge of MSx, SW, BMS is referenced. ACK delay/setup: user must meet tDAAK or tDSAK or synchronous specification tSAKC for deassertion of ACK (low), all three specifications must be met for assertion of ACK (high). 3 See Example System Hold Time Calculation on Page 48 for calculation of hold times given capacitive and dc loads. 2 Rev. H | Page 28 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN tADRCK tDADCCK tADRCKH tDADRO tDAAK tADRCKL ADDRCLK tHADRO ADDRESS, BMS, SW, MSx tDPGC PAGE tHACK tSACKC ACK (IN) READ CYCLE tDRWL tDRDO RD tSSDATI tHSDATI DATA (IN) WRITE CYCLE tDWRO tDRWL WR tDATTR tSDDATO DATA (OUT) Figure 16. Synchronous Read/Write—Bus Master Rev. H | Page 29 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Synchronous Read/Write—Bus Slave Use these specifications for bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor memory space). The bus master must meet the bus slave timing requirements. Table 17. Synchronous Read/Write—Bus Slave Parameter Timing Requirements tSADRI Address, SW Setup Before CLKIN tHADRI Address, SW Hold After CLKIN tSRWLI RD/WR Low Setup Before CLKIN1 tHRWLI RD/WR Low Hold After CLKIN2 tRWHPI RD/WR Pulse High Data Setup Before WR High tSDATWH tHDATWH Data Hold After WR High Switching Characteristics tSDDATO Data Delay After CLKIN3 tDATTR Data Disable After CLKIN4 tDACKAD ACK Delay After Address, SW5 ACK Disable After CLKIN5 tACKTR 5 V and 3.3 V Max Min Unit 15 + DT/2 8 + 7DT/16 ns ns ns ns ns ns ns 18 + 5DT/16 7 – DT/8 9 6 – DT/8 ns ns ns ns 5 + DT/2 9.5 + 5DT/16 –4 – 5DT/16 3 5 1 0 – DT/8 –1 – DT/8 1 tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min)= 4 + DT/8. For ADSP-21060C specification is –3.5 – 5DT/16 ns min, 8 + 7DT/16 ns max; for ADSP-21060LC specification is –3.75 – 5DT/16 ns min, 8 + 7DT/16 ns max. 3 For ADSP-21062/ADSP-21062L/ADSP-21060C specification is 19 + 5DT/16 ns max; for ADSP-21060LC specification is 19.25 + 5DT/16 ns max. 4 See Example System Hold Time Calculation on Page 48 for calculation of hold times given capacitive and dc loads. 5 tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with tACKTR. 2 CLKIN tS A DR I tH A DR I ADDRESS t AC K TR t D AC K AD ACK t SR WLI READ ACCESS tH RW L I t R W HP I RD t D AT T R tSD D AT O DATA (OU T) WRITE ACCESS tH RW L I t SR W LI t R WH PI WR DATA (IN) t S D AT WH Figure 17. Synchronous Read/Write—Bus Slave Rev. H | Page 30 of 64 | March 2013 t H D ATW H ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Multiprocessor Bus Request and Host Bus Request Use these specifications for passing of bus mastership between multiprocessing ADSP-2106xs (BRx) or a host processor, both synchronous and asynchronous (HBR, HBG). Table 18. Multiprocessor Bus Request and Host Bus Request Parameter Timing Requirements tHBGRCSV HBG Low to RD/WR/CS Valid1 tSHBRI HBR Setup Before CLKIN2 tHHBRI HBR Hold After CLKIN2 tSHBGI HBG Setup Before CLKIN tHHBGI HBG Hold After CLKIN High BRx, CPA Setup Before CLKIN3 tSBRI tHBRI BRx, CPA Hold After CLKIN High tSRPBAI RPBA Setup Before CLKIN tHRPBAI RPBA Hold After CLKIN Switching Characteristics tDHBGO HBG Delay After CLKIN HBG Hold After CLKIN tHHBGO tDBRO BRx Delay After CLKIN tHBRO BRx Hold After CLKIN tDCPAO CPA Low Delay After CLKIN4 tTRCPA CPA Disable After CLKIN tDRDYCS REDY (O/D) or (A/D) Low from CS and HBR Low5, 6 tTRDYHG REDY (O/D) Disable or REDY (A/D) High from HBG6, 7 REDY (A/D) Disable from CS or HBR High6 tARDYTR Min 5 V and 3.3 V Max 20 + 5DT/4 20 + 3DT/4 14 + 3DT/4 13 + DT/2 6 + DT/2 13 + DT/2 6 + DT/2 21 + 3DT/4 12 + 3DT/4 7 – DT/8 –2 – DT/8 7 – DT/8 –2 – DT/8 –2 – DT/8 8 – DT/8 4.5 – DT/8 8.5 44 + 23DT/16 10 1 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1. 2 Only required for recognition in the current cycle. 3 CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN. 4 For ADSP-21060LC, specification is 8.5 – DT/8 ns max. 5 For ADSP-21060L, specification is 9.5 ns max, For ADSP-21060LC, specification is 11.0 ns max, For ADSP-21062L, specification is 8.75 ns max. 6 (O/D) = open drain, (A/D) = active drive. 7 For ADSP-21060C/ADSP-21060LC, specification is 40 + 23DT/16 ns min. Rev. H | Page 31 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN tSH B R I tH H B R I HBR tD HB GO tH H B GO HBG (OUT) tD B R O tH B R O BRx (OUT) tTRC P A tD C PA O CPA (OUT, O/D) tSH B GI tH H B GI HBG (I N) tSB R I tH B R I BRx, CPA (IN, O/ D) tS R PB A I tH R PB A I RPBA HBR CS tTR D YH G tD RD Y C S REDY (O/D) tA R DY TR REDY (A/D) tH B GR C SV HBG (OUT) RD WR CS O/D = O PEN DRAIN, A/D = ACTIVE DRIVE Figure 18. Multiprocessor Bus Request and Host Bus Request Rev. H | Page 32 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Asynchronous Read/Write—Host to ADSP-2106x Use these specifications for asynchronous host processor accesses of an ADSP-2106x, after the host has asserted CS and HBR (low). After HBG is returned by the ADSP-2106x, the host can drive the RD and WR pins to access the ADSP-2106x’s internal memory or IOP registers. HBR and HBG are assumed low for this timing. Not required if and address are valid tHBGRCSV after goes low. For first access after asserted, ADDR31–0 must be a non-MMS value 1/2 tCLK before or goes low or by tHBGRCSV after goes low. This is easily accomplished by driving an upper address signal high when is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1. Table 19. Read Cycle Parameter Timing Requirements tSADRDL Address Setup/CS Low Before RD Low1 tHADRDH Address Hold/CS Hold Low After RD tWRWH RD/WR High Width tDRDHRDY RD High Delay After REDY (O/D) Disable tDRDHRDY RD High Delay After REDY (A/D) Disable Switching Characteristics tSDATRDY Data Valid Before REDY Disable from Low tDRDYRDL REDY (O/D) or (A/D) Low Delay After RD Low2 tRDYPRD REDY (O/D) or (A/D) Low Pulse Width for Read tHDARWH Data Disable After RD High3 Min 5 V and 3.3 V Max 0 0 6 0 0 Unit ns ns ns ns ns 2 10 45 + 21DT/16 2 8 ns ns ns ns 1 Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Revision 2.1. 2 For ADSP-21060L, specification is 10.5 ns max; for ADSP-21060LC, specification is 12.5 ns max. 3 For ADSP-21060L/ADSP-21060LC, specification is 2 ns min, 8.5 ns max. Table 20. Write Cycle Parameter Timing Requirements tSCSWRL CS Low Setup Before WR Low tHCSWRH CS Low Hold After WR High tSADWRH Address Setup Before WR High Address Hold After WR High tHADWRH tWWRL WR Low Width tWRWH RD/WR High Width tDWRHRDY WR High Delay After REDY (O/D) or (A/D) Disable tSDATWH Data Setup Before WR High tHDATWH Data Hold After WR High Switching Characteristics REDY (O/D) or (A/D) Low Delay After WR/CS Low tDRDYWRL tRDYPWR REDY (O/D) or (A/D) Low Pulse Width for Write tSRDYCK REDY (O/D) or (A/D) Disable to CLKIN Rev. H | Page 33 of 64 | Min 5 V and 3.3 V Max 0 0 5 2 7 6 0 5 1 ns ns ns ns ns ns ns ns ns 10 15 + 7DT/16 1 + 7DT/16 March 2013 Unit 8 + 7DT/16 ns ns ns ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN t SR D YC K REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 19. Synchronous REDY Timing READ CYCLE ADDRESS/CS tH AD R D H tS A DR D L tW RW H RD tH DA R WH DATA (OUT) tD R D H RD Y tSD ATR DY t DR DY R DL tR D YPR D REDY (O /D ) REDY (A/D) WRITE CYCLE ADDRESS tSA D WR H tS C SWR L tH A D WR H tH CS WR H CS tW WR L tWR WH WR tH D ATWH tS DA TWH DATA (IN) tD WR H R DY tD R D YWR L tR DYP WR REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 20. Asynchronous Read/Write—Host to ADSP-2106x Rev. H | Page 34 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Three-State Timing—Bus Master, Bus Slave These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin. Table 21. Three-State Timing—Bus Master, Bus Slave Parameter Timing Requirements tSTSCK SBTS Setup Before CLKIN tHTSCK SBTS Hold Before CLKIN Switching Characteristics Address/Select Enable After CLKIN1 tMIENA tMIENS Strobes Enable After CLKIN2 tMIENHG HBG Enable After CLKIN tMITRA Address/Select Disable After CLKIN3 tMITRS Strobes Disable After CLKIN2 tMITRHG HBG Disable After CLKIN Data Enable After CLKIN4 tDATEN tDATTR Data Disable After CLKIN4 tACKEN ACK Enable After CLKIN4 tACKTR ACK Disable After CLKIN4 tADCEN ADRCLK Enable After CLKIN tADCTR ADRCLK Disable After CLKIN tMTRHBG Memory Interface Disable Before HBG Low5 Memory Interface Enable After HBG High5 tMENHBG Min 5 V and 3.3 V Max 12 + DT/2 6 + DT/2 –1.5 – DT/8 –1.5 – DT/8 –1.5 – DT/8 0 – DT/4 1.5 – DT/4 2.0 – DT/4 9 + 5DT/16 0 – DT/8 7.5 + DT/4 –1 – DT/8 –2 – DT/8 7 – DT/8 6 – DT/8 8 – DT/4 0 + DT/8 19 + DT 1 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is –1.25 – DT/8 ns min, for ADSP-21062, specification is –1 – DT/8 ns min. Strobes = RD, WR, PAGE, DMAG, BMS, SW. 3 For ADSP-21060LC, specification is 0.25 – DT/4 ns max. 4 In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 5 Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, and BMS (in EPROM boot mode). 2 HBG tMTRHBG tMENHBG MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE) Figure 21. Three-State Timing (Bus Transition Cycle, SBTS Assertion) Rev. H | Page 35 of 64 | March 2013 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN tSTSCK tHTSCK SBTS tMIENA, tMIENS, tMIENHG tMITRA, tMITRS, tMITRHG MEMORY INTERFACE tDATTR tDATEN DATA tACKTR tACKEN ACK tADCEN tADCTR ADRCLK Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion) Rev. H | Page 36 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC DMA Handshake These specifications describe the three DMA handshake modes. In all three modes, DMARx is used to initiate transfers. For Handshake mode, DMAGx controls the latching or enabling of data externally. For External handshake mode, the data transfer is controlled by the ADDR31–0, RD, WR, PAGE, MS3–0, ACK, and DMAGx signals. For Paced Master mode, the data transfer is controlled by ADDR31–0, RD, WR, MS3–0, and ACK (not DMAG). For Paced Master mode, the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/WriteBus Master timing specifications for ADDR31–0, RD, WR, MS3–0, PAGE, DATA63–0, and ACK also apply. Table 22. DMA Handshake Parameter Min Timing Requirements tSDRLC DMARx Low Setup Before CLKIN1 5 tSDRHC DMARx High Setup Before CLKIN1 5 tWDR DMARx Width Low (Nonsynchronous) 6 Data Setup After DMAGx Low2 tSDATDGL tHDATIDG Data Hold After DMAGx High 2 tDATDRH Data Valid After DMARx High2 tDMARLL DMARx Low Edge to Low Edge 23 + 7DT/8 2 tDMARH DMARx Width High 6 Switching Characteristics tDDGL DMAGx Low Delay After CLKIN 9 + DT/4 tWDGH DMAGx High Width 6 + 3DT/8 tWDGL DMAGx Low Width 12 + 5DT/8 tHDGC DMAGx High Delay After CLKIN –2 – DT/8 3 tVDATDGH Data Valid Before DMAGx High 8 + 9DT/16 tDATRDGH Data Disable After DMAGx High4 0 tDGWRL WR Low Before DMAGx Low5 0 DMAGx Low Before WR High 10 + 5DT/8 +W tDGWRH tDGWRR WR High Before DMAGx High 1 + DT/16 tDGRDL RD Low Before DMAGx Low 0 tDRDGH RD Low Before DMAGx High 11 + 9DT/16 + W tDGRDR RD High Before DMAGx High 0 tDGWR DMAGx High to WR, RD, DMAGx Low 5 + 3DT/8 + HI Address/Select Valid to DMAGx High 17 + DT tDADGH 6 tDDGHA Address/Select Hold After DMAGx High –0.5 W = (number of wait states specified in WAIT register) × tCK. HI = tCK (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). 1 5 V and 3.3 V Max 10 + 5DT/8 16 + 7DT/8 15 + DT/4 6 – DT/8 7 2 3 + DT/16 2 3 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Only required for recognition in the current cycle. tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can be driven tDATDRH after DMARx is brought high. 3 tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = tCK – 0.25tCCLK – 8 + (n × tCK) where n equals the number of extra cycles that the access is prolonged. 4 See Example System Hold Time Calculation on Page 48 for calculation of hold times given capacitive and dc loads. 5 For ADSP-21062/ADSP-21062L specification is –2.5 ns min, 2 ns max. 6 For ADSP-21060L/ADSP-21062L specification is –1 ns min. 2 Rev. H | Page 37 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN tSDRLC tDMARLL tSDRHC tWDR tDMARH DMARx tHDGC tDDGL tWDGL tWDGH DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE tDATRDGH tVDATDGH DATA (OUT) (FROM ADSP-2106x TO EXTERNAL DEVICE) tDATDRH tSDATDGL DATA (IN) tHDATIDG (FROM EXTERNAL DEVICE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE) tDGWRL WR tDGWRH tDGWRR (EXTERNAL DEVICE TO EXTERNAL MEMORY) tDGRDR RD tDGRDL (EXTERNAL MEMORY TO EXTERNAL DEVICE) tDRDGH tDADGH ADDR MSx, SW *MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER TIMING SPECIFICATIONS FOR ADDR31–0, RD, WR, SW MS3–0, AND ACK ALSO APPLY HERE. Figure 23. DMA Handshake Rev. H | Page 38 of 64 | March 2013 tDDGHA ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Link Ports —1 × CLK Speed Operation Table 23. Link Ports—Receive Parameter Timing Requirements tSLDCL Data Setup Before LCLK Low1 Data Hold After LCLK Low tHLDCL tLCLKIW LCLK Period (1 Operation) tLCLKRWL LCLK Width Low tLCLKRWH LCLK Width High Switching Characteristics tDLAHC LACK High Delay After CLKIN High2, 3 LACK Low Delay After LCLK High tDLALC tENDLK LACK Enable From CLKIN tTDLK LACK Disable From CLKIN 5V Max Min 3.3 V Max Min 3.5 3 tCK 6 5 3 3 tCK 6 5 18 + DT/2 –3 5 + DT/2 28.5 + DT/2 +13 Unit ns ns ns ns ns 18 + DT/2 –3 5 + DT/2 28.5 + DT/2 +13 20 + DT/2 20 + DT/2 ns ns ns ns 1 For ADSP-21062, specification is 3 ns min. LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill. 3 For ADSP-21060C, specification is 18 + DT/2 ns min, 29 + DT/2 ns max. 2 Table 24. Link Ports—Transmit Parameter Timing Requirements tSLACH LACK Setup Before LCLK High1 tHLACH LACK Hold After LCLK High Switching Characteristics tDLCLK Data Delay After CLKIN (1 Operation)2 tDLDCH Data Delay After LCLK High3 Data Hold After LCLK High tHLDCH tLCLKTWL LCLK Width Low4 tLCLKTWH LCLK Width High5 tDLACLK LCLK Low Delay After LACK High6 tENDLK LACK Enable From CLKIN tTDLK LACK Disable From CLKIN Min 5V Max 18 –7 Min 3.3 V Max 18 –7 15.5 3 –3 (tCK /2) – 2 (tCK /2) – 2 (tCK /2) + 8.5 5 + DT/2 (tCK /2) + 2 (tCK /2) + 2 (3 tCK /2) + 17 20 + DT/2 1 –3 (tCK /2) – 1 (tCK /2) – 1.25 (tCK /2) + 8 5 + DT/2 Unit ns ns 15.5 ns 2.5 ns ns ns ns ns ns ns (tCK /2) + 1.25 (tCK /2) + 1 (3 tCK /2) + 17.5 20 + DT/2 For ADSP-21060L/ADSP-21060LC, specification is 20 ns min. 2 For ADSP-21060L, specification is 16.5 ns max; for ADSP-21060LC, specification is 16.75 ns max. 3 For ADSP-21062, specification is 2.5 ns max. 4 For ADSP-21062, specification is (tCK/2) – 1 ns min, (tCK/2) + 1.25 ns max; for ADSP-21062L, specification is (tCK/2) – 1 ns min, (tCK/2) + 1.5 ns max; for ADSP-21060LC specification is (tCK/2) – 1 ns min, (tCK/2) + 2.25 ns max. 5 For ADSP-21062, specification is (tCK/2) – 1.25 ns min, (tCK/2) + 1 ns max; for ADSP-21062L, specification is (tCK/2) – 1.5 ns min, (tCK/2) + 1 ns max; for ADSP-21060C specification is (tCK/2) – 2.25 ns min, (tCK/2) + 1 ns max. 6 For ADSP-21062, specification is (tCK/2) + 8.75 ns min, (3 × tCK/2) + 17 ns max; for ADSP-21062L, specification is (tCK/2) + 8 ns min, (3 × tCK/2) + 17 ns max; for ADSP-21060LC specification is (tCK/2) + 8 ns min, (3 × tCK/2) + 18.5 ns max. Rev. H | Page 39 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 25. Link Port Service Request Interrupts: 1 and 2 Speed Operations Parameter Timing Requirements tSLCK LACK/LCLK Setup Before CLKIN Low1 tHLCK LACK/LCLK Hold After CLKIN Low1 1 5V Max Min 10 2 Min 3.3 V Max 10 2 Unit ns ns Only required for interrupt recognition in the current cycle. Link Ports —2 × CLK Speed Operation Hold skew is the maximum delay that can be introduced in LCLK relative to LDATA: Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in LDATA relative to LCLK: Hold Skew = tLCLKTWL min – tHLDCH – tHLDCL Calculations made directly from 2 speed specifications will result in unrealistically small skew times because they include multiple tester guardbands. Setup Skew = tLCLKTWH min – tDLDCH – tSLDCL Note that link port transfers at 2× CLK speed at 40 MHz (tCK = 25 ns) may fail. However, 2× CLK speed link port transfers at 33 MHz (tCK = 30 ns) work as specified. Table 26. Link Ports—Receive Parameter Timing Requirements tSLDCL Data Setup Before LCLK Low tHLDCL Data Hold After LCLK Low tLCLKIW LCLK Period (2 Operation) tLCLKRWL LCLK Width Low1 LCLK Width High2 tLCLKRWH Switching Characteristics tDLAHC LACK High Delay After CLKIN High3 tDLALC LACK Low Delay After LCLK High4 Min 5V Max 2.5 2.25 tCK/2 4.5 4.25 18 + DT/2 6 Min 3.3 V Max 2.25 2.25 tCK/2 5.25 4 28.5 + DT/2 16 1 18 + DT/2 6 Unit ns ns ns ns ns 29.5 + DT/2 16 ns ns For ADSP-21060L, specification is 5 ns min. For ADSP-21062, specification is 4 ns min, for ADSP-21060LC, specification is 4.5 ns min. 3 LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill. 4 For ADSP-21060L, specification is 6 ns min, 18 ns max. For ADSP-21060C, specification is 6 ns min, 16.5 ns max. For ADSP-21060LC, specification is 6 ns min, 18.5 ns max. 2 Rev. H | Page 40 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 27. Link Ports—Transmit Parameter Timing Requirements tSLACH LACK Setup Before LCLK High tHLACH LACK Hold After LCLK High Switching Characteristics tDLCLK Data Delay After CLKIN tDLDCH Data Delay After LCLK High1 tHLDCH Data Hold After LCLK High2 tLCLKTWL LCLK Width Low3 LCLK Width High4 tLCLKTWH tDLACLK LCLK Low Delay After LACK High Min 5V Max 19 –6.75 Min 19 –6.5 8 2.25 –2.0 (tCK /4) – 1 (tCK /4) – 1.25 (tCK /4) + 9 3.3 V Max (tCK /4) + 1.25 (tCK /4) + 1 (3 tCK /4) + 16.5 1 ns ns 8 2.25 –2 (tCK /4) – 0.75 (tCK /4) – 1.5 (tCK /4) + 9 Unit (tCK /4) + 1.5 (tCK /4) + 1 (3 tCK /4) + 16.5 ns ns ns ns ns ns For ADSP-21060/ADSP-21060C, specification is 2.5 ns max. For ADSP-21062L, specification is –2.25 ns min. 3 For ADSP-21060, specification is (tCK/4) – 1 ns min, (tCK/4) + 1 ns max; for ADSP-21060C/ADSP-21062L, specification is (tCK/4) – 1 ns min, (tCK/4) + 1.5 ns max. 4 For ADSP-21060, specification is (tCK/4) – 1 ns min, (tCK/4) + 1 ns max; for ADSP-21060C, specification is (tCK/4) – 1.5 ns min, (tCK/4) + 1 ns max. 2 Rev. H | Page 41 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TRANSMIT CLKIN tDLCLK tLCLKTWH tLCLKTWL LAST NIBBLE TRANSMITTED FIRST NIBBLE TRANSMITTED LCLK 1x OR LCLK 2x LCLK INACTIVE (HIGH) tDLDCH tHLDCH LDAT(3:0) OUT tDLACLK tSLACH tHLACH LACK (IN) THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED. RECEIVE CLKIN tLCLKIW tLCLKRWH tLCLKRWL LCLK 1x OR LCLK 2x tHLDCL tSLDCL LDAT(3:0) IN tDLALC tDLAHC LACK (OUT) LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION CLKIN tENDLK t TDLK LCLK LDAT(3:0) LACK LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER. LINK PORT INTERRUPT SETUP TIME CLKIN tSLCK t HLCK LCLK LACK Figure 24. Link Ports—Receive Rev. H | Page 42 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Serial Ports For serial ports, see Table 28, Table 29, Table 30, Table 31, Table 32, Table 33, Table 35, Figure 26, and Figure 25. To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 28. Serial Ports—External Clock Parameter Min Timing Requirements tSFSE TFS/RFS Setup Before TCLK/RCLK1 tHFSE TFS/RFS Hold After TCLK/RCLK1, 2 tSDRE Receive Data Setup Before RCLK1 tHDRE Receive Data Hold After RCLK1 tSCLKW TCLK/RCLK Width3 TCLK/RCLK Period tSCLK 3.5 4 1.5 6.5 9 tCK 5 V and 3.3 V Max Unit ns ns ns ns ns ns 1 Referenced to sample edge. RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge. 3 For ADSP-21060/ADSP-21060C/ADSP-21060LC, specification is 9.5 ns min. 2 Table 29. Serial Ports—Internal Clock 1 2 Parameter Min Timing Requirements tSFSI TFS Setup Before TCLK1; RFS Setup Before RCLK1 tHFSI TFS/RFS Hold After TCLK/RCLK1, 2 tSDRI Receive Data Setup Before RCLK1 tHDRI Receive Data Hold After RCLK1 8 1 3 3 5 V and 3.3 V Max Unit ns ns ns ns Referenced to sample edge. RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge. Table 30. Serial Ports—External or Internal Clock 1 Parameter Min Switching Characteristics tDFSE RFS Delay After RCLK (Internally Generated RFS)1 tHOFSE RFS Hold After RCLK (Internally Generated RFS)1 3 5 V and 3.3 V Max 13 Unit ns ns Referenced to drive edge. Table 31. Serial Ports—External Clock 1 Parameter Min Switching Characteristics tDFSE TFS Delay After TCLK (Internally Generated TFS)1 tHOFSE TFS Hold After TCLK (Internally Generated TFS)1 tDDTE Transmit Data Delay After TCLK1 tHDTE Transmit Data Hold After TCLK1 3 13 16 5 Referenced to drive edge. Rev. H | Page 43 of 64 | 5 V and 3.3 V Max March 2013 Unit ns ns ns ns ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 32. Serial Ports—Internal Clock Parameter Switching Characteristics tDFSI TFS Delay After TCLK (Internally Generated TFS)1 TFS Hold After TCLK (Internally Generated TFS)1 tHOFSI tDDTI Transmit Data Delay After TCLK1 tHDTI Transmit Data Hold After TCLK1 tSCLKIW TCLK/RCLK Width2 1 2 Min Max Unit 4.5 0 0.5tSCLK –2.5 0.5tSCLK +2.5 ns ns ns ns ns Min Max Unit –1.5 7.5 Referenced to drive edge. For ADSP-21060L/ADSP-21060C, specification is 0.5TSCLK – 2 ns min, 0.5tSCLK + 2 ns max. Table 33. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN Data Enable from External TCLK1, 2 Data Disable from External TCLK1, 3 tDDTTE tDDTIN Data Enable from Internal TCLK1 tDDTTI Data Disable from Internal TCLK1, 4 tDCLK TCLK/RCLK Delay from CLKIN tDPTR SPORT Disable After CLKIN 4 3 22 + 3 DT/8 17 ns ns ns ns ns ns Max Unit tCK/2 ns ns Max Unit 12 ns 10.5 0 1 Referenced to drive edge. For ADSP-21060L/ADSP-21060C, specification is 3.5 ns min; for ADSP-21062 specification is 4.5 ns min. 3 For ADSP-21062L, specification is 16 ns max. 4 For ADSP-21062L, specification is 7.5 ns max. 2 Table 34. Serial Ports—GATED SCLK with External TFS (Mesh Multiprocessing)1 Parameter Switching Characteristics tSTFSCK TFS Setup Before CLKIN tHTFSCK TFS Hold After CLKIN 1 Min 4 Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems. Table 35. Serial Ports—External Late Frame Sync Parameter Switching Characteristics tDDTLFSE Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2 tDDTENFS Data Enable from Late FS or MCE = 1, MFD = 01, 3 1 Min 3.5 MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS. 2 For ADSP-21062/ADSP-21062L, specification is 12.75 ns max; for ADSP-21060L/ADSP-21060LC, specification is 12.8 ns max. 3 For ADSP-21060/ADSP-21060C, specification is 3 ns min. Rev. H | Page 44 of 64 | March 2013 ns ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE DATA RECEIVE— EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE SAMPLE EDGE tSCLKW tSCLKIW RCLK RCLK tDFSE tDFSE tSFSI tHOFSE tHOFSE tHFSI RFS tSFSE tHFSE tSDRE tHDRE RFS tSDRI tHDRI DR DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT— INTERNAL CLOCK DRIVE EDGE DATA TRANSMIT— EXTERNAL CLOCK SAMPLE EDGE tSCLKIW DRIVE EDGE SAMPLE EDGE tSCLKW TCLK TCLK tDFSE tDFSI tHOFSI tSFSI tHFSI tHOFSE TFS tSFSE tHFSE TFS tDDTI tDDTE tHDTE tHDTI DT DT NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE DRIVE EDGE TCLK/RCLK TCLK (EXT) tDDTTE tDDTEN DT DRIVE EDGE TCLK (INT) DRIVE EDGE TCLK/RCLK tDDTIN tDDTTI DT CLKIN CLKIN tHTFSCK tDPTR TCLK, RCLK TFS, RFS, DT TCLK (INT) RCLK (INT) SPORT DISABLE DELAY FROM INSTRUCTION SPORT ENABLE AND THREE-STATE LATENCY IS TWO CYCLES tDCLK tSTFSCK TFS (EXT) NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR MESH MULTIPROCESSING. LOW TO HIGH ONLY Figure 25. Serial Ports Rev. H | Page 45 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE RCLK tSFSE/I tHOFSE/I RFS DT tDDTE/I tHDTE/I tDDTENFS 1ST BIT 2ND BIT tDDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE TCLK tHOFSE/I tSFSE/I TFS tDDTE/I TDDTENFS tHDTE/I 1ST BIT DT 2ND BIT tDDTLFSE Figure 26. Serial Ports—External Late Frame Sync Rev. H | Page 46 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC JTAG Test Access Port and Emulation For JTAG Test Access Port and Emulation, see Table 36 and Figure 27. Table 36. JTAG Test Access Port and Emulation Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS System Inputs Setup Before TCK Low1 System Inputs Hold After TCK Low1, 2 tHSYS tTRSTW TRST Pulse Width Switching Characteristics tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay After TCK Low3 Min Max tCK 5 6 7 18 4tCK Unit ns ns ns ns ns ns 13 18.5 1 ns ns System Inputs = DATA63–0, ADDR31–0, RD, WR, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, PA, BRST, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET. 2 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is 18.5 ns min. 3 System Outputs = DATA63–0, ADDR31–0, MS3–0, RD, WR, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS. tTCK TCK tSTAP tHTAP TMS TDI tDTDO TDO tSSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 27. JTAG Test Access Port and Emulation Rev. H | Page 47 of 64 | March 2013 tHSYS ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TEST CONDITIONS For the ac signal specifications (timing parameters), see Timing Specifications on Page 21. These specifications include output disable time, output enable time, and capacitive loading. The timing specifications for the DSP apply for the voltage reference levels in Figure 28. INPUT OR OUTPUT 1.5V 1.5V Figure 28. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Output Disable Time Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by V is dependent on the capacitive load, CL, and the load current, IL. This decay time can be approximated by the following equation: L V P EXT = C ------------IL output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram (Figure 29). If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. Example System Hold Time Calculation To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the ADSP-2106x’s output voltage and the input threshold for the device requiring the hold time. A typical V will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (i.e., tDATRWH for the write cycle). Capacitive Loading Output delays and holds are based on standard capacitive loads: 50 pF on all pins (see Figure 30). The delay and hold specifications given should be derated by a factor of 1.5 ns/50 pF for loads other than the nominal value of 50 pF. Figure 32, Figure 33, Figure 37, and Figure 38 show how output rise time varies with capacitance. Figure 34 and Figure 36 show graphically how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see the previous section Output Disable Time under Test Conditions.) The graphs of Figure 32, Figure 33, Figure 37, and Figure 38 may not be linear outside the ranges shown. The output disable time tDIS is the difference between tMEASURED and tDECAY as shown in Figure 29. The time tMEASURED is the interval from when the reference signal switches to when the output voltage decays V from the measured output high or output low voltage. tDECAY is calculated with test loads CL and IL, and with V equal to 0.5 V. IOL TO OUTPUT PIN +1.5V 50pF REFERENCE SIGNAL tMEASURED tDIS tENA VOH (MEASURED) VOL (MEASURED) VOH (MEASURED) - ⌬V 2.0V VOL (MEASURED) + ⌬V 1.0V tDECAY OUTPUT STOPS DRIVING IOH VOH (MEASURED) Figure 30. Equivalent Device Loading for AC Measurements (Includes All Fixtures) VOL (MEASURED) Output Drive Characteristics OUTPUT STARTS DRIVING Figure 31 shows typical I-V characteristics for the output drivers of the ADSP-2106x. The curves represent the current drive capability of the output drivers as a function of output voltage. HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V Figure 29. Output Enable/Disable Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The output enable time tENA is the interval from when a reference signal reaches a high or low voltage level to when the Rev. H | Page 48 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Output Characteristics (5 V) 3.5 RISE AND FALL TIMES - ns (0.8V to 2.0V) 75 SOURCE CURRENT - mA 50 25 5.25V, -40°C 5.0V, +25°C 0 4.75V, +100°C -25 4.75V,+100°C -50 5.0V, +25°C -75 5.25V, -40°C -100 -125 -150 0 2.5 RISE TIME 2.0 Y = 0.009x + 1.1 1.5 FALL TIME 1.0 Y = 0.005x + 0.6 0.5 0 0.75 1.50 2.25 3.00 3.75 SOURCE VOLTAGE - V 4.50 0 5.25 20 40 60 80 100 120 140 LOAD CAPACITANCE - pF 160 180 200 Figure 33. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance (VDD = 5 V) Figure 31. ADSP-21062 Typical Output Drive Currents (VDD = 5 V) 5 16.0 OUTPUT DELAY OR HOLD - ns 14.0 RISE AND FALL TIMES - ns (0.5V to 4.5V, 10% to 90%) 3.0 12.0 RISE TIME 10.0 Y = 0.005x + 3.7 8.0 FALL TIME 6.0 4.0 Y = 0.03x - 1.45 4 3 2 1 NOMINAL 2.0 0 Y = 0.0031x + 1.1 -1 0 20 40 60 80 100 120 140 LOAD CAPACITANCE - pF 160 180 25 200 Figure 32. Typical Output Rise Time (10% to 90% VDD) vs. Load Capacitance (VDD = 5 V) Rev. H | 50 75 100 125 150 LOAD CAPACITANCE - pF 175 200 Figure 34. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (VDD = 5 V) Page 49 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Output Characteristics (3.3 V) 120 18 3.3V, +25°C 80 SOURCE CURRENT - mA RISE AND FALL TIMES - ns (10% to 90%) 100 3.6V, -40°C 60 40 3.0V, +85°C VOH 20 0 3.0V, +85°C -20 3.3V, +25°C -40 3.6V, -40°C -60 -80 16 14 Y = 0.0796x + 1.17 12 10 RISE TIME 8 6 0 -120 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE - V 3.0 0 3.5 20 40 60 80 100 120 140 160 180 200 LOAD CAPACITANCE - pF Figure 37. Typical Output Rise Time (10% to 90% VDD) vs. Load Capacitance (VDD = 3.3 V) Figure 35. ADSP-21062 Typical Output Drive Currents (VDD = 3.3 V) 5 9 RISE AND FALL TIMES - ns (0.8V to 2.0V) OUTPUT DELAY OR HOLD - ns FALL TIME 2 VOL -100 Y = 0.0467x + 0.55 4 4 3 Y = 0.0329x - 1.65 2 1 NOMINAL -1 25 50 75 100 125 150 LOAD CAPACITANCE - pF 175 8 7 5 RISE TIME 4 Y = 0.0305x + 0.24 3 FALL TIME 2 1 0 200 Y = 0.0391x + 0.36 6 0 20 40 60 80 100 120 140 160 180 200 LOAD CAPACITANCE - pF Figure 36. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature) (VDD = 3.3 V) Rev. H | Page 50 of 64 | Figure 38. Typical Output Rise Time (0.8 V to 2.0 V) vs. Load Capacitance (VDD = 3.3 V) March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ENVIRONMENTAL CONDITIONS Thermal Characteristics for CQFP Package The ADSP-2106x processors are rated for performance under TCASE environmental conditions specified in the Operating Conditions (5 V) on Page 15 and Operating Conditions (3.3 V) on Page 18. The ADSP-21060C/ADSP-21060LC are available in 240-lead thermally enhanced ceramic QFP (CQFP). There are two package versions, one with a copper/tungsten heat slug on top of the package (CZ) for air cooling, and one with the heat slug on the bottom (CW) for cooling through the board. The ADSP-2106x is specified for a case temperature (TCASE). To ensure that the TCASE data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. A heatsink should be attached with a thermal adhesive. Thermal Characteristics for MQFP_PQ4 and PBGA Packages The ADSP-21060/ADSP-21060L and ADSP-21062/ADSP21062L are available in 240-lead thermally enhanced MQFP_PQ4 and 225-ball plastic ball grid array packages. The top surface of the thermally enhanced MQFP_PQ4 contains a metal slug from which most of the die heat is dissipated. The slug is flush with the top surface of the package. Note that the metal slug is internally connected to GND through the device substrate. Both packages are specified for a case temperature (TCASE). To ensure that the TCASE is not exceeded, a heatsink and/or an airflow source may be used. A heatsink should be attached with a thermal adhesive. TCASE = TAMB + (PD CA) TCASE = TAMB + (PD CA) TCASE = Case temperature (measured on top surface of package) TAMB = Ambient temperature C PD = Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation). CA =Value from Table 39 below. Table 39. Thermal Characteristics for Thermally Enhanced 240-Lead CQFP1 Parameter Airflow (LFM2) ADSP-21060CW/ADSP-21060LCW CA 0 CA 100 CA 200 CA 400 CA 600 ADSP-21060CZ/ADSP-21060LCZ CA 0 CA 100 CA 200 CA 400 CA 600 TCASE = Case temperature (measured on top surface of package) TAMB = Ambient temperature C PD =Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation). CA =Values from Table 37 and Table 38 below. Table 37. Thermal Characteristics for Thermally Enhanced 240-Lead MQFP_PQ41 Parameter CA CA CA CA CA Airflow (LFM2) 0 100 200 400 600 Typical 10 9 8 7 6 Unit °C/W °C/W °C/W °C/W °C/W 1 This represents thermal resistance at total power of 5 W. With airflow, no variance is seen in CA at 5 W. CA at 0 LFM varies with power: at 2 W, CA = 14°C/W at 3 W, CA = 11°C/W 2 LFM = Linear feet per minute of airflow. Table 38. Thermal Characteristics for BGA Parameter CA CA CA 1 Airflow (LFM1) 0 200 400 Typical 20.70 15.30 12.90 1 Unit 19.5 16 14 12 10 °C/W °C/W °C/W °C/W °C/W 20 16 14 11.5 9.5 °C/W °C/W °C/W °C/W °C/W This represents thermal resistance at total power of 5 W. With airflow, no variance is seen in CA at 5W. CA at 0 LFM varies with power. ADSP-21060CW/ADSP-21060LCW: at 2 W, CA = 23°C/W at 3 W, CA = 21.5°C/W ADSP-21060CZ/ADSP-21060LCZ: at 2 W, CA = 24°C/W at 3 W, CA = 21.5°C/W JC = 0.24°C/W for all CQFP models. 2 LFM = Linear feet per minute of airflow. Unit °C/W °C/W °C/W LFM = Linear feet per minute of airflow. Rev. H | Typical Page 51 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 225-BALL PBGA BALL CONFIGURATION Table 40. ADSP-2106x 225-Ball Metric PBGA Ball Assignments (B-225-2) Ball Name BMS ADDR30 DMAR2 DT1 RCLK1 TCLK0 RCLK0 ADRCLK CS CLKIN PAGE BR3 DATA47 DATA44 DATA42 MS0 SW ADDR31 HBR DR1 DT0 DR0 REDY RD ACK BR6 BR2 DATA45 DATA43 DATA39 MS3 MS1 ADDR28 SBTS TCLK1 RFS1 TFS0 RFS0 WR DMAG1 BR4 DATA46 DATA41 DATA38 DATA36 Ball Number A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 Ball Name ADDR25 ADDR26 MS2 ADDR29 DMAR1 TFS1 CPA HBG DMAG2 BR5 BR1 DATA40 DATA37 DATA35 DATA34 ADDR21 ADDR22 ADDR24 ADDR27 GND GND GND GND GND GND NC DATA33 DATA30 DATA32 DATA31 ADDR17 ADDR18 ADDR20 ADDR23 GND GND VDD VDD VDD GND GND DATA29 DATA26 DATA28 DATA27 Ball Number D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 Ball Name ADDR14 ADDR15 ADDR16 ADDR19 GND VDD VDD VDD VDD VDD GND DATA22 DATA25 DATA24 DATA23 ADDR12 ADDR11 ADDR13 ADDR10 GND VDD VDD VDD VDD VDD GND DATA18 DATA19 DATA21 DATA20 ADDR9 ADDR8 ADDR7 ADDR4 GND VDD VDD VDD VDD VDD GND DATA12 DATA15 DATA16 DATA17 Rev. H | Ball Number G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 Page 52 of 64 | Ball Name ADDR6 ADDR5 ADDR3 ADDR0 ICSA GND VDD VDD VDD GND GND DATA8 DATA11 DATA13 DATA14 ADDR2 ADDR1 FLAG0 FLAG3 RPBA GND GND GND GND GND NC DATA4 DATA7 DATA9 DATA10 FLAG1 FLAG2 TIMEXP TDI LBOOT L5ACK L5DAT2 L4DAT2 L3DAT0 L2DAT3 L1DAT1 L0DAT0 DATA2 DATA5 DATA6 March 2013 Ball Number K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 Ball Name EMU TDO IRQ0 IRQ1 ID2 L5DAT1 L4CLK L3CLK L3DAT3 L2DAT0 L1ACK L1DAT3 L0DAT3 DATA1 DATA3 TRST TMS EBOOT ID0 L5CLK L5DAT3 L4DAT0 L4DAT3 L3DAT2 L2CLK L2DAT2 L1DAT0 L0ACK L0DAT1 DATA0 TCK IRQ2 RESET ID1 L5DAT0 L4ACK L4DAT1 L3ACK L3DAT1 L2ACK L2DAT1 L1CLK L1DAT2 L0CLK L0DAT2 Ball Number N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 15 14 13 12 11 10 9 DATA47 BR3 PAGE CLKIN CS DATA39 DATA43 DATA45 BR2 BR6 ACK RD REDY DATA36 DATA38 DATA41 DATA46 BR4 DMAG1 WR DATA34 DATA35 DATA37 DATA40 BR1 BR5 DATA42 DATA44 8 7 6 ADRCLK RCLK0 5 4 3 2 BMS A SW MS0 B MS1 MS3 C DMAR2 ADDR30 TCLK0 RCLK1 DT1 DR0 DT0 DR1 HBR ADDR31 RFS0 TFS0 RFS1 TCLK1 SBTS ADDR28 DMAG2 HBG CPA TFS1 DMAR1 ADDR29 MS2 GND 1 ADDR26 ADDR25 D GND ADDR27 ADDR24 ADDR22 ADDR21 E DATA31 DATA32 DATA30 DATA33 NC GND GND GND GND DATA27 DATA28 DATA26 DATA29 GND GND VDD VDD VDD GND GND ADDR23 ADDR20 ADDR18 ADDR17 F DATA23 DATA24 DATA25 DATA22 GND VDD VDD VDD V DD VDD GND ADDR19 ADDR16 ADDR15 ADDR14 G DATA20 DATA21 DATA19 DATA18 GND VDD VDD VDD VDD VDD GND ADDR10 ADDR13 ADDR11 ADDR12 H DATA17 DATA16 DATA15 DATA12 GND VDD VDD VDD VDD VDD GND ADDR4 ADDR7 ADDR8 ADDR9 J DATA14 DATA13 DATA11 DATA8 GND GND V V V GND ICSA ADDR0 ADDR3 ADDR5 ADDR6 K DATA10 DATA9 DATA7 DATA4 NC GND GND GND GND GND RPBA FLAG3 FLAG0 ADDR1 ADDR2 L DATA6 DATA5 DATA2 L0DAT0 L1DAT1 L2DAT3 L3DAT0 L4DAT2 L5DAT2 L5ACK LBOOT TDI TIMEXP FLAG2 FLAG1 M DATA3 DATA1 L0DAT3 L1DAT3 L1ACK L2DAT0 L3DAT3 L3CLK L4CLK L5DAT1 ID2 IRQ1 IRQ0 TDO EMU N DATA0 L0DAT1 L0ACK L1DAT0 L2DAT2 L2CLK L3DAT2 L4DAT3 L4DAT0 L5DAT3 L5CLK ID0 EBOOT TMS TRST P L0DAT2 L0CLK L1DAT2 L1CLK L2DAT1 L2ACK L3DAT1 L3ACK L4DAT1 L4ACK L5DAT0 ID1 RESET IRQ2 TCK R DD DD DD Figure 39. ADSP-21060/ADSP-21062 PBGA Ball Assignments (Top View, Summary) Rev. H | Page 53 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 240-LEAD MQFP_PQ4/CQFP PIN CONFIGURATION Table 41. ADSP-2106x MQFP_PQ4 and ADSP-21060CZ CQFP Pin Assignments (SP-240-2, QS-240-2A, QS-240-2B) Pin Name TDI TRST VDD TDO TIMEXP EMU ICSA FLAG3 FLAG2 FLAG1 FLAG0 GND ADDR0 ADDR1 VDD ADDR2 ADDR3 ADDR4 GND ADDR5 ADDR6 ADDR7 VDD ADDR8 ADDR9 ADDR10 GND ADDR11 ADDR12 ADDR13 VDD ADDR14 ADDR15 GND ADDR16 ADDR17 ADDR18 VDD VDD ADDR19 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name ADDR20 ADDR21 GND ADDR22 ADDR23 ADDR24 VDD GND VDD ADDR25 ADDR26 ADDR27 GND MS3 MS2 MS1 MS0 SW BMS ADDR28 GND VDD VDD ADDR29 ADDR30 ADDR31 GND SBTS DMAR2 DMAR1 HBR DT1 TCLK1 TFS1 DR1 RCLK1 RFS1 GND CPA DT0 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name TCLK0 TFS0 DR0 RCLK0 RFS0 VDD VDD GND ADRCLK REDY HBG CS RD WR GND VDD GND CLKIN ACK DMAG2 DMAG1 PAGE VDD BR6 BR5 BR4 BR3 BR2 BR1 GND VDD GND DATA47 DATA46 DATA45 VDD DATA44 DATA43 DATA42 GND Rev. H | Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Name DATA41 DATA40 DATA39 VDD DATA38 DATA37 DATA36 GND NC DATA35 DATA34 DATA33 VDD VDD GND DATA32 DATA31 DATA30 GND DATA29 DATA28 DATA27 VDD VDD DATA26 DATA25 DATA24 GND DATA23 DATA22 DATA21 VDD DATA20 DATA19 DATA18 GND DATA17 DATA16 DATA15 VDD Page 54 of 64 | March 2013 Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name DATA14 DATA13 DATA12 GND DATA11 DATA10 DATA9 VDD DATA8 DATA7 DATA6 GND DATA5 DATA4 DATA3 VDD DATA2 DATA1 DATA0 GND GND L0DAT3 L0DAT2 L0DAT1 L0DAT0 L0CLK L0ACK VDD L1DAT3 L1DAT2 L1DAT1 L1DAT0 L1CLK L1ACK GND GND VDD L2DAT3 L2DAT2 L2DAT1 Pin No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Pin Name L2DAT0 L2CLK L2ACK NC VDD L3DAT3 L3DAT2 L3DAT1 L3DAT0 L3CLK L3ACK GND L4DAT3 L4DAT2 L4DAT1 L4DAT0 L4CLK L4ACK VDD GND VDD L5DAT3 L5DAT2 L5DAT1 L5DAT0 L5CLK L5ACK GND ID2 ID1 ID0 LBOOT RPBA RESET EBOOT IRQ2 IRQ1 IRQ0 TCK TMS Pin No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 42. ADSP-21060CW/21060LCW CQFP Pin Assignments (QS-240-1A, QS-240-1B) Pin Name GND DATA0 DATA1 DATA2 VDD DATA3 DATA4 DATA5 GND DATA6 DATA7 DATA8 VDD DATA9 DATA10 DATA11 GND DATA12 DATA13 DATA14 VDD DATA15 DATA16 DATA17 GND DATA18 DATA19 DATA20 VDD DATA21 DATA22 DATA23 GND DATA24 DATA25 DATA26 VDD VDD DATA27 DATA28 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name DATA29 GND DATA30 DATA31 DATA32 GND VDD VDD DATA33 DATA34 DATA35 NC GND DATA36 DATA37 DATA38 VDD DATA39 DATA40 DATA41 GND DATA42 DATA43 DATA44 VDD DATA45 DATA46 DATA47 GND VDD GND BR1 BR2 BR3 BR4 BR5 BR6 VDD PAGE DMAG1 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name DMAG2 ACK CLKIN GND VDD GND WR RD CS HBG REDY ADRCLK GND VDD VDD RFS0 RCLK0 DR0 TFS0 TCLK0 DT0 CPA GND RFS1 RCLK1 DR1 TFS1 TCLK1 DT1 HBR DMAR1 DMAR2 SBTS GND ADDR31 ADDR30 ADDR29 VDD VDD GND Rev. H | Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Name ADDR28 BMS SW MS0 MS1 MS2 MS3 GND ADDR27 ADDR26 ADDR25 VDD GND VDD ADDR24 ADDR23 ADDR22 GND ADDR21 ADDR20 ADDR19 VDD VDD ADDR18 ADDR17 ADDR16 GND ADDR15 ADDR14 VDD ADDR13 ADDR12 ADDR11 GND ADDR10 ADDR9 ADDR8 VDD ADDR7 ADDR6 Page 55 of 64 | March 2013 Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Name ADDR5 GND ADDR4 ADDR3 ADDR2 VDD ADDR1 ADDR0 GND FLAG0 FLAG1 FLAG2 FLAG3 ICSA EMU TIMEXP TDO VDD TRST TDI TMS TCK IRQ0 IRQ1 IRQ2 EBOOT RESET RPBA LBOOT ID0 ID1 ID2 GND L5ACK L5CLK L5DAT0 L5DAT1 L5DAT2 L5DAT3 VDD Pin No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Pin Name GND VDD L4ACK L4CLK L4DAT0 L4DAT1 L4DAT2 L4DAT3 GND L3ACK L3CLK L3DAT0 L3DAT1 L3DAT2 L3DAT3 VDD NC L2ACK L2CLK L2DAT0 L2DAT1 L2DAT2 L2DAT3 VDD GND GND L1ACK L1CLK L1DAT0 L1DAT1 L1DAT2 L1DAT3 VDD L0ACK L0CLK L0DAT0 L0DAT1 L0DAT2 L0DAT3 GND Pin No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC OUTLINE DIMENSIONS 23.20 23.00 SQ 22.80 A1 CORNER INDEX AREA 15 13 11 9 7 5 3 1 14 12 10 8 6 4 2 A B C D E F G H J K L M N P R BALL A1 INDICATOR 20.10 20.00 SQ 19.90 TOP VIEW 18.00 BSC SQ 1.27 BSC 0.50 R 3 PLACES BOTTOM VIEW DETAIL A 2.70 MAX DETAIL A 0.70 0.60 0.50 SEATING PLANE 0.15 MAX COPLANARITY 0.90 0.75 0.60 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MS-034-AAJ-2 Figure 40. 225-Ball Plastic Ball Grid Array [PBGA] (B-225-2) Dimensions shown in millimeters Rev. H | Page 56 of 64 | 1.30 1.20 1.10 March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 34.60 BSC SQ 0.66 0.56 0.46 29.50 REF SQ 4.10 3.78 3.55 181 240 1 180 SEATING PLANE PIN 1 24.00 REF SQ HEAT SLUG TOP VIEW (PINS DOWN) 32.00 BSC SQ 121 60 3.50 3.40 3.30 0.20 0.09 0.38 0.25 7° 0° VIEW A 0.076 COPLANARITY 120 61 0.50 BSC LEAD PITCH 3.92 × 45° (4 PLACES) 0.27 MAX 0.17 MIN VIEW A ROTATED 90° CCW COMPLIANT WITH JEDEC STANDARDS MS-029-GA Figure 41. 240-Lead Metric Quad Flat Package, Thermally Enhanced “PowerQuad” [MQFP_PQ4] (SP-240-2) Dimensions shown in millimeters Rev. H | Page 57 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 36.60 36.13 SQ 35.65 28.05 27.80 SQ 27.55 32.00 BSC SQ PIN 1 INDICATOR 181 240 181 240 1 180 180 1 SEAL RING LID TOP VIEW (PINS DOWN) BOTTOM VIEW (PINS UP) HEAT SLUG 121 60 61 4.30 3.62 2.95 3.70 3.22 2.75 0.90 0.75 0.60 0.23 0.20 0.17 60 120 61 VIEW A 19.00 REF SQ 7° -3° 121 120 0.50 BSC 0.60 0.40 0.20 1.70 0.15 0.35 0.30 0.25 0.175 0.156 0.137 NOTES: 1. LEAD FINISH = GOLD PLATE 2. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX (Sweep and/or Offset can be used as the controlling dimension). 0.180 0.155 0.130 LEAD THICKNESS 2.06 REF VIEW A Figure 42. 240-Lead Ceramic Quad Flat Package, Heat Slug Up [CQFP] (QS-240-2A) Dimensions shown in millimeters Rev. H | Page 58 of 64 | 0.15 March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 2.60 2.55 2.50 75.00 BSC SQ 29.50 BSC 16.50 (8×) 2.05 3.60 3.55 3.50 120 120 61 61 121 121 60 60 SEAL RING LID 65.90 BSC 29.50 BSC TOP VIEW BOTTOM VIEW HEAT SLUG 1 1 180 240 INDEX 1 181 INDEX 2 1.50 DIA NO GOLD GOLD PLATED 240 1.22 (4×) NONCONDUCTIVE CERAMIC TIE BAR 70.00 BSC SQ 75.50 BSC SQ 0.50 3.42 3.17 2.92 0.90 0.80 0.70 SIDE VIEW Figure 43. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Down [CQFP] (QS-240-2B) Dimensions shown in millimeters Rev. H | Page 59 of 64 | March 2013 180 181 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 36.60 36.13 SQ 35.65 19.00 REF SQ 32.00 BSC SQ PIN 1 INDICATOR 181 240 181 240 1 180 180 1 SEAL RING LID TOP VIEW (PINS DOWN) BOTTOM VIEW (PINS UP) HEAT SLUG 121 60 61 28.05 27.80 SQ 27.55 4.20 3.52 2.85 7° -3° 121 0.90 0.75 0.60 0.23 0.20 0.17 60 120 120 61 VIEW A 3.70 3.22 2.75 0.50 BSC 0.50 0.30 0.10 1.70 0.15 0.35 0.30 0.25 0.175 0.156 0.137 NOTES: 1. LEAD FINISH = GOLD PLATE 2. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX (Sweep and/or Offset can be used as the controlling dimension). 0.180 0.155 0.130 LEAD THICKNESS 2.06 REF VIEW A Figure 44. 240-Lead Ceramic Quad Flat Package, Heat Slug Down [CQFP] (QS-240-1A) Dimensions shown in millimeters Rev. H | Page 60 of 64 | 0.15 March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 2.60 2.55 2.50 75.00 BSC SQ 29.50 BSC 16.50 (8×) 2.05 3.60 3.55 3.50 120 120 61 61 121 121 60 60 SEAL RING LID 65.90 BSC 29.50 BSC TOP VIEW BOTTOM VIEW HEAT SLUG 240 INDEX 1 181 180 1 1 180 INDEX 2 2.00 DIA NO GOLD GOLD PLATED 240 181 1.22 (4×) NONCONDUCTIVE CERAMIC TIE BAR 70.00 BSC SQ 75.50 BSC SQ 0.50 3.42 3.17 2.92 0.90 0.80 0.70 SIDE VIEW Figure 45. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Up [CQFP] (QS-240-1B) Dimensions shown in millimeters SURFACE-MOUNT DESIGN Table 43 is provided as an aide to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 43. BGA Data for Use with Surface-Mount Design Package 225-Ball Grid Array (PBGA) Ball Attach Type Solder Mask Defined Rev. H | Page 61 of 64 | Solder Mask Opening 0.63 mm diameter March 2013 Ball Pad Size 0.76 mm diameter ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ORDERING GUIDE Model ASDP-21060CZ-133 ASDP-21060CZ-160 ASDP-21060CW-133 ASDP-21060CW-160 ADSP-21060KS-133 ADSP-21060KSZ-133 ADSP-21060KS-160 ADSP-21060KSZ-160 ADSP-21060KB-160 ADSP-21060KBZ-160 ADSP-21060LKSZ-133 ADSP-21060LKS-160 ADSP-21060LKSZ-160 ADSP-21060LKB-160 ADSP-21060LAB-160 ADSP-21060LABZ-160 ADSP-21060LCB-133 ADSP-21060LCBZ-133 ASDP-21060LCW-160 ADSP-21062KS-133 ADSP-21062KSZ-133 ADSP-21062KS-160 ADSP-21062KSZ-160 ADSP-21062KB-160 ADSP-21062KBZ-160 ADSP-21062CS-160 ADSP-21062CSZ-160 ADSP-21062LKSZ-133 ADSP-21062LKS-160 ADSP-21062LKSZ-160 ADSP-21062LKB-160 ADSP-21062LKBZ-160 ADSP-21062LAB-160 ADSP-21062LABZ-160 ADSP-21062LCS-160 ADSP-21062LCSZ-160 Temperature Notes Range 1, 2 –40C to +100C 1, 2 –40C to +100C 1, 2 –40C to +100C 1, 2 –40C to +100C 0C to 85C 2 0C to 85C 0C to 85C 2 0C to 85C 0C to 85C 2 0C to 85C 2 0C to 85C 0C to 85C 2 0C to 85C 0C to 85C –40C to +85C 2 –40C to +85C –40C to +100C 2 –40C to +100C 1, 2 –40C to +100C 0C to 85C 2 0C to 85C 0C to 85C 2 0C to 85C 0C to 85C 2 0C to 85C –40C to +100C 2 –40C to +100C 2 0C to 85C 0C to 85C 2 0C to 85C 0C to 85C 2 0C to 85C –40C to 85C 2 –40C to 85C –40C to +100C 2 –40C to +100C Instruction Rate 33 MHz 40 MHz 33 MHz 40 MHz 33 MHz 33 MHz 40 MHz 40 MHz 40 MHz 40 MHz 33 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 33 MHz 33 MHz 40 MHz 33 MHz 33 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 33 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz On-Chip SRAM 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit 2M Bit Operating Voltage 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 5V 5V 5V 5V 5V 5V 5V 5V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 1 Package Description 240-Lead CQFP [Heat Slug Up] 240-Lead CQFP [Heat Slug Up] 240-Lead CQFP [Heat Slug Down] 240-Lead CQFP [Heat Slug Down] 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 225-Ball PBGA 225-Ball PBGA 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 225-Ball PBGA 225-Ball PBGA 225-Ball PBGA 225-Ball PBGA 225-Ball PBGA 240-Lead CQFP [Heat Slug Down] 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 225-Ball PBGA 225-Ball PBGA 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 225-Ball PBGA 225-Ball PBGA 225-Ball PBGA 225-Ball PBGA 240-Lead MQFP_PQ4 240-Lead MQFP_PQ4 Package Option QS-240-2A QS-240-2A QS-240-1A QS-240-1A SP-240-2 SP-240-2 SP-240-2 SP-240-2 B-225-2 B-225-2 SP-240-2 SP-240-2 SP-240-2 B-225-2 B-225-2 B-225-2 B-225-2 B-225-2 QS-240-1A SP-240-2 SP-240-2 SP-240-2 SP-240-2 B-225-2 B-225-2 SP-240-2 SP-240-2 SP-240-2 SP-240-2 SP-240-2 B-225-2 B-225-2 B-225-2 B-225-2 SP-240-2 SP-240-2 Model refers to package with formed leads. For model numbers of unformed lead versions (QS-240-1B, QS-240-2B), contact Analog Devices or an Analog Devices sales representative. 2 RoHS compliant part. Rev. H | Page 62 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev. H | Page 63 of 64 | March 2013 ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00167-0-3/13(H) Rev. H | Page 64 of 64 | March 2013