AIT1042 Integrated Digital Tuner with RF and IF Gain Control PRELIMINARY DATA SHEET - Rev 1.0 FEATURES • Complete Integrated RF Tuner: Includes Upconverter with RF Gain Control, Downconverter, Digital IF Amplifier with Gain Control, Dual PLL, and VCOs with integrated tanks • IF Output - 35 to 50 MHz • 54 to 1002 MHz Operation • Operates from a Single +5 V Supply • Integrated Oscillator Tank Circuits • 78 dB Gain (including external filter losses) through Digital Output • 35 dB RF Gain Control Range • 45 dB IF Gain Control Range S38 Package 48 Pin QFN 7 mm x 7 mm x 1 mm • 2-Wire Serial Programming with 4 Addresses for Multiple Tuner Applications • Programmable Power-Down Mode • Programmable Charge Pump Currents • Materials set consistent with RoHS directives APPLICATIONS • CATV Tuners • HDTV Tuners • Set-Top Boxes • PC TV Tuner Cards or Tuner-on-Board PRODUCT DESCRIPTION The AIT1042 Integrated Digital Tuner with RF and IF Gain Control is a complete 1 GHz bandwidth tuner IC specifically designed to support digital video and data applications. It combines GaAs and Silicon technology to integrate the upconverter, downconverter, VCO, synthesizer, IF amplifier, RF gain control and IF gain control functions of a double-conversion tuner into one small package. Figure 1: Functional Block Diagram 02/2009 AIT1042 The exceptional linearity and low noise figure of the AIT1042 are ideal for use with today’s CATV systems with densely loaded spectrum. With integrated oscillator tank circuits, the AIT1042’s high level of integration minimizes board layout sensitivities and the amount of external circuitry required for a complete receiver solution. The integrated IF output further enables system solutions that minimize board layout space. The device operates from a single +5 V supply, and incorporates a programmable power-down mode. The AIT1042 is offered in a small 7 mm x 7 mm x1 mm, 48 pin, RoHS compliant, surface mount package ideal for space-sensitive applications such as PC cards and multiple-tuner set-top boxes. ACGND VREGBYP3 VREGBYP4 Figure 2: Pinout (X-ray Top View) 2 PRELIMINARY DATA SHEET - Rev 1.0 02/2009 AIT1042 Table 1: Pin Description PIN NAME 1 VDDU1 2 DESCRIPTION PIN NAME UpconverterSupply 48 IFOUT+ UpconverterDifferentialIFOutput (Inputto1stIFFilter) ACGND ACGround 47 IFOUT- UpconverterDifferentialIFOutput (Inputto1stIFFilter) 3 ACGND ACGround 46 GND Ground 4 RFUIN UpconverterRFInput 45 GND Ground 5 GND Ground 44 RFDN- DownconverterDiff.RFInput 6 GND Ground 43 RFDN+ DownconverterDiff.RFInput 7 GND Ground 42 IFDIGOUT+ DigitalIFDifferentialOutput 8 VRFAGC RFGainControlVoltage 41 IFDIGOUT- DigitalIFDifferentialOutput 9 VDD U2 UpconverterSupply 40 VREGBYP2 RegulatorBypass 10 GND Ground 39 VIFAGC IFGainControlVoltage 11 GND Ground 38 GND Ground 12 GND Ground 37 GND Ground 13 VREGBYP3 RegulatorBypass 36 VDDDIGIF 14 VUFC UpconverterOscillatorFrequency ControlVoltage 35 IFIN- IFAmplifierDifferentialInput 15 GND Ground 34 IFIN+ IFAmplifierDifferentialInput 16 CPU UpconverterSynthesizerCharge PumpOutput 33 VDD DN DownconverterSupply 17 VDDSYNU1 UpconverterSynthesizerSupply 32 IFDOUT+ DownconverterDifferentialIFOutput (Inputto2ndIFFilter)Inductively CoupledtoVDD 18 VREGBYP1 RegulatorBypass 31 IFDOUT- DownconverterDifferentialIFOutput (Inputto2ndIFFilter)Inductively CoupledtoVDD 19 REFIN CrystalReferenceInput 30 VREGBYP4 20 REFOUT CrystalReferenceOutput 29 GND Ground 21 VDDSYND1 DownconverterSynthesizerSupply 28 GND Ground 22 VDD SYND2 DownconverterSynthesizerSupply 27 VDFC Downconv.OscillatorFrequency ControlVoltage 23 CLK 2-WireInterfaceCLK 26 CPD DownconverterSynthesizerCharge PumpOutput 24 DATA 2-WireInterfaceData 25 VAS 2-WireInterfaceAddressSelect Voltage PRELIMINARY DATA SHEET - Rev 1.0 02/2009 DESCRIPTION DigitalIFAMPSupply RegulatorBypass 3 AIT1042 ELECTRICAL CHARACTERISTICS Table 2: Absolute Minimum and Maximum Ratings PARAMETER MIN MAX UNIT SupplyVoltage(VCC) 0 +6 V RFGainControlVoltage(VRFAGC) 0 +6 V IFGainControlVoltage(VIFAGC) 0 +6 V RFInputPower - +60 ElectrostaticDischarge (HumanBodyModel) - 250 V -55 +150 °C StorageTemperature COMMENTS dBmV at RFUIN and RFDIN Class1A Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. Table 3: Operating Ranges PARAMETER MIN TYP MAX UNIT SupplyVoltage(VCC) 4.75 5.00 5.25 V RFGainControlVoltage(VRFAGC) 0 - +3 V IFGainControlVoltage(VIFAGC) 0 - +3 V UpconverterRFInputCenter Frequency(fRF) 54 - 1002 MHz 1680 1690 1700 MHz IFOutputCenterFrequency(fIF2) 35 45 50 MHz CaseTemperature 0 - +85 °C FirstIFCenterFrequency(fIF1) The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. 4 PRELIMINARY DATA SHEET - Rev 1.0 02/2009 AIT1042 Table 4: DC Electrical Specifications (TC = +55 °C, VDD = +5.0 V) PARAMETER MIN TYP MAX UNIT RF Gain Control Current - 100 - A IF Gain Control Current - 100 - A TotalSupplyCurrent - 320 - mA TotalPowerConsumption - 1600 - mW StandbyCurrent - 125 - mA Table 5: AC Electrical Specifications (TC = +55 °C, VDD = +5.0 V, fIF1 = 1690 MHz, fIF2 = 45.75 MHz) MIN TYP MAX UNIT ConversionGain(2),(3),(4) - 78 - dB IFOutput(pins41&42) ChannelFlatness - 0.5 - dB 6MHzBandwidth SSBNoiseFigure - 8 - dB Measuredatmaxgain InputReturnLoss 3 - - dB 75Impedancewithoutmatch CompositeLOPhaseNoise - -85 - dBc/Hz RF Gain Control Range - 40 - dB maxgainatVRFAGC=+3V mingainatVRFAGC=+0.5V Digital IF Gain Control Range - 45 - dB maxgainatVIFAGC=+3V mingainatVIFAGC=+0.5V FinalIFOutputVoltage(4) - 1000 - mVP-P CSO - -55 - dBc 129Channels,+3dBmVeach CTB - -63 - dBc 129Channels,+3dBmVeach XMOD - -57 - dBc 129Channels,+3dBmVeach 15.75kHzAM-modulated 20 - - dB PARAMETER PowerSupplyRejectionto1MHz COMMENTS 10kHzOffset IFOutput(pins41&42) Notes: 1. All specifications as measured in ANADIGICS test fixture with a 1st IF filter loss of 4 dB and a 2nd IF filter loss of 15 dB. (2) At maximum RF and IF AGC gain settings, where applicable. (3) Including nominal 1st and 2nd IF filter losses of 4 dB and 15 dB, respectively. (4) IF output measured with a 1 k differential load across pins 41 and 42. PRELIMINARY DATA SHEET - Rev 1.0 02/2009 5 AIT1042 Table 6: Digital 2-Wire Interface Specifications (TC = +55 °C, VDD = +5.0 V, ref. Figure 3) PARAMETER SYMBOL MIN MAX UNIT CLKFrequency fCLK 1 400 kHz LogicHighInput(pins23,24) VH 2.0 - V LogicLowInput(pins23,24) VL - 0.8 V LogicInputCurrentConsumption(pins23,24) ILOG - 10 A AddressSelectInputCurrentConsumtion(pin25) IAS - 10 A DataSinkCurrent(2) IAK - 4.0 mA BusFreeTimebetweenaSTOPandSTART Condition tBUF 1.3 - s tHD;STA 0.6 - s LOWperiodofCLK tLOW 1.3 - s HIGHperiodofCLK tHIGH 0.6 - s Set-upTimeforaRepeatedSTARTCondition tSU;STA 0.6 - s DataHoldTime(for2-wirebusdevices) tHD;DAT 0.0 0.9 s DataSet-upTime tSU;DAT 100 - ns RiseTimeofDATAandCLKsignals tR 20+0.1Cb(1) 300 ns FallTimeofDataandCLKsignals tF 20+0.1Cb(1) 300 ns tSU;STO 0.6 - s Cb - 400 pF HoldTime(repeated)STARTCondition.Afterthis period,thefirstclockpulseisgenerated. Set-upTimeforSTOPCondition CapacitiveLoadforEachBusLine Notes: (1) Cb is the total capacitance of one bus line in pF. (2) For maximum 0.8 V level during Acknowledge Pulse. 3. All timing values are referred to minimum VH and maximum VL levels. DATA tF tLOW tR tSU;DAT tF tHD;STA tSP tR tBUF CLK S 6 tHD;STA tHD;DAT tHIGH tSU;STA Sr Figure 3: Serial 2-Wire Data Input Timing PRELIMINARY DATA SHEET - Rev 1.0 02/2009 tSU;STO P S AIT1042 Figure?: 4: Frequency CSO vs. Frequency Figure vs. CSO (+3dBmV input power, 129 channels - flat, TC = +558C) o (+3dBmV input power, 129 digital channels, 25 C) 0 -10 -1.25mHz -0.75mHz -20 +0.75mHz CSO (dBc) +1.25mHz -30 -40 -50 -60 -70 -80 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) Figure Frequency vs. CSO Figure?: 5: CSO vs. Frequency o ( +15dBmV input power, +3dBmV Attack, 129 flat channels, C) = +558C) (+15 dBmV input power, +3dBmV Attack, 129 channels - flat, TC+25 0 -1.25mHz -10 -0.75mHz +0.75mHz CSO (dBc) -20 +1.25mHz -30 -40 -50 -60 -70 -80 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) PRELIMINARY DATA SHEET - Rev 1.0 02/2009 7 AIT1042 Figure ?:6:Frequency vs. CSO Figure CSO vs. Frequency o input power, +3dBmV Attack / 129 flat channels, ) (+20( +20dBmV dBmV input power, +3 dBmV Attack / 129 channels - flat, T+25 C =C +558C) 0 -1.25mHz -10 -0.75mHz +0.75mHz -20 CSO (dBc) +1.25mHz -30 -40 -50 -60 -70 -80 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) Figure CTB vs. Frequency Figure ?: 7:Frequency vs. CTB (129 channels - flat, TC = +558C) o (129 digital flat channels, +25 C) -50 +3dBmV Input -52 +15dBmV Input, +3dBmV Attack -54 +20dBmV Input, +3dBmV Attack CTB (dBc) -56 -58 -60 -62 -64 -66 -68 -70 0 100 200 300 400 500 600 Frequency (MHz) 8 PRELIMINARY DATA SHEET - Rev 1.0 02/2009 700 800 900 1000 AIT1042 Figure ?: Frequency vs. XMOD Figure 8: XMOD vs. Frequency o (129 digital flat channels, +25 C) (129 channels - flat, TC = +558C) -45 -50 XMOD (dBc) -55 -60 -65 +3dBmV Input -70 +15dBmV Input, +3dBmV Attack +20dBmV Input, +3dBmV Attack -75 -80 -85 0 100 200 300 400 500 600 700 800 900 1000 Frequency (MHz) Figure Gain && NFNF vs. Frequency Figure ?:9:Gain vs. Frequency (TC = +558C) NoiseFigure(dB) 85 16 84 15 83 14 82 13 81 12 80 11 79 10 78 9 77 8 76 7 75 0 100 200 300 400 500 600 700 800 Noise Figure (dB) Gain (dB) Gain(dB) 6 900 1000 1100 Frequency (MHz) PRELIMINARY DATA SHEET - Rev 1.0 02/2009 9 AIT1042 FigureFigure 10: Composite Oscillator Phase Noise @ 10 KHz Offset ?: Internal Oscillator Phase Noise (10kHz) (TC = +558C) -70 Phase Noise (-dBc/Hz) -72 -74 -76 -78 -80 -82 -84 -86 -88 -90 50 150 250 350 450 550 650 Input Frequency (MHz) 10 PRELIMINARY DATA SHEET - Rev 1.0 02/2009 750 850 950 AIT1042 LOGIC PROGRAMMING This section describes the programming interface for the ANADIGICS AIT1042 integrated tuner. PHYSICAL INTERFACE Hosts that conform to the I 2C-Bus Specification standard can be used to program the AIT1042. The physical layer interface is a two-wire serial bus using CLOCK and DATA digital lines. The nominal bit rate of the interface is 400 kbits/sec. For data transmission, the signal on the DATA line must be stable when the CLOCK signal is high, and the state of the data must change only while the CLOCK signal is low. A logic level transition on the DATA line during a high CLOCK signal indicates the beginning or end of a data transmission, as specified in the following sections and shown in Figure 4. Start Indicator: Stop Indicator: CLOCK DATA CLOCK DATA Figure 4: Transmission Indicators ADDRESSING THE AIT1042 The AIT1042 monitors the CLOCK and DATA signals for a Start indication from the host. A Start is indicated by a high-to-low transition of the DATA signal while the CLOCK signal is high. Immediately following the Start indicator, the host sends an 8-bit address word to the AIT1042. Address words depend on the voltage on Pin 25 (VAS), as shown in Table 7 (the MSB is sent first, LSB last). Once the AIT1042 has recognized the Start indicator and a valid address word, it sends an address acknowledgement to the host by pulling the DATA line low for one clock pulse. The host can then begin to send data to program the AIT1042. Table 7: Address Select Decoding (VDD = +5 V) Pin 25 VAS Voltage Address (Hex) 1.1to1.7V C0 0to0.8V C2 2.1to2.7V C4 4.2VtoVDD C6 Sending Data If the received address byte matches the address set by the VAS voltage, the AIT1042 will acknowledge by pulling the data low before the 9th positive clock edge. The host can then begin sending programming data in 8-bit words. The MSB is sent first and the LSB last. The AIT1042 acknowledges receipt by pulling the DATA line low for one clock pulse after each received byte. The data acknowledgement tells the host it may send the next data word. Each group of three data words (24 bits total) is used to program one of seven registers described below. Completing Data Transmission After sending the final data word, the host sends a Stop indicator to mark the end of data transmission. A Stop is indicated by a low-to-high transition of the DATA signal while the CLOCK signal is held high. After receiving the Stop indicator, the AIT1042 ceases to send further acknowledgements and begins to monitor the CLOCK and DATA signals for the next Start indicator. Note: The Stop indicator does not directly control when the programming data is latched or takes effect; the data takes effect immediately following the receipt of each three-word block of data, which represents a complete 24-bit divider register. Re-sending Data If, for some reason, the data transmission fails or is interrupted, the host can resend the data. To resend data, a new Start indicator and address word must be sent prior to any data words. PRELIMINARY DATA SHEET - Rev 1.0 02/2009 11 AIT1042 PROGRAMMING THE AIT1042 This section describes how to program the registers of the AIT1042 to control its operation. The 24-bit registers that control the dividers and other functions are each segmented into three 8-bit data words. Some bits have required fixed values (reserved bits and addressing), while others are used for control and synthesizer operation. The grayed areas of the addresses and control registers are fixed values and must be set as indicated in Table 8. Control Register I Control register I has two user programmable functions: • • Wake-up (Bit 19) Charge pump current settings (Bits 8-10 and bits 12-14) in the synthesizers Table 9 shows how the Wake-up bit is used to control power up of the AIT1042. When the device is initially powered up the wake up bit (19) is set to 0 and the device will draw minimum current. Setting bit 19 to 1 will turn the device on for normal operation. The charge pump current settings for the upconverter (CPI1) and downconverter (CPI2) synthesizers are set by Bits 8-10 and Bits 12-14, respectively. Refer to Table 10. Table 8: Control Register I MSB LSB PLL_CtrlI (Control Register I) Firstdatabyte Seconddatabyte 23 22 21 20 19 18 17 16 15 0 1 0 0 W 0 0 0 0 Table 9: Wake-up Mode Bit 14 13 CPI2 12 11 0 10 Thirddatabyte 9 8 CPI1 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 1 Table 10: Charge Pump Current Bits Bit 19 Wake-up mode CPIx Bits Charge Pump Current 0 Powerdown(default) 0000 (reserved) 1 Normaloperation 0001 0.7mA 0010 1.3mA 0011 1.9mA 0100 2.5mA 0101 3.1mA 0110 3.6mA 0111 4.1mA Note: 1000 thru 1111 are Reserved. 12 PRELIMINARY DATA SHEET - Rev 1.0 02/2009 AIT1042 Control Register II Control register II contains only fixed values of address and reserve bits that must be programmed as indicated in Table 11. Table 11: Control Register II MSB LSB PLL_CtrlII (Control Register II) Firstdatabyte Seconddatabyte Thirddatabyte 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 Control Register III Control register III contains only fixed values of address and reserved bits that must be programmed as indicated in Table 12. There are no user programmable bits and this control register must be transmitted last. Table 12: Control Register III MSB LSB PLL_CtrlIII (Control Register III) Firstdatabyte Seconddatabyte Thirddatabyte 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 PRELIMINARY DATA SHEET - Rev 1.0 02/2009 13 AIT1042 Upconverter Main and Reference Divider Registers The upconverter main and reference divider registers are used to set the A, B and R counters in the upconverter synthesizer. The output frequency for the synthesizer is computed using the following equation: where: fosc = [(16)(B) + A] fxtal R fOSC is the upconverter local oscillator (LO1) frequency B is the divide ratio of the B counter (2 to 2047 inclusive) A is the divide ratio of the A counter (0 < A < P-1, A < B) fXTAL is the frequency of the reference crystal oscillator R is the divide ratio of the R counter (2 to 1023 inclusive) The preset modulus of the prescalar is 16 and is not programmable. In the main divider register, the A counter is set via Bits 2-8 and the B counter is set with Bits 9-19. In the reference divider register, the R counter is set with Bits 2-11. The remaining bits must use the fixed values indicated in Tables 13 and 14. Table 13: Upconverter Main Divider Register MSB LSB PLL1_Main (Upconverter Main Divider Register) Firstdatabyte 23 22 21 20 0 0 0 0 19 Seconddatabyte 18 17 16 15 14 13 12 11 10 Thirddatabyte 9 8 7 Bcounter MSB 6 5 4 3 2 Acounter 1 0 1 1 LSB Table 14: Upconverter Reference Divider Register PLL1_Ref (Upconverter Reference Divider Register) Firstdatabyte Seconddatabyte 23 22 21 20 19 18 17 16 15 14 13 12 0 0 0 1 0 0 1 0 0 0 0 0 14 11 10 Thirddatabyte 9 8 PRELIMINARY DATA SHEET - Rev 1.0 02/2009 7 6 Rcounter 5 4 3 2 1 0 1 0 AIT1042 Downconverter Main and Reference Divider Registers The downconverter main and reference divider registers are used to set the A, B and R counters in the downconverter synthesizer. The output frequency for the synthesizer is computed using the following equation: fosc = [(64)(B) + A] fxtal R where: fOSC is the downconverter local oscillator (LO2) frequency B is the divide ratio of the B counter (2 to 2047 inclusive) A is the divide ratio of the A counter (0 < A < P-1, A < B) fXTAL is the frequency of the reference crystal oscillator R is the divide ratio of the R counter (2 to 4095 inclusive) The preset modulus of the prescalar is 64 and is not programmable. In the main divider register, the A counter is set via Bits 2-8 and the B counter is set with Bits 9-19. In the reference divider register, the R counter is set with Bits 2-13. The remaining bits must use the fixed values indicated in Tables 15 and 16. Table 15: Downconverter Main Divider Register MSB LSB PLL2_Main (Downconverter Main Divider Register) Firstdatabyte 23 22 21 20 0 0 0 0 19 Seconddatabyte 18 17 16 15 14 13 12 11 10 Thirddatabyte 9 8 7 Bcounter 6 5 4 3 2 Acounter 1 0 0 1 Table 16: Downconverter Reference Divider Register MSB LSB PLL2_Ref (Downconverter Reference Divider Register) Firstdatabyte Seconddatabyte 23 22 21 20 19 18 17 16 15 14 0 0 0 1 0 0 1 0 0 0 13 12 11 10 Thirddatabyte 9 8 7 Rcounter PRELIMINARY DATA SHEET - Rev 1.0 02/2009 6 5 4 3 2 1 0 0 0 15 AIT1042 Synthesizer Programming Example The following is an example for programming the two synthesizers in the AIT1042 device. The calculations will determine the values required to input into the four main registers: • Main divider and reference divider for the upconverter • Main divider and reference divider for the downconverter. Conditions The desired CATV frequency to receive is 55.25MHz (picture carrier). The 1st IF (HIF) is 1690.75MHz and the 2nd IF is 45.75MHz. Phase detector comparison frequency for the upconverter is 2000KHz (2MHz). Phase detector comparison frequency for the downconverter is 62.5KHz. The crystal (xtal) reference oscillator frequency is 16MHz The preset modulus of the prescalar for: Upconverter - P = 16 and for Downconveter – P = 64. Calculation of the Reference Divider Values The value for each reference divider can be calculated by dividing the reference oscillator frequency by the desired phase detector comparison frequency: R = Fref.osc./FPD For the upconverter, the 16MHz crystal oscillator frequency and the 2000KHz phase detector comparison frequency are used to get: RPLL1 = 16MHz/2000KHz(2MHz) = 8. Therefore, the bit values for the upconverter reference divider register would be: 0000001000 For the downconverter, the 16MHz crystal oscillator frequency and the 62.5KHz phase detector comparison frequency are used to get: RPLL2 = 16MHz/62.5KHz (0.625MHz) = 256. Therefore, the bit values for the downconverter reference divider register would be: 0100000000 Main Divider Register Calculations The values of the A and B counters are determined by the desired VCO output frequency of the on-chip local oscillators and the phase detector comparison frequency: N = FVCO/FPD B = trunc(N/P) A = N – (B x P) The upconverter local oscillator frequency will be 1690.75MHz + 55.25MHz = 1746MHz for this example. Therefore, the N value for PLL1 will be = 1746MHz/2MHz = 873, the B value for PLL1 will be = (873/16) = 54, and the A value for PLL1 will be = 873 – (54 x 16) = 9. The upconverter main divider register value will be: B = 00000110110, A = 0001001 The downconverter local oscillator frequency will be 1690.75 – 45.75MHz = 1645MHz. Therefore, the N values for PLL2 will be 1645MHz/62.5KHz = 26320, the B value for PLL2 will be = (26320/64) = 411, and the A value for PLL2 will be = 26320 – (411 x 64) = 16. The downconverter main register value will be: B = 00110011011, A = 0010000 16 PRELIMINARY DATA SHEET - Rev 1.0 02/2009 AIT1042 Table 17: Complete Register Map MSB LSB PLL2_Ref (Downconverter Reference Divider Register) Firstdatabyte Seconddatabyte 23 22 21 20 19 18 17 16 15 14 0 0 0 1 0 0 1 0 0 0 13 12 11 10 Thirddatabyte 9 8 7 6 5 4 3 2 Rcounter 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 PLL2_Main (Downconverter Main Divider Register) Firstdatabyte 23 22 21 20 0 0 0 0 19 Seconddatabyte 18 17 16 15 14 13 12 11 10 Thirddatabyte 9 8 7 6 Bcounter 5 4 3 2 Acounter PLL1_Ref (Upconverter Reference Divider Register) Firstdatabyte Seconddatabyte 23 22 21 20 19 18 17 16 15 14 13 12 0 0 0 1 0 0 1 0 0 0 0 0 11 10 Thirddatabyte 9 8 7 6 5 4 3 2 Rcounter PLL1_Main (Upconverter Main Divider Register) Firstdatabyte 23 22 21 20 0 0 0 0 19 Seconddatabyte 18 17 16 15 14 13 12 11 10 Thirddatabyte 9 8 7 6 Bcounter 5 4 3 2 Acounter PLL_CtrlI (Control Register I) Firstdatabyte Seconddatabyte 23 22 21 20 19 18 17 16 15 0 1 0 0 W 0 0 0 0 14 13 12 CPI2 11 10 0 Thirddatabyte 9 8 CPI1 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 1 PLL_CtrlII (Control Register II) Firstdatabyte Seconddatabyte Thirddatabyte 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 PLL_CtrlIII (Control Register III) Firstdatabyte Seconddatabyte Thirddatabyte 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 Reminder: Program Control Register III last. PRELIMINARY DATA SHEET - Rev 1.0 02/2009 17 AIT1042 PACKAGE OUTLINE Figure 12: S38 Package Outline - 48 Pin 7 mm x 7 mm x 1 mm QFN 18 PRELIMINARY DATA SHEET - Rev 1.0 02/2009 AIT1042 ORDERING INFORMATION ORDER NUMBER TEMPERATURE RANGE PACKAGE DESCRIPTION COMPONENT PACKAGING AIT1042RS38P8 O8Cto+858C RoHS-Compliant 48pinQFNPackage 7mmx7mmx1mm Tape&Reel,2500piecesperReel AIT1042RS38P9 O8Cto+858C RoHS-Compliant 48pinQFNPackage 7mmx7mmx1mm SpecialHandling ANADIGICS, Inc. 141 Mount Bethel Road Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: [email protected] IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. warning ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. 19 PRELIMINARY DATA SHEET - Rev 1.0 02/2009