AKM AK4554VT

ASAHI KASEI
[AK4554]
AK4554
Low Power & Small Package 16bit ∆Σ CODEC
GENERAL DESCRIPTION
The AK4554 is a low voltage 16bit A/D & D/A converter for portable digital audio system. In the AK4554,
the loss of accuracy form clock jitter is also improved by using SCF techniques for on-chip post filter.
Analog signal input/output of the AK4554 are single-ended, therefore, any external filters are not required.
The AK4554 is suitable for portable digital audio system, as the AK4554 is low power dissipation and a
small package.
FEATURES
† HPF for DC-offset cancel (fc=3.4Hz)
† Single-ended ADC
- S/(N+D): 80dB@VDD=2.5V
- Dynamic Range, S/N: 89dB@VDD=2.5V
† Single-ended DAC
- Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling
- S/(N+D): 85dB@VDD=2.5V
- Dynamic Range, S/N: 92dB@VDD=2.5V
† Audio I/F format: MSB First, 2’s Compliment (AK4550 compatible)
- ADC: 16bit MSB justified
- DAC: 16bit LSB justified
† Input/Output Voltage: 0.6 x VDD (=1.5Vpp@VDD=2.5V)
† High Jitter Tolerance
† Sampling Rate: 8kHz to 50kHz
† Master Clock: 256fs/384fs/512fs/768fs (fs=8kHz to 50kHz)
1024fs (fs=8kHz to 25kHz)
† Power Supply: 1.6 to 3.6V
† Low Power Supply Current: 8mA
† Ta = −40 to 85°C
† Very Small Package: 16pin TSSOP
VDD
AINL
AINR
VCOM
VSS
∆Σ
Modulator
Decimation
Filter
∆Σ
Modulator
Decimation
Filter
Clock
Divider
MCLK
LRCK
SCLK
Serial I/O
Interface
Common Voltage
SDTO
SDTI
DEM0
AOUTL
AOUTR
LPF
∆Σ
Modulator
LPF
∆Σ
Modulator
8X
DEM1
Interpolator
8X
Interpolator
MS0325-E-01
PWDAN
PWADN
2005/08
-1-
ASAHI KASEI
[AK4554]
„ Ordering Guide
AK4554VT
AKD4554
−40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4554
„ Pin Layout
VCOM
1
16
AOUTR
AINR
2
15
AOUTL
AINL
3
14
PWDAN
VSS
4
13
PWADN
VDD
5
12
SCLK
DEM0
6
11
MCLK
DEM1
7
10
LRCK
SDTO
8
9
SDTI
Top
View
„ Comparison with AK4550
Item
Power Supply Voltage
VCOM pin
ADC S/(N+D) (typ)
ADC Input Resistance (typ)
ADC PSRR (typ)
Power Supply Current (typ)
AD+DA
AD
DA
DAC Digital Filter
Stopband Attenuation (min)
Passband Ripple (max)
Group Delay
AK4550
2.3 ∼ 3.6V
0.45 x VDD
82dB
100kΩ
35dB
AK4554
1.6 ∼ 3.6V
0.5 x VDD
80dB
70kΩ
45dB
10mA
5.6mA
5.6mA
8mA
4mA
4.4mA
43dB
±0.06dB
14.8/fs
MCLK
256fs/384fs/512fs
54dB
±0.02dB
19.0/fs
256fs/384fs/512fs/768fs (fs=8∼50kHz)
1024fs (fs=8∼25kHz)
External Circuit
VCOM pin
AINL, AINR pins
4.7µF + 0.1µF
RC filter is needed.
0.1µF
RC filter is on-chip.
MS0325-E-01
2005/08
-2-
ASAHI KASEI
[AK4554]
PIN/FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
Pin Name
VCOM
AINR
AINL
VSS
VDD
DEM0
DEM1
SDTO
SDTI
LRCK
MCLK
SCLK
I/O
O
I
I
I
I
O
I
I
I
I
13
PWADN
I
14
PWDAN
I
15
16
AOUTL
AOUTR
O
O
Function
Common Voltage Output Pin, 0.5 x VDD
Rch Analog Input Pin
Lch Analog Input Pin
Ground Pin
Power Supply Pin
De-emphasis Control Pin
De-emphasis Control Pin
Audio Serial Data Output Pin
Audio Serial Data Input Pin
Input/Output Channel Clock Pin
Master Clock Input Pin
Audio Serial Data Clock Pin
ADC Power-Down & Reset Mode Pin
“L”: Power down. ADC should always be reset upon power-up.
DAC Power-Down & Reset Mode Pin
“L”: Power down. DAC should always be reset upon power-up.
Lch Analog Output Pin
Rch Analog Output Pin
Note: All input pins except analog input pins (AINR and AINL) should not be left floating.
„ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
AINR, AINL, AOUTL, AOUTR
SDTO
SDTI
MS0325-E-01
Setting
These pins should be open.
This pin should be open.
This pin should be connected to VSS.
2005/08
-3-
ASAHI KASEI
[AK4554]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supply
Input Current (any pins except for supplies)
Input Voltage
Ambient Temperature (power applied)
Storage Temperature
Symbol
VDD
IIN
VIN
Ta
Tstg
min
−0.3
−0.3
−40
−65
max
4.6
±10
VDD+0.3
85
150
Units
V
mA
V
°C
°C
Note 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
min
1.6
typ
2.5
max
3.6
Units
V
Note 1. All voltages with respect to ground.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0325-E-01
2005/08
-4-
ASAHI KASEI
[AK4554]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=2.5V; fs=44.1kHz; Signal Frequency=1kHz; SCLK=64fs; Measurement frequency=20Hz ∼ 20kHz;
unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics: (Note 2)
Resolution
16
Bits
S/(N+D)
70
80
dB
(−0.5dB Input)
D-Range
82
89
dB
(−60dB Input, A-weighted)
S/N
(A-weighted)
82
89
dB
Interchannel Isolation
80
95
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Input Voltage
(Note 3)
1.35
1.50
1.65
Vpp
Input Resistance
40
70
kΩ
Power Supply Rejection
(Note 4)
45
dB
DAC Analog Output Characteristics:
Resolution
16
Bits
S/(N+D)
75
85
dB
D-Range
86
92
dB
(−60dB Output, A-weighted)
S/N
(A-weighted)
86
92
dB
Interchannel Isolation
80
95
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Output Voltage
(Note 3)
1.35
1.50
1.65
Vpp
Load Resistance
10
kΩ
Load Capacitance
30
pF
Power Supply Rejection
(Note 4)
50
dB
Power Supplies
Power Supply Current
AD+DA
PWADN= “H”, PWDAN= “H”
8
13
mA
AD
PWADN= “H”, PWDAN= “L”
4
mA
DA
PWADN= “L”, PWDAN= “H”
4.4
mA
Power down (Note 5) PWADN= “L”, PWDAN= “L”
10
50
µA
Power Consumption
AD+DA
PWADN= “H”, PWDAN= “H”
20
32.5
mW
AD
PWADN= “H”, PWDAN= “L”
10
mW
DA
PWADN= “L”, PWDAN= “H”
11
mW
Power down (Note 5) PWADN= “L”, PWDAN= “L”
25
125
µW
Note 2. The offset of ADC is removed by internal HPF.
Note 3. Input/Output of ADC and DAC scales with VDD voltage. 0.6 x VDD(typ).
Note 4. PSR is applied to VDD with 1kHz, 50mV. No signal is input to AINL/R pins and “0” data is input to SDTI pin.
Note 5. In case of power-down mode, all digital input including clocks pins (MCLK, SCLK and LRCK) are held to VDD
or VSS. PWADN and PWDAN pins are held to VSS.
MS0325-E-01
2005/08
-5-
ASAHI KASEI
[AK4554]
FILTER CHARACTERISTICS
(Ta=25°C; VDD=1.6 ∼ 3.6V; fs=44.1kHz; DEM1 pin = “L”, DEM0 pin = “H”)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
Passband
(Note 6)
PB
0
±0.1dB
−1.0dB
−3.0dB
Stopband
SB
25.7
Passband Ripple
PR
Stopband Attenuation
SA
65
Group Delay
(Note 7)
GD
Group Delay Distortion
∆GD
ADC Digital Filter (HPF):
Frequency Response (Note 6)
FR
−3dB
−0.5dB
−0.1dB
DAC Digital Filter:
Passband
(Note 6)
PB
0
±0.05dB
−6.0dB
Stopband
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay
(Note 7)
GD
DAC Digital Filter + Analog Filter:
Frequency Response
FR
0 ∼ 20.0kHz
typ
max
Units
20.0
21.1
17.0
0
17.4
±0.1
-
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
3.4
10
22
-
Hz
Hz
Hz
22.05
19.0
20.0
±0.02
-
kHz
kHz
kHz
dB
dB
1/fs
±0.5
-
dB
Note 6. The passband and stopband frequencies scale with fs (sampling frequency). For examples, PB=20.0kHz(@ADC:
−1.0dB, DAC: −0.1dB) are 0.454 x fs.
Note 7. This is the calculated delay time caused by digital filtering. This time is measured from the input of analog signal
to setting the 16bit data of both channels on input register to the output register of ADC. This time also includes
group delay of HPF. For DAC, this time is from setting the 16bit data of both channels on input register to the
output of analog signal.
DC CHARACTERISTICS
(Ta=25°C; VDD=1.6 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage
2.2V≤VDD≤3.6V
VIH
70%VDD
1.6V≤VDD<2.2V
VIH
80%VDD
Low-Level Input Voltage
2.2V≤VDD≤3.6V
VIL
1.6V≤VDD<2.2V
VIL
High-Level Output Voltage
(Iout= −20µA)
VOH
VDD−0.1
Low-Level Output Voltage
(Iout= 20µA)
VOL
Input Leakage Current
Iin
-
MS0325-E-01
typ
-
max
30%VDD
20%VDD
0.1
±10
Units
V
V
V
V
V
V
µA
2005/08
-6-
ASAHI KASEI
[AK4554]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=1.6 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
Frequency
256fs/384fs/512fs/768fs
fCLK
2.048
1024fs
fCLK
2.048
Duty Cycle
dCLK
40
LRCK Timing
Frequency
fs
8
Duty Cycle
Duty
45
Serial Interface Timing
SCLK Period
tSCK
1/(96fs)
(8kHz ≤ fs ≤ 33kHz)
tSCK
312.5
(33kHz < fs ≤ 50kHz)
SCLK Pulse Width Low
tSCKL
130
Pulse Width High
tSCKH
130
(Note 8)
tLRS
50
LRCK Edge to SCLK “↑”
(Note 8)
tSLR
50
SCLK “↑” to LRCK Edge
LRCK Edge to SDTO (MSB)
tDLR
tDSS
SCLK “↓” to SDTO
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Reset Timing
PWADN or PWDAN Pulse Width
tPW
150
(Note 9)
tPWV
PWADN “↑” to SDTO Valid
typ
max
Units
-
38.4
25.6
60
MHz
MHz
%
44.1
-
50
55
kHz
%
-
80
80
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2081
-
ns
1/fs
Note 8. SCLK rising edge must not occur at the same time as LRCK edge.
Note 9. These cycles are the number of LRCK rising from PWADN rising.
MS0325-E-01
2005/08
-7-
ASAHI KASEI
[AK4554]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK = tCLKH x fCLK x 100
= tCLKL x fCLK x 100
1/fs
VIH
LRCK
VIL
tLRH
tLRL
Duty = tLRH x fs x 100
= tLRL x fs x 100
tSCK
VIH
SCLK
VIL
tSCKH
tSCKL
Figure 1. Clock Timing
VIH
LRCK
VIL
tSLR
tLRS
VIH
SCLK
VIL
tDLR
tDSS
SDTO
50%VDD
tSDS
tSDH
VIH
SDTI
VIL
Figure 2. Serial Interface Timing
tPW
PWDAN
VIL
tPW
VIH
PWADN
VIL
tPWV
SDTO
50%VDD
Figure 3. Reset & Initialize Timing
MS0325-E-01
2005/08
-8-
ASAHI KASEI
[AK4554]
OPERATION OVERVIEW
„ System Clock Input
The AK4554 can be input MCLK=256fs, 384fs, 512fs, 768fs or 1024fs (fs is equal to or lower than 25kHz when MCLK
is 1024fs). The input clock applied to the MCLK pin as internal master clock is divided into 256fs automatically. When
MCLK is 1024fs, oversampling rate of D/A converter is automatically changed from 128fs to 256fs. The relationship
between the external clock applied to the MCLK input and the desired sample rate is defined in Table 1. The LRCK clock
input should be synchronized with MCLK. The phase between these clocks does not matter. *fs is sampling frequency.
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4554 may
occur click noise.
All external clocks(MCLK, SCLK and LRCK) must be present unless PWADN=PWDAN= “L”. If these clocks are not
provided, the AK4554 may draw excess current and may not possibly operate properly because the device utilizes
dynamic refreshed logic internally.
fs
8.0kHz
16.0kHz
32.0kHz
44.1kHz
48.0kHz
256fs
2.0480MHz
4.0960MHz
8.1920MHz
11.2896MHz
12.2880MHz
384fs
3.0720MHz
6.1440MHz
12.2880MHz
16.9344MHz
18.4320MHz
MCLK
512fs
768fs
1024fs
4.0960MHz
6.1440MHz
8.1920MHz
8.1920MHz 12.2880MHz 16.3840MHz
16.3840MHz 24.5760MHz
N/A
22.5792MHz 33.8688MHz
N/A
24.5760MHz 36.8640MHz
N/A
Table 1. System Clock Example
SCLK
32fs
64fs
0.2560MHz
0.512MHz
0.5120MHz
1.024MHz
1.0240MHz
2.048MHz
1.4112MHz
2.822MHz
1.5360MHz
3.072MHz
For low sampling rates, outband noise causes S/N of DAC to degrade. S/N is improved by setting MCLK to 1024fs. Table
2 shows S/N of DAC output.
fs
MCLK
S/N(fs=8kHz, A-weighted)
256fs/384fs/512fs/768fs
84dB
8kHz ∼ 50kHz
1024fs
90dB
8kHz ∼ 25kHz
Table 2. Relationship among fs, MCLK frequency and S/N of DAC
MS0325-E-01
2005/08
-9-
ASAHI KASEI
[AK4554]
„ Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. The data is MSB first, 2’s compliment.
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
SCLK(i)
(32fs)
SDTI(i)
SDTO(o)
15
14
6
1
0
5
14
4
15
3
16
2
17
1
0
31
15
0
14
6
5
14
1
4
15
3
16
2
17
1
0
31
15
0
14
1
SCLK(i)
(64fs)
SDTO(o)
15
SDTI(i)
Don’t care
14
2
1
15
0
15
14
0
14
2
1
0
Don’t care
15
15
14
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Audio Interface Timing
„ De-emphasis filter
The DAC of AK4554 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to three
frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter selected by DEM0 and DEM1 pins is enabled for input
audio data. The de-emphasis is also disabled at DEM1 pin = “L” and DEM0 pin = “H”.
DEM1 pin
DEM0 pin
Mode
L
L
44.1kHz
L
H
OFF
H
L
48kHz
H
H
32kHz
Table 3. De-emphasis filter control
„ Digital High Pass Filter
The AK4554 has a Digital High Pass Filter (HPF) for DC-offset cancel. The cut-off frequency of the HPF is 3.4Hz at
fs=44.1kHz and the frequency response at 20Hz is −0.12dB. It also scales with the sampling frequency (fs).
MS0325-E-01
2005/08
- 10 -
ASAHI KASEI
[AK4554]
„ Power-down & Reset
The ADC and DAC of AK4554 are placed in the power-down mode by bringing each power down pin, PWADN,
PWDAN = “L” independently and each digital filter is also reset at the same time. These resets should always be done
after power-up. In case of the ADC, an anlog initialization cycle starts after exiting the power-down mode. Therefore, the
output data, SDTO becomes available after 2081 cycles of LRCK clock. This initialization cycle does not affect the DAC
operation. Figure 5 shows the power-up sequence when the ADC is powered up before the DAC power-up.
PWADN
2081/fs
ADC Internal
State
Normal Operation
Power-down
Init Cycle
Normal Operation
PWDAN
DAC Internal
State
Normal Operation
Normal Operation
Power-down
GD
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data
Idle Noise
DAC In
(Digital)
Idle Noise
“0”data
GD
GD
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
The clocks may be stopped.
External
Mute
Mute ON
Figure 5. Power-up Sequence
MS0325-E-01
2005/08
- 11 -
ASAHI KASEI
[AK4554]
SYSTEM DESIGN
Figure 6 shows the system connection diagram. An evaluation board[AKD4554] is available which demonstrates
application circuit, optimum layout, power supply arrangements and measurement results.
0.1u
Rch In
Lch In
Analog Supply
1.6 ∼ 3.6V
Mode
Control
+
+
10u
+
1
VCOM
AOUTR 16
2
AINR
AOUTL 15
3
AINL
4
VSS
0.1u
AK4554
Top View
PWDAN 14
Reset
PWADN 13
Reset
SCLK 12
5
VDD
6
DEM0
MCLK 11
7
DEM1
LRCK 10
8
SDTO
SDTI
Controller
9
Analog Ground
System Ground
Figure 6. System Connection Diagram Example
Notes:
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- Capacitor value of VCOM depends on low frequency noise of supply voltage.
MS0325-E-01
2005/08
- 12 -
ASAHI KASEI
[AK4554]
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling
capacitors should be as near to the AK4554 as possible, with the small value ceramic capacitor being nearest.
2. Voltage Reference
The input to VDD voltage sets the analog input/output range. A 0.1µF ceramic capacitor and a 10µF electrolytic capacitor
is connected to VDD and VSS pins, normally. VCOM is a signal ground of this chip. An electrolytic less than 4.7µF in
parallel with a 0.1µF ceramic capacitor attached to these pins eliminates the effects of high frequency noise. No load
current may be drawn from VCOM pin. All signals, especially clock, should be kept away from the VDD and VCOM pins
in order to avoid unwanted coupling into the AK4554.
3. Analog Inputs
ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and
nominally 0.6xVDD Vpp(typ). The ADC output data format is 2’s compliment.
The AK4554 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. The AK4554 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The output signal range scales with the
supply voltage and nominally 0.6xVDD Vpp(typ). The DAC input data format is 2’s compliment. The output voltage is a
positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal output is VCOM voltage
for 0000H(@16bit). If the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the
attenuation by external filter is required.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
MS0325-E-01
2005/08
- 13 -
ASAHI KASEI
[AK4554]
„ Layout Pattern Example
AK4554 requires careful attention to power supply and grounding arrangements to optimize performance.
(Please refer to AKD4554 Evaluation Board layout pattern.)
1.
VDD pin should be supplied from analog power supply on system, and VSS pin should be connected to analog
ground on system. The AK4554 is placed on the analog ground plane, and near the analog ground and digital ground
split. And analog and digital ground planes should be only connected at one point. The connection point should be
near to the AK4554.
2.
VDD pin should be distributed from the point with low impedance of regulator etc.
3.
The series resistors are prevent on the clock lines to reduce overshoot and undershoot. To avoid digital noise
coupling to analog circuit in the AK4554, a 10pF ceramic capacitor on MCLK pin is connected with digital ground.
4.
0.1µF ceramic capacitors of VDD-VSS pins and VCOM-VSS pins should be located as close to the AK4554 as
possible. And these lines should be the shortest connection to pins.
0.1u
Rch In
Lch In
+
+
1 VCOM
AOUTR 16
2 AINR
AOUTL 15
3 AINL
Analog Supply
1.6 ∼ 3.6V
AK4554
Reset &Power-down
PWADN 13
4 VSS
+
10u 0.1u
PWDAN 14
Top View SCLK 12
5 VDD
6 DEM0
MCLK 11
7 DEM1
LRCK 10
8 SDTO
SDTI 9
51
51
10P
51
Analog Ground
Digital Ground
Controller
51
51
Mode Control
Figure 7. Layout Pattern Example
MS0325-E-01
2005/08
- 14 -
ASAHI KASEI
[AK4554]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0±0.1
9
A
8
1
0.13 M
6.4±0.2
*4.4±0.1
16
1.05±0.05
0.22±0.1
0.65
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
„ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0325-E-01
2005/08
- 15 -
ASAHI KASEI
[AK4554]
MARKING
AKM
4554VT
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4554VT
Asahi Kasei Logo
Revision History
Date (YY/MM/DD)
04/07/28
05/08/08
Revision
00
01
Reason
First Edition
Spec Change
Page
Contents
7
Switching Characteristics
tSCK(min): 312.5ns Æ 1/(96fs) or 312.5ns
MS0325-E-01
2005/08
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ASAHI KASEI
[AK4554]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
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and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
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absence of such notification.
MS0325-E-01
2005/08
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