PRELIMINARY Am29F400AT/Am29F400AB 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory DISTINCTIVE CHARACTERISTICS ■ 5.0 V ± 10% for read and write operations — Minimizes system level power requirements ■ Compatible with JEDEC-standards — Pinout and software compatible with single-power-supply flash — Superior inadvertent write protection ■ Minimum 100,000 write/erase cycles guaranteed ■ High performance — 60 ns maximum access time ■ Sector erase architecture — One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and seven 64 Kbytes — Any combination of sectors can be erased. Also supports full chip erase. ■ Sector protection — Hardware method that disables any combination of sectors from write or erase operations. Implemented using standard PROM programming equipment. ■ Embedded Erase Algorithms — Automatically preprograms and erases the chip or any sector — Automatically programs and verifies data at specified address ■ Data Polling and Toggle Bit feature for detection of program or erase cycle completion ■ Ready/Busy output (RY/BY) — Hardware method for detection of program or erase cycle completion ■ Erase Suspend/Resume — Supports reading data from a sector not being erased ■ Low power consumption — 20 mA typical active read current for Byte Mode — 28 mA typical active read current for Word Mode — 30 mA typical program/erase current ■ Enhanced power management for standby mode — 1 µA typical standby current ■ Boot Code Sector Architecture — T = Top sector — B = Bottom sector ■ Hardware RESET pin — Resets internal state machine to the read mode GENERAL DESCRIPTION The Am29F400A is a 4 Mbit, 5.0 Volt-only Flash memory organized as 512 Kbytes of 8 bits each or 256 Kwords of 16 bits each. The 4 Mbits of data is divided into 11 sectors of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbytes, for flexible erase capability. The 8 bits of data will appear on DQ0–DQ7 or 16 bits on DQ0–DQ15. The Am29F400A is offered in 44-pin SO and 48-pin TSOP packages. This device is designed to be programmed in-system with the standard system 5.0 Volt VCC supply. 12.0 Volt VPP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard Am29F400A offers access times of 60 ns, 70 ns, 90 ns, 120 ns and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE) and output enable (OE) controls. The Am29F400A is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 20380 Rev: B Amendment/0 Issue Date: April 1997 5.0 V-only Flash ■ Package options — 44-pin SO — 48-pin TSOP ■ Embedded Program Algorithms P R E L I M I N A R Y Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 Volt Flash or EPROM devices. The Am29F400A is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The Am29F400A memory electrically erases all b i t s w i t h i n a s e c t o r s i mu l t a n e o u s l y v i a Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. Flexible Sector-Erase Architecture ■ One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and seven 64 Kbyte sectors ■ Individual-sector or multiple-sector erase capability ■ Sector protection is user definable (x8) This device also features a sector erase architecture. This allows for sectors of memory to be erased and reprogrammed without affecting the data contents of other sectors. A sector is typically erased and verified within 1.5 seconds. The Am29F400A is erased when shipped from the factory. SA10 16 Kbyte SA9 8 Kbyte SA8 8 Kbyte SA7 32 Kbyte SA6 64 Kbyte SA5 64 Kbyte SA4 64 Kbyte AMD has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of time to read data from a sector that was not being erased. Thus, true background erase can be achieved. SA3 64 Kbyte SA2 64 Kbyte SA1 64 Kbyte The device features single 5.0 Volt power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations during power transitions. The end of program or erase is detected by the RY/BY pin. Data Polling of DQ7, or by the Toggle Bit (DQ6). Once the end of a program or erase cycle has been completed, the device automatically resets to the read mode. SA0 64 Kbyte The Am29F400A device also features hardware sector protection. This feature will disable both program and erase operations in any combination of eleven sectors of memory. The Am29F400A also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm will be terminated. The internal state machine will then be reset into the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device will be automatically reset to the read mode and will have erroneous data stored in the address locations being operated on. These locations will need rewriting after the Reset. Resetting the device will enable the system’s microprocessor to read the boot-up firmware from the Flash memory. (x16) 7FFFFh 3FFFFh 7BFFFh 3DFFFh 79FFFh 3CFFFh 77FFFh 3BFFFh 6FFFFh 37FFFh 5FFFFh 2FFFFh 4FFFFh 27FFFh 3FFFFh 1FFFFh 2FFFFh 17FFFh 1FFFFh 0FFFFh 0FFFFh 07FFFh 00000h 00000h 20380B-1 Am29F400AT Sector Architecture (x8) 7FFFFh 3FFFFh SA10 64 Kbyte SA9 64 Kbyte SA8 64 Kbyte SA7 64 Kbyte SA6 64 Kbyte SA5 64 Kbyte SA4 64 Kbyte SA3 32 Kbyte SA2 8 Kbyte SA1 8 Kbyte SA0 16 Kbyte 6BFFFh 37FFFh 5FFFFh 2FFFFh 4FFFFh 27FFFh 3FFFFh 1FFFFh 2FFFFh 17FFFh 1FFFFh 0FFFFh 0FFFFh 07FFFh 07FFFh 03FFFh 05FFFh 02FFFh 03FFFh 01FFFh 00000h 00000h 20380B-2 Am29F400AB Sector Architecture 2 (x16) Am29F400AT/Am29F400AB P R E L I M I N A R Y PRODUCT SELECTOR GUIDE Family Part No: Am29F400A Ordering Part No:VCC = 5.0 V ± 5% -65 VCC = 5.0 V ± 10% -70 -90 -120 -150 Max Access Time (ns) 60 70 90 120 150 CE (E) Access (ns) 60 70 90 120 150 OE (G) Access (ns) 30 30 35 50 55 BLOCK DIAGRAM 5.0 V-only Flash DQ0–DQ15 VCC VSS WE BYTE RESET RY/BY Buffer RY/BY Input/Output Buffers Erase Voltage Generator State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE OE VCC Detector A0-A17 Timer Address Latch STB STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A-1 20380B-3 Am29F400AT/Am29F400AB 3 P R E L I M I N A R Y CONNECTION DIAGRAMS SO NC 1 44 RESET RY/BY 2 43 WE A17 3 42 A8 A7 4 41 A9 A6 5 40 A10 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 A2 9 36 A14 A1 10 35 A15 A0 11 34 A16 CE 12 33 BYTE VSS OE 13 32 14 31 VSS DQ15/A-1 DQ0 15 30 DQ7 DQ8 16 29 DQ14 DQ1 17 28 DQ6 DQ9 18 27 DQ13 DQ2 19 26 DQ5 DQ10 20 25 DQ12 DQ3 21 24 DQ4 DQ11 22 23 VCC 20380B-4 4 Am29F400AT/Am29F400AB P R E L I M I N A R Y CONNECTION DIAGRAMS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 20380B-5 Standard TSOP A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Reverse TSOP Am29F400AT/Am29F400AB 5.0 V-only Flash A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET NC NC RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 20380B-6 5 P R E L I M I N A R Y PIN CONFIGURATION LOGIC SYMBOL A1, A0–A17 = 18 Addresses BYTE CE = Selects 8-bit or 16-bit mode A-1 18 = Chip Enable DQ0–DQ15 NC = Pin Not Connected Internally OE = Output Enable CE (E) RESET = Hardware Reset Pin, Active Low OE (G) RY/BY = Ready/Busy Output VSS = +5.0 Volt Single-Power Supply (±10% for -90, -120, -150) or (±5% for -75) VSS = Device Ground WE = Write Enable 6 16 or 8 A0–A17 DQ0–DQ15 = 16 Data Inputs/Outputs WE (W) RESET BYTE RY/BY 20380B-7 Am29F400AT/Am29F400AB P R E L I M I N A R Y ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: AM29F400A T -65 E C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In 5.0 V-only Flash TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29F400A 4 Megabit (512K x 8-Bit/256K x 16-Bit) CMOS Flash Memory 5.0 Volt-only Program and Erase Valid Combinations Valid Combinations AM29F400AT/B-65 EC, EI, FC, FI, SC, SI Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM29F400AT/B-70 AM29F400AT/B-90 AM29F400AT/B-120 EC, EI, EE, EEB, FC, FI, FE, FEB, SC, SI, SE, SEB AM29F400AT/B-150 Am29F400AT/Am29F400AB 7 P R E L I M I N A R Y Table 1. Am29F400A User Bus Operations (BYTE = VIH) Operation CE OE WE A0 A1 A6 A9 DQ0–DQ15 RESET Autoselect, AMD Manuf. Code (Note 1) L L H L L L VID Code H Autoselect Device Code (Note 1) L L H H L L VID Code H Read L L H A0 A1 A6 A9 DOUT H Standby H X X X X X X HIGH Z H Output Disable L H H X X X X HIGH Z H Write L H L A0 A1 A6 A9 DIN H Verify Sector Protect (Note 2) L L H L H L VID Code H Temporary Sector Unprotect X X X X X X X X VID Hardware Reset X X X X X X X HIGH Z L Table 2. Operation Am29F400A User Bus Operations (BYTE = VIL) CE OE WE A0 A1 A6 A9 Autoselect, AMD Manuf. Code (Note 1) L L H L L L VID Code HIGH Z H Autoselect Device Code (Note 1) L L H H L L VID Code HIGH Z H Read L L H A0 A1 A6 A9 DOUT HIGH Z H Standby H X X X X X X HIGH Z HIGH Z H Output Disable L H H X X X X HIGH Z HIGH Z H Write L H L A0 A1 A6 A9 DIN HIGH Z H Verify Sector Protect (Note 2) L L H L H L VID Code HIGH Z H Temporary Sector Unprotect X X X X X X X X HIGH Z VID Hardware Reset X X X X X X X HIGH Z HIGH Z L DQ0–DQ7 DQ8–DQ15 RESET Legend: L = logic 0, H = logic 1, X = Don’t Care. See Characteristics for voltage levels. Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4. 2. Refer to the section on Sector Protection. Read Mode The Am29F400A has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (as- 8 suming the addresses have been stable for at least tACC-tOE time). Standby Mode There are two ways to implement the standby mode on the Am29F400A device, both using the CE pin. A CMOS standby mode is achieved with the CE input held at VCC ± 0.5 V. Under this condition the current is typically reduced to less than 5 µA. A TTL standby mode is achieved with the CE pin held at VIH. Under this condition the current is typically reduced to 1 mA. In the standby mode the outputs are in the high impedance state, independent of the OE input. Am29F400AT/Am29F400AB P R E L I M I N A R Y Output Disable Am29F400A is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 4 (see Autoselect Command Sequence). With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. The autoselect mode allows the reading of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don’t cares except A0, A1, and A6 (see Table 3). The autoselect mode also facilitates the determination of sector protection in the system. By performing a read operation at the address location XX02H with the higher order address bits A12–A17 set to the desired sector address, the device will return 01H for a protected sector and 00H for a non-protected sector. The manufacturer and device codes may also be read via the command register, for instances when the Table 3. Am29F400A Sector Protection Verify Autoselect Codes Type A12-A17 A6 A1 A0 Code (HEX) X VIL VIL VIL 01H X VIL VIL VIH VIL VIL VIH VIL VIH VIL Manufacturer Code-AMD 23H Byte Am29F400AT Word 2223H Am29F400A Device Byte ABH Am29F400AB X Word Sector Address Sector Protection 22ABH 01H* *Outputs 01H at protected sector addresses Table 4. Type Manufacturer Code-AMD Am29F400A Device Expanded Autoselect Code Table Code DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 01H 0 0 0 0 0 0 0 DQ DQ DQ DQ DQ DQ DQ DQ DQ 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z Am29F400AT(B) 23H (W) 2223H 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 Am29F400AB(B) ABH A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z (W) 22ABH 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 Sector Protection 01H 0 0 0 0 0 0 0 0 0 B) - Byte mode (W) - Word mode Am29F400AT/Am29F400AB 9 5.0 V-only Flash Byte 0 (A0 = VIL) represents the manufacturer’s code (AMD=01H) and byte 1 (A0 = VIH) the device identifier code (Am29F400AT = 23H and Am29F400AB = ABH for x8 mode; Am29F400AT = 2223H and Am29F400AB = 22ABH for x16 mode). These two bytes/words are given in the table below. All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be V IL (see Tables 3 and 4). Autoselect P R E L I M I N A R Y Table 5. Sector Address Tables (Am29F400AT) A17 A16 A15 A14 A13 A12 (x8) Address Range (x16) Address Range SA0 0 0 0 X X X 00000h-0FFFFh 00000h-07FFFh SA1 0 0 1 X X X 10000h-1FFFFh 08000h-0FFFFh SA2 0 1 0 X X X 20000h-2FFFFh 10000h-17FFFh SA3 0 1 1 X X X 30000h-3FFFFh 18000h-1FFFFh SA4 1 0 0 X X X 40000h-4FFFFh 20000h-27FFFh SA5 1 0 1 X X X 50000h-5FFFFh 28000h-2FFFFh SA6 1 1 0 X X X 60000h-6FFFFh 30000h-37FFFh SA7 1 1 1 0 X X 70000h-77FFFh 38000h-3BFFFh SA8 1 1 1 1 0 0 78000h-79FFFh 3C000h-3CFFFh SA9 1 1 1 1 0 1 7A000h-7BFFFh 3D000h-3DFFFh SA10 1 1 1 1 1 X 7C000h-7FFFFh 3E000h-3FFFFh Table 6. Sector Address Tables (Am29F400AB) A17 A16 A15 A14 A13 A12 (x8) Address Range (x16) Address Range SA0 0 0 0 0 0 X 00000h-03FFFh 00000h-01FFFh SA1 0 0 0 0 1 0 04000h-05FFFh 02000h-02FFFh SA2 0 0 0 0 1 1 06000h-07FFFh 03000h-03FFFh SA3 0 0 0 1 X X 08000h-0FFFFh 04000h-07FFFh SA4 0 0 1 X X X 10000h-1FFFFh 08000h-0FFFFh SA5 0 1 0 X X X 20000h-2FFFFh 10000h-17FFFh SA6 0 1 1 X X X 30000h-3FFFFh 18000h-1FFFFh SA7 1 0 0 X X X 40000h-4FFFFh 20000h-27FFFh SA8 1 0 1 X X X 50000h-5FFFFh 28000h-2FFFFh SA9 1 1 0 X X X 60000h-6FFFFh 30000h-37FFFh SA10 1 1 1 X X X 70000h-7FFFFh 38000h-3FFFFh Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written to by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. 10 Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Protection The Am29F400A features hardware sector protection. This feature will disable both program and erase operations in any combination of ten sectors of memory. The sector protect feature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected. Alternatively, AMD may program and protect sectors in the factory prior to shipping the device (AMD’s ExpressFlash Service). Am29F400AT/Am29F400AB P R E L I M I N A R Y It is possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02H, where the higher order address bits A12–A17 is the desired sector address, will produce a logical “1” at DQ0 for a protected sector. See Table 3 for Autoselect codes. Temporary Sector Unprotect Command Definitions Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 7 defines the valid r e g i s t e r c o m m a n d s e q u e n c e s. N o t e t h a t t h e Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover, both Reset/Read commands are functionally equivalent, resetting the device to the read mode. Am29F400AT/Am29F400AB 11 5.0 V-only Flash This feature allows temporary unprotection of previously protected sectors of the Am29F400A device in order to change data in-system. The Sector Unprotect mode is activated by setting the RESET pin to high voltage (12V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again. Refer to Figures 16 and 17. P R E L I M I N A R Y Table 7. Am29F400A Command Definitions (Notes 1–7) Command Sequence Read/Reset Bus Write Cycles Req’d First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Addr Addr Addr Data Addr Data Addr Addr Data Reset/Read 1 XXXXH F0H F0H RA RD 90H 01H 2223H (T Device ID) 22ABH (B Device ID) 2AAAH 55H 5555H 10H 5555H AAAAH Reset/ Read Word Data 5555H AAH 2AAAH 55H 5555H AAAAH AAAAH 3 Byte Word Autoselect Data 3 Byte 5555H 5555H AAH 2AAAH 55H 5555H AAAAH AAAAH 5555H 23H (T Device ID) ABH (B Device ID) Word /Byte Word 00H 4 Data 5555H AAH 2AAAH 55H 5555H A0H AAAAH AAAAH 01H (T/B Manuf. ID) PA PD 5555H AAH Program Byte Word 6 5555H 5555H AAH 2AAAH 55H 5555H AAAAH AAAAH 80H Chip Erase Byte Sector Erase Word 6 Byte 5555H 5555H AAH 2AAAH 55H 5555H AAAAH AAAAH Erase Suspend 1 XXXXH B0H Erase Resume 1 XXXXH 30H 5555H AAAAH 80H 5555H AAH AAAAH 2AAAH 55H SA 30H 5555H Notes: 1. Bus operations are defined in Tables 1 and 2. 2. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A17–A12 will uniquely select any sector. 3. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. 4. Reading from non-erasing sectors is allowed in the Erase Suspend mode. 5. Address bits A17–A15 are don’t care for unlock and command cycles. 6. The system should generate the following address patterns: Word Mode: 5555H or 2AAAH to addresses A0–A14 Byte Mode: AAAAH or 5555H to addresses A-1–A14. Read/Reset Command The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. 12 The device will automatically power-up in the read/ reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Am29F400AT/Am29F400AB P R E L I M I N A R Y Autoselect Command Flash memories are intended for use in applications where the local CPU can alter memory contents. As s u c h , m a nu f a c t u r e a n d d e v i c e c o d e s m u s t be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desirable system design practice. All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Furthermore, the write protect status of sectors can be read in this mode. Scanning the sector addresses (A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. To terminate the operation, it is necessary to write the read/reset command sequence into the register. Byte/Word Programming The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program setup command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming using the Embedded Program Algorithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see Table 8, Write Operation Status). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may cause the device to exceed programming time limits (DQ5 = 1) or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still “013”. Only erase operations can convert “0”s to “1”s. Figure 1 illustrates the Embedded Programming Algori t h m u s i n g t y p i c a l c o m m a n d s t r i n g s a n d bus operations. Chip Erase Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “setup” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. The erase is performed sequentially on all sectors at the same time (see Table “Erase and Programming Performance”). The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is “1” (see Write Operation Status section) at which time the device returns to read the mode. Figure 1 illustrates the Embedded Erase Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the sector erase command. The sector a d d r e s s ( a ny a d d r e s s l o c a t i o n w i t h i n t h e desired sector) is latched on the falling edge of WE, while the command (30H) is latched on the rising edge of WE. After a time-out of 100 µs from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased sequentially by writing the six bus cycle operations as described above. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be sequentially erased. The time between writes must be less than 100 µs otherwise that command will not be Am29F400AT/Am29F400AB 13 5.0 V-only Flash The device contains an autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the autoselect command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of 01H. A read cycle from address XX01H returns the device code (Am29F400AT = 23H and Am29F400AB = ABH for x8 mode; Am29F400AT = 2223H and Am29F400AB = 22ABH for x16 mode) (see Tables 3 and 4). Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. P R E L I M I N A R Y accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 100 µs from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 100 µs time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this period will reset the device to the read mode, ignoring the previous command string. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for DQ3, Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to10). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 100 µs time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7, Data Polling, is “1” (see Write Operation Status section) at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors being erased. Figure 1 illustrates the Embedded Erase Algorithm using typical command strings and bus operations. Erase Suspend The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written duri n g t h e C h i p E ra s e o p e r a t i o n o r E m b e d d e d Program Algorithm. Writing the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Any other command written during the Erase Suspend m o d e w i l l b e i g n o r e d ex c e p t t h e E r a s e Resume command. Writing the Erase Resume command resumes the erase operation. The addresses are “don’t-cares” when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of 15 µs to suspend the erase operation. When the device has entered the erase-suspended mode, DQ6 will stop toggling. The user must use the address of a sector being erased for reading DQ6 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be r e a d f r o m s e c t o r s t h a t h ave n o t b e e n erase-suspended. To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Write Operation Status Table 8. Write Operation Status Status DQ7 DQ6 DQ5 DQ3 Auto-Programming DQ7 Toggle 0 0 0 Toggle 0 1 DQ7 Toggle 1 0 0 Toggle 1 1 In Progress Program/Erase in Auto-Erase Exceeded Time Limits Auto-Programming Program/Erase in Auto-Erase Notes: 1. D8–D15 = Don’t Care for x16 mode. 2. DQ4 for AMD internal use only. 14 Am29F400AT/Am29F400AB P R E L I M I N A R Y DQ7 Data Polling For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling must be performed at sector addresses within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0–DQ6 may be still invalid. The valid data on DQ0–DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, or sector erase time-out (see Table 7). See Figure 10 for the Data Polling timing specifications and diagrams. DQ6 Toggle Bit The Am29F400A also features the “Toggle Bit” as a method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase, the Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause DQ6 to toggle. See Figure 11 for the Toggle Bit timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE pins will control the output disable functions as described in Table 1. The DQ5 failure condition will also appear if a user tries to program a 1 to a location that is previously programmed to 0. In this case the device locks out and never completes the Embedded Program Algorithm. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device. DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If DQ3 is low (“0”), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted. Refer to Table 8: Write Operation Status. Am29F400AT/Am29F400AB 15 5.0 V-only Flash The Am29F400A device features Data Polling as a method to indicate to the host that the embedded algori t h m s a r e i n p r o gr e s s o r c o m p l e t e d . D u r i n g the Embedded Program Algorithm an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 2. Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during the sector time-out. P R E L I M I N A R Y RY/BY Ready/Busy The Am29F400A provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or have been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the Am29F400A is placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin should be ignored while RESET is at VIL. Refer to Figure 12 for a detailed timing diagram. Since this is an open-drain output, several RY/BYpins can be tied together in parallel with a pull-up resistor to VCC. RESET Hardware Reset The Am29F400A device may be reset by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device requires an additional 50 ns before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be indeterminate. The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s microprocessor to read the boot-up firmware from the Flash memory. Byte/Word Configuration The BYTE pin selects the byte (8-bit) mode or word (16 bit) mode for the Am29F400A device. When this pin is driven high, the device operates in the word (16 16 bit) mode. The data is read and programmed at DQ0–DQ15. When this pin is driven low, the device operates in byte (8 bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit and DQ8–DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0–DQ7 and the DQ8–DQ15 bits are ignored. Refer to Figures 14 and 15 for the timing diagram. Data Protection The Am29F400A is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from V CC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, the Am29F400A locks out write cycles for VCC < VLKO (see DC Characteristics section for voltages). When VCC < VLKO, the command register is d i s a bl e d , a l l i n t e r n a l p r o gra m / e ra s e c i r c u i t s are disabled, and the device resets to the read mode. The Am29F400A ignores all writes until VCC > VLKO. The user must ensure that the control pins are in the correct logic state when VCC > VLKO to prevent unintentional writes. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL,CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. Am29F400AT/Am29F400AB P R E L I M I N A R Y EMBEDDED ALGORITHMS Start Write Program Command Sequence (see below) Data Poll Device 5.0 V-only Flash No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data 20380B-8 Figure 1. Embedded Programming Algorithm Am29F400AT/Am29F400AB 17 P R E L I M I N A R Y EMBEDDED ALGORITHMS Start Write Erase Command Sequence (see below) Data Polling or Toggle Bit Successfully Completed Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/10H Sector Address/30H Sector Address/30H Additional sector erase commands are optional Sector Address/30H 20380B-9 Note: To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted. Figure 2. 18 Embedded Erase Algorithm Am29F400AT/Am29F400AB P R E L I M I N A R Y Start VA = Byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = Valid address equals any non-protected sector group address during chip erase Read Byte (DQ0-DQ7) Addr=VA DQ7=Data ? Yes No 5.0 V-only Flash No DQ5=1 ? Yes Read Byte (DQ0-DQ7) Addr=VA DQ7=Data ? No Yes Pass Fail 20380B-10 Note: DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 3. Data Polling Algorithm Am29F400AT/Am29F400AB 19 P R E L I M I N A R Y Start Read Byte (DQ0–DQ7) Addr=Don’t Care DQ6=Toggle ? No Yes No DQ5=1 ? Yes Read Byte (DQ0–DQ7) Addr=Don’t Care DQ6=Toggle ? No Yes Pass Fail 20380B-11 Note: DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”. Figure 4. Toggle Bit Algorithm 20 ns 20 ns +0.8 V -0.5 V -2.0 V 20380B-12 20 ns Figure 5. Maximum Negative Overshoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns Figure 6. 20 20 ns Maximum Positive Overshoot Waveform Am29F400AT/Am29F400AB 20380B-13 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65°C to +125°C Commercial (C) Devices Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55°C to +125°C Industrial (I) Devices Voltage with Respect to Ground All pins except A9, OE and RESET (Note 1) . . . . . . . . . . . . . . . . . . . . . . . -2.0 V to +7.0 V Extended (E) Devices Ambient Temperature (TA). . . . . . . . . . . . 0˚C to +70˚C Ambient Temperature (TA). . . . . . . . . . -40˚C to +85˚C Ambient Temperature (TA). . . . . . . . . -55˚C to +125˚C VCC Supply Voltages VCC for Am29F400T/B-65, . . . . . . +4.75 V to +5.25 V Output Short Circuit Current (Note 3) . . . . . . 200 mA VCC for Am29F400T/B-70, -90, -120, -150 . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 7 and Figure 8. Operating ranges define those limits between which the functionality of the device is guaranteed. 2. Minimum DC input voltage on pins A9, OE, and RESET is -0.5 V. During voltage transitions, A9, OE, and RESET may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. See Figure 7 and Figure 8. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Am29F400AT/Am29F400AB 21 5.0 V-only Flash VCC (Note 1). . . . . . . . . . . . . . . . . . . . -2.0 V to +7.0 V A9, OE, and RESET (Note 2). . . . . . -2.0 V to +13.0 V P R E L I M I N A R Y DC CHARACTERISTICS TTL/NMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Max Unit ±1.0 µA 50 µA ±1.0 µA ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ILIT A9, OE, RESET Input Load Current VCC = VCC Max, A9, OE, RESET = 12.5 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ICC1 VCC Active Read Current (Note 1) CE = VIL, OE = VIH ICC2 VCC Active Program/Erase Current (Notes 2, 3) CE = VIL, OE = VIH 60 mA ICC3 VCC Standby Current VCC = VCC Max, CE = VIH, OE = VIH 1.0 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V 11.5 12.5 V 0.45 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min VOH Output High Voltage IOH = -2.5 mA, VCC = VCC Min VLKO Low VCC Lock-Out Voltage Byte 40 Word 50 mA 2.4 3.2 V 4.2 Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Program or Erase Algorithm is in progress. 3. Not 100% tested. 22 Am29F400AT/Am29F400AB V P R E L I M I N A R Y DC CHARACTERISTICS (continued) CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ILIT A9, OE, RESET Input Load Current VCC = VCC Max, A9, OE, ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ICC1 VCC Active Read Current (Note 1) CE = VIL, OE = VIH ICC2 VCC Active Program/Erase Current (Notes 2, 3) ICC3 VCC Standby Current (Note 4) VIL Input Low Voltage VIH Input High Voltage VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min Output Low Voltage VOH2 VLKO RESET = 12.5 V Max Unit ±1.0 µA 50 µA ±1.0 µA Byte 20 40 Word 28 50 CE = VIL, OE = VIH 30 50 mA VCC = VCC Max, CE = VIH, OE = VIH 1 5 µA -0.5 0.8 V 0.7 x VCC VCC + 0.3 V 11.5 12.5 V 0.45 V mA IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V IOH = –100 µA, VCC = VCC Min VCC -0.4 V Low VCC Lock-Out Voltage 3.2 4.2 V Notes: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. ICC active while Embedded Program or Erase Algorithm is in progress. 3. Not 100% tested. 4. ICC3 = 20 µA max at extended temperatures (> +85°C). Am29F400AT/Am29F400AB 23 5.0 V-only Flash VOH1 Typ P R E L I M I N A R Y AC CHARACTERISTICS Read-Only Operations Characteristics Parameter Symbols Speed Option (Notes 1 and 2) JEDEC Standard Description tAVAV tRC Test Setup Read Cycle Time (Note 4) -65 -70 -90 -120 -150 Unit Min 60 70 90 120 150 ns CE = VIL OE = VIL Max 60 70 90 120 150 ns tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay OE = VIL Max 60 70 90 120 150 ns tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 55 ns tEHQZ tDF Chip Enable to Output High Z (Notes 3, 4) Max 20 20 20 30 35 ns tGHQZ tDF Output Enable to Output High Z (Notes 3, 4) Max 20 20 20 30 35 ns tAXQX tOH Output Hold Time From Addresses, CE or OE, Whichever Occurs First Min 0 0 0 0 0 ns tReady RESET Pin Low to Read Mode (Note 4) Max 20 20 20 20 20 µs tELFL tELFH CE to BYTE Switching Low or High Max 5 5 5 5 5 ns Notes: Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level: 0.8 V and 2.0 V input and output 1. Test Conditions (for -65 only) Output Load: 1 TTL gate and 30 pF Input Rise and Fall Times: 5 ns Input Pulse Levels:0.0 V to 3.0 V Timing Measurement Reference Level: 1.5 V input and output 3. Output Driver Disable Time 4. Not 100% tested. 2. Test Conditions (for -70, -90, -120, -150) Output Load: 1 TTL gate and 100 pF Input Rise and Fall Times: 20 ns 5.0 V IN3064 or Equivalent Device Under Test CL 6.2 kΩ 2.7 kΩ IN3064 or Equivalent IN3064 or Equivalent Notes: For -65: CL = 30 pF including jig capacitance IN3064 or Equivalent For all others: CL = 100 pF including jig capacitance 20380B-14 Figure 7. 24 Test Conditions Am29F400AT/Am29F400AB P R E L I M I N A R Y AC CHARACTERISTICS Write (Erase/Program) Operations Parameter Symbols Speed Option (Notes 1 and 2) JEDEC Standard Description -70 -90 -120 -150 Unit tAVAV tWC Write Cycle Time Min 60 70 90 120 150 ns tAVWL tAS Address Setup Time Min 0 0 0 0 0 ns tWLAX tAH Address Hold Time Min 45 45 45 50 150 ns tDVWH tDS Data Setup Time Min 30 30 45 50 50 ns tWHDX tDH Data Hold Time Min 0 0 0 0 0 ns Output Enable Hold Time Read (Note 2) Min 0 0 0 0 0 ns tOEH Toggle and Data Polling (Note 2) Min 10 10 10 10 10 ns tGHWL tGHWL Read Recovery Time Before Write (OE High to WE Low) Min 0 0 0 0 0 ns tELWL tCS CE Setup Time Min 0 0 0 0 0 ns tWHEH tCH CE Hold Time Min 0 0 0 0 0 ns tWLWH tWP Write Pulse Width Min 35 35 45 50 50 ns tWHDL tWPH Write Pulse Width High Min 20 20 20 20 20 ns Byte Typ 7 7 7 7 7 tWHWH1 tWHWH1 Programming Operation µs Word Typ 14 14 14 14 14 µs Typ 1.0 1.0 1.0 1.0 1.0 sec tWHWH2 tWHWH2 Sector Erase Operation (Note 1) Max 8 8 8 8 8 sec tVCS VCC Setup Time (Note 2) Min 50 50 50 50 50 µs tVIDR Rise Time to VID (Notes 2, 3) Min 500 500 500 500 500 ns Min 4 4 4 4 4 µs tOESP OE Setup Time to WE Active (Notes 2, 3) tRP RESET Pulse Width Min 500 500 500 500 500 ns tFLQZ BYTE Switching Low to Output High Z (Notes 3, 4) Max 20 20 30 30 30 ns tBUSY Program/Erase Valid to RY/BY Delay (Note 2) Min 30 30 35 50 55 ns tRESSP RESET Setup Time to WE Active Min 4 4 4 4 4 µs Notes: 1. This does not include the preprogramming time. 2. Not 100% tested. 3. These timings are for Temporary Sector Unprotect operation. 4. Output Driver Disable Time. Am29F400AT/Am29F400AB 25 5.0 V-only Flash -65 P R E L I M I N A R Y KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Be Changing from H to L May Change from L to H Will Be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010 SWITCHING WAVEFORMS tRC Addresses Addresses Stable tACC CE (tDF) tOE OE tOEH WE (tCE) (tOH) Outputs High Z Output Valid High Z 20380B-15 Figure 8. 26 AC Waveforms for Read Operations Am29F400AT/Am29F400AB P R E L I M I N A R Y SWITCHING WAVEFORMS 3rd Bus Cycle Data Polling PA PA 5555H Addresses tWC tRC tAH tAS CE tGHWL OE WE tWPH tCS tDH Data PD A0H tDF tOE DQ7 DOUT tDS tOH 5.0 V tCE 20380B-16 Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. These waveforms are for the x16 mode. Figure 9. Program Operation Timings tAH Addresses 2AAAH 5555H 5555H 5555H 2AAAH SA tAS CE tGHWL OE tWP WE tWPH tCS tDH tDS AAH Data VCC 55H 80H AAH tVCS 55H 10H/30H 20380B-17 Notes: 1. SA is the sector address for Sector Erase. Addresses = don’t care for Chip Erase. 2. These waveforms are for the x16 mode. Figure 10. AC Waveforms Chip/Sector Erase Operations Am29F400AT/Am29F400AB 27 5.0 V-only Flash tWHWH1 tWP P R E L I M I N A R Y SWITCHING WAVEFORMS tCH CE tDF tOE OE tOEH WE tCE * DQ7 tOH DQ7= Valid Data DQ7 High Z tWHWH 1 or 2 DQ0-DQ6=Invalid DQ0-DQ6 DQ0-DQ6 Valid Data 20380B-18 Note: *DQ7=Valid Data (The device has completed the Embedded operation). Figure 11. AC Waveforms for Data Polling During Embedded Algorithm Operations CE tOEH WE OE * Data (DQ0-DQ7) DQ6=Toggle DQ6= Stop Toggling DQ6=Toggle DQ0-DQ7 Valid tOE 20380B-19 Note: *DQ6 stops toggling (The device has completed the Embedded operation). Figure 12. 28 AC Waveforms for Toggle Bit During Embedded Algorithm Operations Am29F400AT/Am29F400AB P R E L I M I N A R Y SWITCHING WAVEFORMS CE The rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY 5.0 V-only Flash Figure 13. 20380B-20 RY/BY Timing Diagram During Program/Erase Operations RESET tRP tReady 20380B-21 Figure 14. RESET Timing Diagram Am29F400AT/Am29F400AB 29 P R E L I M I N A R Y SWITCHING WAVEFORMS CE OE BYTE tELFL tELFH DQ0-DQ14 Data Output (DQ0-DQ14) DQ15 Output DQ15/A-1 Data Output (DQ0-DQ7) Address Input tFLQZ 20380B-22 Figure 15. BYTE Timing Diagram for Read Operation CE The falling edge of the last WE signal WE BYTE tSET (tAS) tHOLD (tAH) 20380B-23 Figure 16. 30 BYTE Timing Diagram for Write Operations Am29F400AT/Am29F400AB P R E L I M I N A R Y Start RESET = VID (Note 1) Perform Erase or Program Operations Temporary Sector Group Unprotect Completed (Note 2) 20380B-24 Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 17. Temporary Sector Unprotect Algorithm 5V RESET 12 V tVIDR CE WE Program or Erase Command Sequence RY/BY 20380B-25 Figure 18. Temporary Sector Unprotect Timing Diagram Am29F400AT/Am29F400AB 31 5.0 V-only Flash RESET = VIH P R E L I M I N A R Y AC CHARACTERISTICS Write/Erase/Program Operations Alternate CE Controlled Writes Parameter Symbols JEDEC Speed Option (Notes 1 and 2) Standard Description -65 -70 -90 -120 -150 Unit tAVAV tWC Write Cycle Time (Note 2) Min 60 70 90 120 150 ns tAVEL tAS Address Setup Time Min 0 0 0 0 0 ns tELAX tAH Address Hold Time Min 45 45 45 50 50 ns tDVEH tDS Data Setup Time Min 30 30 45 50 50 ns tEHDX tDH Data Hold Time Min 0 0 0 0 0 ns tOES Output Enable Setup Time Min 0 0 0 0 0 ns Read (Note 2) Min 0 0 0 0 0 ns tOEH Output Enable Hold Time Toggle and Data Polling (Note 2) Min 10 10 10 10 10 ns tGHEL tGHEL Read Recover Time Before Write Min 0 0 0 0 0 ns tWLEL tWS WE Setup Time Min 0 0 0 0 0 ns tEHWH tWH WE Hold Time Min 0 0 0 0 0 ns tELEH tCP CE Pulse Width Min 35 35 45 50 50 ns tEHEL tCPH CE Pulse Width High Min 20 20 20 20 20 ns Byte Typ 7 7 7 7 7 tWHWH1 tWHWH1 Programming Operation µs Word Typ 14 14 14 14 14 µs Typ 1.0 1.0 1.0 1.0 1.0 sec tWHWH2 tWHWH2 Sector Erase Operation (Note 1) Max 8 8 8 8 8 sec Max 20 20 30 30 30 ns tFLQZ BYTE Switching Low to Output High Z (Note 2) Notes: 1. This does not include the preprogramming time. 2. Not 100% tested. 32 Am29F400AT/Am29F400AB P R E L I M I N A R Y SWITCHING WAVEFORMS Data Polling Addresses PA PA 5555H tWC tAH tAS WE tGHEL OE tCP tWS 5.0 V-only Flash CE tWHWH1 tCPH tDH Data PD A0H DQ7 DOUT tDS 5.0 Volt 20380B-26 Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6. These waveforms are for the x16 mode. Figure 19. Alternate CE Controlled Program Operation Timings ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Typ (Note 1) Max Unit Comments Sector Erase Time 1.0 8 sec Excludes 00H programming prior to erasure Chip Erase Time 11 88 sec Excludes 00H programming prior to erasure Byte Programming Time 7 300 (Note 3) µs Excludes system-level overhead (Note 4) Word Programming Time 14 600 µs Excludes system-level overhead (Note 4) Chip Programming Time 3.6 10.8 (Notes 3, 5) sec Excludes system-level overhead (Note 4) Notes: 1. 25°C, 5.0 V VCC, 100,000 cycles. 2. Although Embedded Algorithms allow for longer chip program and erase time, the actual time will be considerably less since bytes program or erase significantly faster than the worst case byte. 3. Under worst case condition of 90°C, 4.5 V VCC, 100,000 cycles. 4. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte. In the preprogramming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure. 5. The Embedded Algorithms allow for 2.5 ms byte program time. DQ5 = “1” only after a byte takes the theoretical maximum time to program. A minimal number of bytes may require significantly more programming pulses than the typical byte. The majority of the bytes will program within one or two pulses. This is demonstrated by the Typical and Maximum Programming Times listed above. Am29F400AT/Am29F400AB 33 P R E L I M I N A R Y LATCHUP CHARACTERISTICS Input Voltage with respect to VSS on all I/O pins VCC Current Min Max –1.0 V VCC + 1.0 V –100 mA +100 mA Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. TSOP PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 CIN2 Control Pin Capacitance VIN = 0 CIN Typ Max Unit 6 7.5 pF 8.5 12 pF 8 10 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. SO PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VPP = 0 8 10 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time 34 Am29F400AT/Am29F400AB P R E L I M I N A R Y REVISION SUMMARY Erase Suspend: Distinctive Characteristics: Third paragraph, third sentence: Deleted the word “NOT.” High Performance: The fastest speed option available is now 60 ns. Operating Ranges: Enhanced power management for standby mode: Changed typical standby current to 1µA. General Description: First paragraph, first sentence should read, “...organized as 512 Kbytes of 8 bits each or 256 Kwords of 16 bits each.” Added 60 ns speed option. VCC Supply Voltages: Added -65 and deleted -75 speed options in the list. Changed A9 maximum to +13.0 V. DC Characteristics: CMOS Compatible: Revised ICC specifications. Added Note 4 (refers to ICC3). AC Characteristics: Read Only Operations Characteristics: Added the -65 column and test conditions. Added -65 column (60 ns, ±5% VCC). Added -70 (70 ns, ±10% VCC) and deleted -75 speed option. Replaced -75 column with -70 column. Ordering Information, Standard Products: Test Conditions, Figure 7: The -65 speed option is now listed in the example. Changed speed option in first CL statement from -75 to -65. Valid Combinations: Added -65 and -70, and deleted 75 speed options. AC Characteristics: Corrected WE for read operations; was don’t care (X), is now H. Write/Erase/Program Operations, Alternate CE Controlled Writes: Added the -65 column. Replaced -75 column with -70 column. Revised sector erase and programming specifications. Standby Mode: Erase and Programming Performance: Corrected standby mode current; was 100 µA, is now 5 µA. Revised specifications in table. Clarified table and notes. Table 5, Sector Address Tables (Am29F400AB): Revised Note 5 to cover all upper address bits that are don’t care. Tables 1 and 2, User Bus Operations: Corrected x16 starting address for SA5; was 1C000h, is now 28000h. Table 7, Command Definitions Deleted Note 6. Am29F400AT/Am29F400AB 35 5.0 V-only Flash Product Selector Guide: