APL1581 DUAL INPUT LOW DROPOUT REGULATOR Features General Description • Adjustable or Fixed Output • 520mV typ. Dropout at 5A in Dual Power Voltage Mode • • Remote Sense Pin Available 2% Accuracy Over Temperature Range • • Build-in Over Temperature Protection Build-in Current Limit • 5 Pin TO-220 and TO-263, TO-252, SOP-8-P Packages • Lead Free and Green Devices Available The APL1581 series of high performance positive voltage regulators are designed for use in applications requiring very low dropout voltage at 5Amp. The APL1581 can provide a output voltage at the range of 1.25V to 2.55V where both 5V and 3.3V voltage supplies are available. The superior dropout characteristics result in reducing heat dissipation compared to regular LDOs. The APL1581 also provides excellent regulation over line, load, and temperature variations. (RoHS Compliant) Current limit is trimmed to ensure specified output cur- Applications rent and controlled short-circuit current. On-chip thermal limiting provides protection against any combina- • Microprocessor Supplies tion of overload that would create excessive junction temperature. • • Chip Set Supplies VGA Card Power The APL1581 is available in both the through-hole and • LCD Monitor Power TO-220 and TO-263, TO-252, SOP-8P power packages. surface mount versions of the industry standard 5-Pin Ordering and Marking Information APL1581 Assembly Material Handling Code Temperature Range Package Code Voltage Code APL1581-15 F/G/U : 15 APL1581 XXXXX - Date Code XXXXX Package Code F : TO-220-5 G : TO-263-5 U :TO-252-5 KA : SOP-8P Temperature Range C : 0 to 70° C Handling Code TR : Tape & Reel Voltage Code : 15 : 1.5V 18 : 1.8V 25 : 2.5V Blank : Adjustable Version Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APL1581 KA : APL1581 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 1 www.anpec.com.tw APL1581 Pin Configuration TAB is VOUT 5 VIN 4 VCNTL 3 VOUT 2 ADJ (or GND) 2 ADJ(or GND) 1 VSENSE 1 VSENSE VIN 4 TAB is VOUT VCNTL 3 VIN 4 VCNTL 3 VOUT Front View of TO-252-5 Front View of TO-220-5 5 TAB is VOUT 5 VOUT 2 ADJ (or GND) 1 VSENSE VSENSE 1 8 VOUT ADJ (or GND) 2 7 VOUT VCNTL 3 6 VOUT VIN 4 5 VOUT SOP-8-P (Top View) NC = No internal connection Front View of TO-263-5 = Thermal Pad (connected to VOUT plane for better heat dissipation) Pin 5~8 must be connected together by a shortest wide track or plane. Pin Description PIN Description Name I/O VSENSE I Positive side of the reference voltage, which allows remote sensing to obtain excellent load regulation. ADJ O Negative side of the reference voltage, which allows to use resistor divider to set an expect output voltage. A small bypass capacitor can be connected from this pin to ground to improve PSRR performance. GND O For fixed voltage devices this is the bottom of the resistor divider that sets the output voltage. VOUT O Output pin of the regulator, which connects to the TAB. A minimum of 10µF capacitor must be connected from this pin to ground to ensure the stability. VCNTL I Supply pin of the control circuitry, which must be always higher than VOUT for the device to regulate. (See electrical characteristics) VIN I Power input pin of the regulator, which must be always higher than VOUT for the device to regulate. (See electrical characteristics) Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 2 www.anpec.com.tw APL1581 Block Diagram VOUT VIN VCNTL Current Limit Thermal Protection Absolute Maximum Ratings Symbol VIN VCNTL VSENSE Voltage Regulation ADJ/GND (Note 1, 2) Parameter Rating Unit Input Voltage 7 V Control Voltage 7 V Internally Limited W 150 °C -65 to +150 °C 260 °C PD Power Dissipation TJ Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: The maximum allowable power dissipation at any TA (ambient temperature) is calculated using: PD (max) = (TJ – TA) / θJA; TJ = 125°C. Exceeding the maximum allowable power dissipation will result in excessive die temperature. Thermal Characteristics Symbol Parameter Typical Value Unit (Note 3) θJA θJC Junction-to-Ambient Resistance in free air TO-263-5 (Toplayer plane size : 15mm x 15 mm) TO-252-5 (Toplayer plane size : 10mm x 10 mm) SOP-8-P (Toplayer plane size : 10mm x 10 mm) (Note 4) Junction-to-Case Resistance TO-220-5 TO-263-5 TO-252-5 28 42 68 3 4 5 o C/W o C/W Note 3: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The sizes of the rectangular plane, where the devices are mounted, are shown in the table. Note 4: The case temperature is measured on the TAB of the device mounted on the test board described in Note 3 except the package TO-220-5. The case temperature of the TO-220-5 is measured on the bottom of the case directly below the die. Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 3 www.anpec.com.tw APL1581 Electrical Characteristics Unless otherwise noted , these specifications apply over CIN = 10µF, CCNTL = 1µF, COUT = 10µF, and TA = 0 to 70°C. Typical values refer to TA = 25°C. VOUT = VSENSE. Symbol VREF VOUT REGLINE REGLOAD VCNTL-VOUT VIN-VOUT ILIMIT ILMIN REGTHERMAL PSRR ICNTL IGND IADJ Parameter Reference Voltage APL1581 Output Voltage APL1581-15 APL1581-18 APL1581-25 Line Regulation APL1581 APL1581-15 APL1581-18 APL1581-25 Load Regulation (Note 5) APL1581 APL1581-15 APL1581-18 APL1581-25 Dropout Voltage (Note 6) APL1581 APL1581-15 APL1581-18 APL1581-25 Dropout Voltage (Note 6) APL1581 APL1581-15 APL1581-18 APL1581-25 Current Limit Minimum Load Current (Note7) APL1581 Thermal Regulation Power Supply Ripple Rejection APL1581 APL1581-15 APL1581-18 APL1581-25 CNTL Pin Current Ground Pin Current APL1581-15 APL1581-18 APL1581-25 Adjust Pin Current APL1581 Test Conditions VCNTL=2.75~5.5V, VIN=2.05~5.5V, IO =10mA~5A, VADJ=0V (IO =0~5A for fixed versions) VCNTL=3~5.5V , VIN=2.3~5.5V VCNTL=3.3~5.5V , VIN=2.6~5.5V VCNTL=4~5.5V , VIN=3.3~5.5V (IO =0A for fixed versions) VCNTL=2.75~5.5V, VIN=1.75~5.5V, IO =10mA, VADJ=0V VCNTL=3~5.5V, VIN=2.3~5.5V VCNTL=3.3~5.5V, VIN=2.6~5.5V VCNTL=4~5.5V, VIN=3~5.5V (IO =0~5A for fixed versions) VCNTL=2.75V, VIN=2.1V, VADJ =0V, IO =10mA~5A VCNTL=3V, VIN=2.35V VCNTL=3.3V, VIN=2.65V VCNTL=4V, VIN=3.35V IO =5A for all versions VIN=2.05V, VADJ =0V VIN=2.3V VIN=2.6V VIN=3.3V IO =5A for all versions VCNTL=2.75V, VADJ =0V VCNTL=3V VCNTL=3.3V VCNTL=4V VCNTL-VOUT=1.5V, VIN-VOUT=0.6V MIN APL1581 TYP MAX 1.225 1.250 1.275 V 1.470 1.764 2.450 1.500 1.800 2.500 1.530 1.836 2.550 V 3 mV 5 mV 1.20 1.35 V 0.52 0.75 V 5 UNIT A VCNTL=5V, VIN=3.3V, VADJ =0V 0.8 30ms Pulse VRIPPLE=1VPP at 120Hz, IO=5A 0.01 %/W 70 dB VCNTL=5V, VIN=5V, VADJ =0V VCNTL=5.25V, VIN=5.25V VCNTL=5.55V, VIN=5.55V VCNTL=6.25V, VIN=6.25V VCNTL-VOUT=1.5V, VIN-VOUT=0.8V, IO =5A VCNTL =3V, VIN =2.3V VCNTL =3.3V, VIN =2.6V VCNTL =4V, VIN =3.3V VCNTL=2.75V, VIN=2.05V , VADJ =0V 60 10 mA 45 120 mA 8 13 mA 50 120 µA Note 5 : Low duty cycle pulse test with Kelvin connections are required to maintain data accuracy . Note 6 : Dropout voltage is defined as the minimum difference between VIN and VOUT required to maintain 1% VOUT regulation. Note 7 : Minimum load current is defined as the minimum current required at the output to maintain VOUT regulation. Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 4 www.anpec.com.tw APL1581 Application Circuit (1) Adjustable Output Voltage Device VIN VIN VOUT VOUT +3.3V +2.5V/5A APL1581 (Adj.) VCNT L VCNTL +5V VSENSE ADJ CCNTL 10uF V REF R1 120 COUT 470uF CIN 100uF R2 120 GND GND * VOUT = VREF ( 1+ R2 / R1 ) + IADJ * R2 where VREF =1.25V (typical) IADJ=50µA (typical) * R1 is typically in range of 100Ω to 125Ω to satisfy the minimum load current requirement. (2) Fixed Output Voltage Device V IN VIN V OUT VOUT +3.3V +2.5V/5A APL1581-25 V CNT L VCNTL +5V VSENSE GND CCNTL 10uF COUT 470uF CIN 100uF GND GND (3) With Enable Control Application VIN VIN +3.3V Q1 VCNT L +5V VCNTL 10k +2.5V/5A VSENSE ADJ Q2 Enable VOUT VOUT APL1581 (Adj.) CCNTL 10uF V REF R1 120 CIN 100uF COUT 470uF R2 120 10k GND GND Q1 : APM2301A Q2 : APM2300A Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 5 www.anpec.com.tw APL1581 Typical Characteristics Adjust Pin Current vs. Junction Temperature 1.275 80 1.270 70 Adjust Pin Current (uA) Reference Voltage (V) Reference Voltage vs. Junction Temperature 1.265 1.260 1.255 1.250 1.245 1.240 1.235 60 50 40 30 20 10 1.230 0 1.225 -50 -25 0 25 50 75 100 125 -50 150 -25 Junction Temperature (°C) 50 75 100 125 150 VIN-VOUT Dropout Voltage vs. Output Current 700 VIN-VOUT Dropout Voltage (mV) 1.2 Minimum Load Current (mA) 25 Junction Temperature (°C) Minimum Load Current vs. Junction Temperature 1.0 VCNTL-VOUT=10.75V 0.8 VCNTL-VOUT=1.45V 0.6 0.4 0.2 0.0 -50 0 TJ=125°C 600 500 TJ=25°C 400 300 TJ=-50°C 200 100 0 -25 0 25 50 75 100 125 150 0 1 1.5 2 2.5 3 3.5 4 4.5 5 Output Current (A) Junction Temperature (°C) Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 0.5 6 www.anpec.com.tw APL1581 Typical Characteristics Short-Circuit Current vs. Junction Temperature VCONTROL-VOUT Dropout Voltage vs. Output Current 1.4 VCNTL-VOUT Dropout Voltaage (V) 14 Short-Circuit Current (A) VIN=5.0V 12 10 VIN=3.3V 8 6 4 2 0 -50 TJ=-50°C TJ=0°C 1.3 1.2 1.1 TJ=25°C 1.0 0.9 TJ=125°C 0.8 0.7 -25 0 25 50 75 100 125 0 150 0.5 1 1.5 Junction Temperature (°C) 2.5 3 3.5 4 4.5 5 Output Current (A) Control Pin Current vs. Output Current Control Pin Current vs. Output Current VIN-VOUT=0.6V VIN-VOUT=0.8V 80 160 TJ=125°C 140 VCNTL Pin Current (mA) VCNTL Pin Current (mA) 2 120 100 TJ=25°C 80 60 TJ=0°C 40 TJ=-50°C TJ=75°C 20 TJ=-50°C 70 TJ=0°C 60 TJ=25°C 50 TJ=75°C 40 30 TJ=125°C 20 10 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 1.5 2 2.5 3 3.5 4 4.5 5 Output Current (A) Output Current (A) Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 0.5 7 www.anpec.com.tw APL1581 Typical Characteristics Control Pin Current vs. Output Current VIN-VOUT=1.0V VIN-VOUT=4.25V 80 70 VCNTL Pin Current (mA) TJ=-50°C 70 VCNTL Pin Current (mA) Control Pin Current vs. Output Current TJ=0°C 60 TJ=25°C 50 TJ=75°C 40 30 20 TJ=125°C 10 0 60 TJ=-50°C TJ=0°C 50 TJ=25°C 40 TJ=75°C 30 20 TJ=125°C 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Output Current (A) Output Current (A) Application Information General APL1581 is available in SOP-8P, TO-252-5, The APL1581 (adjustable or fixed) regulator is a 5 ter- TO-263-5, and TO-220-5 packages to meet different power dissipation applications. minal device designed specifically to provide extremely low dropout voltages comparable to the PNP type with- Output Voltage Setting out the disadvantage of the extra power dissipation See Figure 1 Adjustable APL1581 develops a 1.25V due to the base current associated with PNP regulators. reference voltage between the VSENSE pin and the This is done by bringing out the control pin of the regu- ADJ pin. Placing a resistor between these two termi- lator that provides the base current to the power NPN nals causes a constant current to flow through R1 and and connecting it to a voltage that is greater than the down through R2 to set the overall output voltage. In voltage present at the VIN pin. This flexibility makes general, R1 is chosen so that this current is the speci- APL1581 ideal for applications where dual inputs are fied minimum load current of 10mA.The current out of available, such as a computer motherboard with an the ADJ pin is small, typically 50µA and itadds to the ATX power supply that provides 5V and 3.3V to the current from R1. Because IADJ is very small, it needs board. to be considered only when very precise output volt- APL1581 is equipped with a 1.25V reference, preci- age setting is required. For best regulation, the top of sion and fast voltage regulations, on-chip current and the resistor divider should be connected directly to thermal limits, and remote sensing capability to reduce system total cost. the SENSE pin. The adjustable APL1581 can be pro- Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 8 www.anpec.com.tw APL1581 Application Information (Cont.) Output Voltage Setting (Cont.) regardless of whether they are inside or outside the grammable to any voltages in the range of 1.25V to 5.5V regulation loop. according to the following formula: VOUT VIN R2 ) + IADJ x R2 R1 VOUT = VREF x (1+ VIN VOU T APL1581 VCNTL VCN TL VSENSE AD J Load R1 where VREF = 1.25V (typical) Adjustable Device IADJ = 50µA (typical) R2 The recommended R1 is in range of 100Ω to125Ω to RP satisfy the minimum load current requirement. Proper sizes of R2 and R1 are also concerned for power VOUT VIN VIN dissipation. APL1581 VCNTL VIN VOU T VIN VCN TL VSENSE GN D Load VOUT VOU T APL1581 VCNT L VCNTL VSENSE AD J VRE F IA DJ=50uA Fixed Voltage Device R1 RP Figure 2 Remote Voltage Sensing R2 Stability and Output Capacitors Figure 1 Setting Output Voltage The circuit design of using the APL1581 series requires an output capacitor as part of the device fre- Grounding and Output Sensing quency compensation. The following chart shows a The APL1581 allows true Kelvin sensing for both the stable region to select output capacitor for APL1581. high and low side of the load. Figure 2 shows the de- This region above the curve indicates minimum re- vice connected to take advantage of the remote sense quired ESR and capacitance to maintain stability. feature. The SENSE pin and the top of the resistor However, the output capacitor should have an ESR divider are connected to the top of the load; the bot- less than1Ω. tom of the resistor divider is connected to the bottom 100 and parasitic resistance RP is made up of the PC traces 80 ESR (mΩ) of the load. Typically the load is a microprocessor and /or connector resistance between the regulator and the processor. RP is now connectedinside the regulation loop of the APL1581 and for reasonable val- 40 20 ues of RP the load regulation at the load will be 0 1 negligible. Voltage drops due to RP are not eliminated; they will add to the dropout voltage of the regulator Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 Stable Region 60 9 10 100 Capacitance(µF) 1000 www.anpec.com.tw APL1581 Application Information (Cont.) Stability and Output Capacitors (Cont.) exceeded under continuous normal load conditions. A low-ESR solid tantalum and aluminum electrolytic Careful consideration must be given to all sources of capacitor (ESR<1Ω) works extremely well and provides thermal resistance from junction to ambient, includ- good transient response and stability over temperature. ing junction-to-case, case-to-heat sink interface, and Ultra-low-ESR capacitors, such as ceramic chip heat sink resistance itself. capacitors, may promote unstable or under-damped See Figure 3 The SOP-8P is a cost-effective package transient response, but proper ceramic chip capaci- featuring a small size as a standard SOP-8 and a tors placed near loads can be used as decoupling bottom thermal pad to minimize the thermal resistance capacitors. of the package, being applicable to high current The output capacitors are also used to reduce the slew applications. The thermal pad is soldered to the top rate of load current and help the APL1581 to minimize VOUT plane which may be connected to internal or variations of the output voltage, improving transient bottom VOUT plane by vias to reduce the heat sink response. For this purpose, the low-ESR capacitors thermal resistance. Therefore, the printed circuit board are recommended. (PCB) forms a heat sink and dissipates heat into ambient air. Input Capacitors The input capacitors of VCNTL and VIN pins are not Top layer VOUT plane for Heat Dissi p a t i o n (L a rg e r a re a i s better) required for stability but for supplying surge currents during large load transients, and this will prevent the C OUT input rail from drooping and improve the performance of the APL1581. Because parasitic inductors from voltage sources or other bulk capacitors to the VCNTL and VIN pins will limit the slew rate of the surge cur8 rents during large load transients, resulting in voltage 7 6 5 Load drop at VIN and VCNTL pins. Vias Vias A capacitor of 1µF (ceramic chip capacitor) or greater (aluminum electrolytic capacitor) is recommended and 1 connected near VCNTL pin. For VIN pin, an aluminum S o l d e ri n g a re a (1 4 0 m i l x 110mil) for bottom p a d electrolytic capacitor (>33µF) is recommended. It is not necessary to use low-ESR capacitors. More capacitance reduces the variations of the input voltage 2 3 CCNTL 4 C IN Figure 3 Recommended SOP-8P Layout at VIN pin. Layout and Thermal Consideration The APL1581 series have internal power and thermal limiting (TJ=150oC typical) circuitry designed to protect the device under overload conditions. However, maximum junction temperature ratings should not be Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 10 www.anpec.com.tw APL1581 Package Information TO-220-5 D R Q b e e1 E L H1 A c F Dim A b c D e e1 E F H1 J1 L R Q Millimeters Min. 3.55 0.63 0.35 14.22 1.57 6.68 9.65 1.14 5.84 2.03 13.72 3.53 2.54 Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 J1 Inches Max. 4.83 1.02 0.56 16.51 1.83 6.94 10.67 1.40 6.60 3.05 14.22 4.09 3.43 11 Min. 0.140 0.025 0.014 0.560 0.062 0.263 0.380 0.045 0.230 0.080 0.540 0.139 0.100 Max. 0.190 0.040 0.022 0.650 0.072 0.273 0.420 0.055 0.260 0.120 0.560 0.161 0.135 www.anpec.com.tw APL1581 Package Information TO-263-5 A c2 E1 H D D1 L1 E b e c SEE VIEW A 0 SEATING PLANE 0.25 L VIEW A A1 GAUGE PLANE TO-263-5 S Y M B O L MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 A1 0.00 0.25 0.000 0.010 b 0.51 0.99 0.020 0.039 c 0.38 0.74 0.015 0.029 c2 1.14 1.65 0.045 0.065 D 8.38 9.65 0.330 0.380 D1 6.00 9.00 0.236 0.354 E 9.65 11.43 0.380 0.450 E1 6.22 9.00 0.245 0.354 H 14.61 15.88 0.575 0.625 L 1.78 2.79 0.070 0.110 MILLIMETERS e 1.70 BSC 0.067 BSC 0.066 1.68 L1 0 INCHES 0o 8o o 0 8o Note : Follow from JEDEC TO-263 BB. Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 12 www.anpec.com.tw APL1581 Packaging Information TO-252-5 E A c2 E1 H D D1 L3 b3 c b e SEE VIEW A 0 SEATING PLANE L A1 0.25 GAUGE PLANE VIEW A TO-252-5 S Y M B O L MIN. MAX. MIN. MAX. A 2.18 2.39 0.086 0.094 INCHES MILLIMETERS 0.005 0.13 A1 b 0.50 0.89 0.020 0.035 b3 4.32 5.46 0.170 0.215 c 0.46 0.61 0.018 0.024 c2 0.46 0.89 0.018 0.035 D 5.33 6.22 0.210 0.245 D1 4.57 6.00 0.180 0.236 E 6.35 6.73 0.250 0.265 E1 3.81 6.00 0.150 e 1.27 BSC 0.236 0.050 BSC H 9.40 10.41 0.370 0.410 L 1.40 1.78 0.055 0.070 L3 0.89 2.03 0.035 0.080 0 0° 8° Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 0° 13 8° www.anpec.com.tw APL1581 Packaging Information SOP-8-P D SEE VIEW A E E1 THERMAL PAD E2 D1 h X 45 ° c A 0.25 b L 0 GAUGE PLANE SEATING PLANE A1 A2 e VIEW A S Y M B O L SOP-8P MILLIMETERS MIN. INCHES MAX. A MAX. MIN. 0.063 1.60 0.006 0.000 0.15 A1 0.00 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 D1 2.25 3.50 0.098 0.138 0.049 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 0.118 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0o 8o 0o 8o Note : 1. Follow JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 14 www.anpec.com.tw APL1581 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 381.0±2.00 60 MIN. TO-263-5 Application P0 P1 4.0±0.10 16.0±0.10 A H 330.0±2.00 50 MIN. TO-252-5 Application P0 P1 4.0±0.10 8.0±0.10 A H 330.0±2.00 50 MIN. SOP-8-P P0 P1 4.0±0.10 8.0±0.10 T1 C d 24.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P2 D0 D1 1.5+0.10 2.0±0.10 -0.00 1.5 MIN. T1 C d 16.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P2 D0 D1 1.5+0.10 2.0±0.05 1.5 MIN. -0.00 T1 C d 12.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P2 D0 D1 1.5+0.10 2.0±0.05 -0.00 1.5 MIN. D 20.2 MIN. W E1 F 24.0±0.30 1.75±0.10 11.5±0.10 T 0.6+0.00 -0.40 D A0 10.8±0.20 16.1±0.20 5.2±0.20 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.05 W E1 T 0.6+0.00 -0.40 D 6.80±0.20 20.2 MIN. 12.0±0.30 1.75±0.10 T 0.6+0.00 -0.40 A0 B0 W A0 K0 F B0 K0 10.40± 2.50±0.20 0.20 E1 F B0 5.5±0.05 K0 6.40±0.20 5.20±0.20 2.10±0.20 (mm) Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 15 www.anpec.com.tw APL1581 Devices Per Unit Package Type Unit Quantity TO-252-5 Tape & Reel 2500 TO-263-5 Tape & Reel 1000 SOP-8-P Tape & Reel 2500 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 16 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA www.anpec.com.tw APL1581 Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Note: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness Volume mm <350 Volume mm ≥350 <2.5 mm ≥2.5 mm 240 +0/-5°C 225 +0/-5°C 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 Package Thickness 3 Volume mm <350 Volume mm 350-2000 3 Volume mm >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 17 www.anpec.com.tw