APL5336 Source and Sink, 1.5A, Fast Transient Response Linear Regulator Features General Description • Provide Bi-direction Output Currents -Sourcing and Sinking Current up to 1.5A The APL5336 linear regulator is designed to provide a regulated voltage with bi-direction output current for DDR- • Built-in Soft-Start • • • Power-On-Reset Monitoring on VCNTL and VIN pins Fast Transient Response Stable with Ceramic Output Capacitors SDRAM termination voltage. The APL5336 integrates two power transistors to source or sink load current up to • ±20mV High System Output Accuracy over Load 1.5A. It also features internal soft-start, current-limit, thermal shutdown and enable control functions into a single chip. The internal soft-start controls the rising rate of the output voltage to prevent inrush current during start-up. The current-limit circuit detects the output current and limits and Temperature Ranges • Adjustable Output Voltage by External Resistors • Current-Limit Protection • On-Chip Thermal Shutdown • Shutdown for Standby or Suspend Mode • Simple SOP-8 and SOP-8 with Exposed Pad the current during short-circuit or current overload conditions. The on-chip thermal shutdown provides thermal protection against any combination of overload that would create excessive junction temperatures. The output voltage of APL5336 is regulated to track the voltage on VREF pin. An proper resistor divider connected (SOP-8P) Packages • to VIN, GND, and VREF pins is used to provide a half voltage of VIN to VREF pin. In addition, connect an exter- Lead Free and Green Devices Available nal ceramic capacitor and a open-drain transistor to VREF pin for external soft-start and shutdown control. (RoHS Compliant) Applications Pulling and holding the voltage on VREF below the enable voltage threshold shuts down the output. The output • DDRII/III SDRAM Termination Voltage • Motherboard and VGA Card Power Supplies • Setop Box • SSTL-2/3 Termination Voltage of APL5336 will be high impedance after being shut down by VREF or the thermal shutdown function. Pin Configuration Simplified Application Circuit VCNTL +5V VIN +1.8V/+1.5V 1 3 VIN VCNTL APL5336 VREF VOUT GND 2 VIN 1 8 VCNTL GND 2 7 VCNTL VREF 3 6 VCNTL VOUT 4 5 VCNTL 6 4 Top View of SOP-8 VOUT 0.9V / 0.75V Shutdown Enable VIN 1 8 NC GND 2 7 NC VREF 3 6 VCNTL VOUT 4 5 NC Top View of SOP-8P Exposed Pad (connected to GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 1 www.anpec.com.tw APL5336 Ordering and Marking Information Package Code K : SOP-8 KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 ° C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APL5336 Assembly Material Handling Code Temperature Range Package Code APL5336 K: APL5336 XXXXX APL5336 KA: APL5336 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol (Note 1) Rating Unit VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 7 V VIN Supply Voltage (VIN to GND) -0.3 ~ 7 V VREF VREF Input Voltage (VREF to GND) -0.3 ~ 7 V VOUT VOUT Output Voltage (VOUT to GND) -0.3 ~ VIN+0.3V V VCNTL VIN Parameter PD Power Dissipation TJ Junction Temperature TSTG TSDR Internally Limited Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds W 150 o -65 ~ 150 o 260 o C C C Note 1: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Thermal Characteristics Symbol Parameter Rating Unit SOP-8 80 °C/W SOP-8P 55 Junction-to-Ambient Thermal Resistance in Free Air (Note 2) θJA θJC Junction-to-Case Thermal Resistance in Free Air (Note 3) SOP-8P o C/W 20 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3: The exposed pad of SOP-8P is soldered directly on the PCB. The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package. Recommended Operating Conditions Symbol VCNTL Parameter Range Unit VCNTL Supply Voltage 3.0 ~ 5.5 V VIN VIN Supply Voltage 1.2 ~ 5.5 V VREF VREF Input Voltage 0.7 ~ VCNTL – 2.2 V VOUT VOUT Output Voltage VREF ± 0.02 V Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 2 www.anpec.com.tw APL5336 Recommended Operating Conditions (Cont.) Symbol Parameter Range Unit -1.5 ~ +1.5 A IOUT VOUT Output Current (Note 4) CIN Capacitance of Input Capacitor 10 ~ 100 µF Equivalent Series Resistor (ESR) of Input Capacitor 0 ~ 200 mΩ COUT TA TJ 8 ~ 47 µF Total Output Capacitance (Note 5) 10 ~ 330 µF Ambient Temperature -40 ~ 85 o -40 ~ 125 o Capacitance of Output Multi-layer Ceramic Capacitor (MLCC) Junction Temperature C C Note 4: The symbol “+” means the VOUT sources current to load; the symbol “-” means the VOUT sinks current from load to GND. Note 5: It’s necessary to use a multi-layer ceramic capacitor 8µF at least as an output capacitor. Please place the ceramic capacitor near VOUT pin as close as possible. Besides, the other kinds of capacitors (like Electrolytic, PoSCap, tantalum capacitors) can be used as the output capacitors in parallel. Electrical Characteristics Refer to the typical application circuit. These specifications apply over VCNTL=5V, VIN=1.8V or 1.5V, VREF=0.5VIN, CIN=10µF, COUT=10µF (MLCC) and TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter Test Conditions APL5336 Unit Min Typ Max IOUT= 0A - 1 2 mA VREF=0V (Shutdown) - - 5 µA VREF = GND (Shutdown) - - 5 µA VCNTL Rising 2.5 2.75 2.9 V - 0.35 - V VIN Rising 0.7 0.9 1.05 - 0.3 - V SUPPLY CURRENT ICNTL VCNTL Supply Current IVIN VIN Supply Current at Shutdown POWER-ON-RESET (POR) Rising VCNTL POR Threshold VCNTL POR Hysteresis Rising VIN POR Threshold VIN POR Hysteresis OUTPUT VOLTAGE VOUT VOS VOUT Output Voltage IOUT=0A, VREF=0.7V ~ 2.8V - VREF - V System Accuracy Over temperature and load current ranges -20 - 20 mV IOUT=+10mA -7 -1 - IOUT=-10mA - +8 +12 IOUT=+10mA ~ +1.5A -13 -8 - IOUT=-10mA ~ -1.5A - +4 +8 VOUT Offset Voltage (VOUT -VREF) Load Regulation Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 3 mV mV www.anpec.com.tw APL5336 Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over VCNTL=5V, VIN=1.8V or 1.5V, VREF=0.5VIN, CIN=10µF, COUT=10µF (MLCC) and TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter APL5336 Test Conditions Min Typ Max 2 3 Unit PROTECTIONS ILIM Sourcing Current (VIN=1.8V) TJ=25oC 1.8 o TJ=125 C 1.6 - - Sinking Current (VIN=1.8V) TJ=25oC -2 -2.2 -3 TJ=125oC -1.6 - - Sourcing Current (VIN=1.5V) TJ=25oC 1.6 1.8 2.6 TJ=125oC 1.1 - - TJ=25 C -1.6 -1.8 -2.6 TJ=125oC -1.1 - - - 150 - - 40 - Current-Limit Sinking Current (VIN=1.5V) TSD Thermal Shutdown Temperature TJ rising Thermal Shutdown Hysteresis o A A o C ENABLE and SOFT-START VREF Enable Voltage Threshold 0.15 0.3 0.4 V IVREF VREF Bias Current -100 - +100 nA TSS Soft-Start Interval 0.1 0.2 0.4 ms Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 4 www.anpec.com.tw APL5336 Typical Operating Characteristics Sourcing Current-Limit vs. Junction Temperature VOUT Offset Voltage vs. Junction Temperature 3.5 8 3 Current-Limit,ILIM (A) VOUT Offset Voltage,VOS (mV) 10 6 IOUT= -10mA 4 IOUT= 10mA 2 0 -2 2.5 2 VIN=2.5V 1.5 VIN=1.8V VIN=1.5V 1 Sourcing Current VREF=0.5xVIN VCNTL=5V 0.5 VIN=1.5V 0 -4 -50 -25 0 25 50 75 100 125 -50 150 -25 Junction Temperature (TJ ,oC) Sinking Current-Limit vs. Junction Temperature 3.5 -10 3 -20 2.5 VIN=2.5V VIN=1.8V VIN=1.5V 1.5 1 Sinking Current VREF=0.5xVIN VCNTL=5V 0.5 0 -50 -25 0 50 75 100 125 -50 -60 VIN=1.5V,IOUT=1.5A VIN=1.5V,IOUT=0.5A -80 1000 125 10000 100000 1000000 Frequency (HZ) Sinking Current-Limit vs. Junction Temperature 3 2.5 2.5 VIN=1.8V 2 Current-Limit,ILIM (A) Current-Limit,ILIM (A) 100 VIN=2.5V,IOUT=1.5A VIN=2.5V,IOUT=0.5A -40 Sourcing Current-Limit vs. Junction Temperature 1.5 VIN=1.5V 1 0 75 -30 Junction Temperature (TJ ,oC) 0.5 50 VCNTL=5V, COUT=10µF(MLCC) VREF=0.5xVIN -70 25 25 VCNTL Power Supply Rejection Ratio (PSRR) 0 VCNTL PSRR (dB) Current-Limit,ILIM (A) 4 2 0 Junction Temperature (TJ ,oC) Sourcing Current VREF=0.5xVIN VCNTL=3.3V -50 -25 0 2 1.5 VIN=1.8V VIN=1.5V 1 0.5 Sinking Current VREF=0.5xVIN VCNTL=3.3V 0 25 50 75 100 -50 125 Junction Temperature (oC) Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 -25 0 25 50 75 100 125 Junction Temperature (oC) 5 www.anpec.com.tw APL5336 Operating Waveforms VCNTL = 5V, V IN = 1.8V or 1.5V, VREF=0.5xVIN, CIN=COUT=10µF(MLCC) Load Transient Response (VIN=1.8V) Load Transient Response (VIN=1.8V) IOUT=10mA to 1.5A IOUT=10mA to 1.5A to 10mA VOUT 1 VOUT 1 IOUT IOUT 2 2 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 200µs/Div Load Transient Response (VIN=1.8V) Load Transient Response (VIN=1.8V) IOUT=1.5A to 10mA IOUT=-10mA to -1.5A to -10mA VOUT VOUT 1 1 IOUT 2 IOUT 2 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 200µs/Div 6 www.anpec.com.tw APL5336 Operating Waveforms (Cont.) VCNTL = 5V, V IN = 1.8V or 1.5V, VREF=0.5xVIN, CIN=COUT=10µF(MLCC) Load Transient Response (VIN=1.8V) Load Transient Response (VIN=1.8V) IOUT=-10mA to -1.5A IOUT=-1.5A to -10mA VOUT VOUT 1 1 IOUT IOUT 2 2 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div Load Transient Response (VIN=1.5V) Load Transient Response (VIN=1.5V) IOUT=10mA to 1A IOUT=10mA to 1A to 10mA VOUT 1 VOUT 1 IOUT IOUT 2 2 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 200µs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div 7 www.anpec.com.tw APL5336 Operating Waveforms (Cont.) VCNTL = 5V, V IN = 1.8V or 1.5V, VREF=0.5xVIN, CIN=COUT=10µF(MLCC) Load Transient Response (VIN=1.5V) Load Transient Response (VIN=1.5V) IOUT=1A to 10mA IOUT=-10mA to -1A to -10mA VOUT VOUT 1 1 2 IOUT IOUT 2 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 200µs/Div CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div Load Transient Response (VIN=1.5V) Load Transient Response (VIN=1.5V) IOUT=-10mA to -1A IOUT=-1A to -10mA VOUT VOUT 1 1 2 2 IOUT IOUT CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 CH1: VOUT, 20mV/Div, AC CH2: IOUT, 0.5A/Div, DC TIME: 1µs/Div 8 www.anpec.com.tw APL5336 Operating Waveforms (Cont.) VCNTL = 5V, V IN = 1.8V or 1.5V, VREF=0.5xVIN, CIN=COUT=10µF(MLCC) Power ON Test (VIN=1.8V) RLoad=1 Ω Power OFF Test (VIN=1.8V) RLoad=1 Ω VIN VIN 1 1 VOUT VOUT IOUT IOUT 2 2 3 3 CH1: VIN, 1V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: IOUT, 1A/Div, DC CH1: VIN, 1V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: IOUT, 1A/Div, DC TIME: 50ms/Div TIME: 5ms/Div Power OFF Test (VIN=1.5V) Power ON Test (VIN=1.5V) RLoad=1 Ω RLoad=1 Ω VIN VIN 1 1 VOUT VOUT IOUT 2 2 IOUT 3 3 CH1: VIN, 1V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: IOUT, 1A/Div, DC CH1: VIN, 1V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: IOUT, 1A/Div, DC TIME: 50ms/Div TIME: 5ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 9 www.anpec.com.tw APL5336 Pin Description PIN NO. PIN NAME FUNCTION 1 VIN Main Power Input Pin. Connect this pin to a voltage source and an input capacitor. The APL5336 sources current to VOUT pin by controlling the upper pass MOSFET, providing a current path from VIN to VOUT. 2 GND Power and Signal Ground. Connect this pin to system ground plane with shortest traces. The APL5336 sinks current from VOUT pin by controlling the lower pass MOSFET, providing a current path from VOUT to GND. This pin is also the ground path for internal control circuitry. 3 VREF Reference Voltage Input and Active-high Enable Control Pin. Apply a voltage to this pin as a reference voltage for the APL5336. Connect this pin to a resistor diver, between VIN and GND, and a capacitor for filtering noise purpose. Applying and holding the voltage below the enable voltage threshold on this pin by an open-drain transistor shuts down the output. During shutdown, the VOUT pin has high input impedance. 4 VOUT Output Pin of The Regulator. Connect this pin to load and output capacitors (>8µF MLCC is necessary) required for stability and improving transient response. The output voltage is regulated to track the reference voltage and capable of sourcing or sinking current up to 1.5A. 5, 7, 8 (SOP-8P) NC 5 ~ 8 (SOP-8) 6 (SOP-8P) VCNTL Power Input Pin for Internal Control Circuitry. Connect this pin to a voltage source, providing a bias for the internal control circuitry. A decoupling capacitor is connected near this pin. Exposed Pad (SOP-8P only) GND Chip Substrate Connection of The Chip. Connect this pad to system ground plane for good thermal conductivity. No Internal Connection. Block Diagram VIN VCNTL Power-OnReset VREF Enable EN POR VREF Thermal Shutdown THSD Error Amplifier and Soft-Start VOUT CurrentLimit GND Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 10 www.anpec.com.tw APL5336 Typical Application Circuit VCNTL +5V VIN +1.8V/+1.5V 1 C2 47µF R1 100kΩ 3 VIN VCNTL APL5336 VREF GND Q1 Enable R2 100kΩ 4 VOUT 0.9V/0.75V 2 VREF Shutdown VOUT C1 1µF 6 C5 10µF C4 1µF C3 100µF (optional) The ceramic capacitor C5 ( at least 8µF) is necessary for output stability. Function Description Power-On-Reset low 0.3V (typical) shuts down the output of the regulator. In the typical application, an NPN transistor or N-channel A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to prevent wrong logic MOSFET is used to pull down the VREF while applying a “high” signal to turn on the transistor. When shutdown controls. The POR function initiates a soft-start process after both of the supply voltages exceed their rising POR function is active, both of the internal power MOSFETs are turned off and the impedance of the VOUT pin is larger voltage thresholds during powering on. than 10MΩ. Output Voltage Regulation Internal and External Soft-Start The output voltage on VOUT pin is regulated to track the reference voltage applied on VREF pin. Two internal N- The APL5336 is designed with an internal soft-start function to control the rise rate of the output voltage to prevent channel power MOSFETs controlled by high bandwidth error amplifiers regulate the output voltage by sourcing inrush current during start-up. When release the pull-low transistor connected with VREF current from VIN pin or sinking current to GND pin. An internal output voltage sense pad is bonded to the VOUT pin, the current via the resistor divider charges the external soft-start capacitor (C4) and the VREF starts to rise up. pin with a bonding wire for perfect load regulation. For preventing the two power MOSFETs from shoot- The IC starts a soft-start process when the VREF reaches the enable voltage threshold. The output voltage is regu- through, a small voltage offset between the positive inputs of the two error amplifiers is designed. It results in lated to follow the lower voltage, which is either the internal soft-start voltage ramp or the VREF voltage, to rise up. higher output voltage while the regulator sinks light or heavy load current. The external soft-start interval is programmable by the resistor-divider and the soft-start capacitor (C4). The APL5336 provides very fast load transient response at small output capacitance to save total cost. Thermal Shutdown Current-Limit The thermal shutdown circuit limits the junction temperature of the APL5336. When the junction temperature ex- The APL5336 monitors the output current, both sourcing and sinking current, and limits the maximum output cur- ceeds 150 C, a thermal sensor turns off the both pass transistors, allowing the device to cool down. The ther- rent to prevent damages during current overload or shortcircuit (shorted from VOUT to GND or VIN) conditions. mal sensor allows the regulator to regulate again after o the junction temperature cools by 40 C, resulting in a Enable The VREF pin is a multi-function input pin which is the pulsed output during continuous thermal overload o conditions. The thermal limit is designed with a 40 C reference voltage input pin and the enable control input pin. Applying and holding the voltage (VREF) on VREF be- hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the o APL5336. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 11 www.anpec.com.tw APL5336 Application Information Table 1 provides the suitable output capacitors for APL5336 Power Sequencing The input sequence of powers applied for VIN and VCNTL Vendor Murata is not necessary to be concerned. Description 10µF, 6.3V, X7R, 0805, GRM21BR70J106K 10µF, 6.3V, X5R, 0805, GRM21BR60J106K Reference Voltage Murata website: www.murata.com A reference voltage is applied at the VREF pin by a resistor divider between VIN and GND pins. An external by- Table 1: Output Capacitor Guide pass capacitor is also connected to VREF. The capacitor and the resistor divider form a low-pass filter to reduce Operation Region and Power Dissipation The APL5336 maximum power dissipation depends on the thermal resistance and temperature difference be- the inherent reference noise from VIN. The capacitor is a 0.1µF or greater ceramic capacitor and connected as close tween the die junction and ambient air. The power dissipation PD across the device is: to VREF as possible. More capacitance and large resistor divider will increase the soft-start interval. Do not place PD ≤ any additional loading on this reference input pin. Input Capacitor (TJ − TA ) θJA Where (TJ-TA) is the temperature difference between the junction and ambient air. θJA is the thermal resistance The APL5336 requires proper input capacitors to supply current surge during stepping load transients to prevent o between junction and ambient air. Assuming the TA=25 C o and maximum TJ=150 C (typical thermal limit threshold), the input rail from dropping. Because the parasitic inductors from the voltage sources or other bulk capacitors to the maximum power dissipation is calculated as: the VIN pin limit the slew rate of the input current, more (150 − 25) 80 = 1.56( W ) PD(max) = parasitic inductance needs more input capacitance. For the APL5336, the total capacitance of input capacitors value including MLCC and aluminum electrolytic capaci- For normal operation, do not exceed the maximum junc- tors should be larger than 10µF. For VCNTL pin, a capacitor of 0.47µF (MLCC) or above is o tion temperature of TJ = 125 C. The calculated power dissipation should less than: recommended for noise decoupling. (125 − 25) 80 = 1.25( W ) PD = Output Capacitor The APL5336 needs a proper output capacitor to maintain circuit stability and improve transient response. In order to insure the circuit stability, a 10µF X5R or X7R PCB Layout Consideration MLCC output capacitor is sufficient at all operating temperatures and it must be placed near the VOUT. The maxi- Figure 1 illustrates the layout. Below is a checklist for your layout: mum distance from output capacitor to VOUT must within 10mm. Total output capacitors value including MLCC and 1. Please place the input capacitors close to the VIN. 2. Please place the output capacitors close to the VOUT, aluminum electrolytic capacitors should be larger than 10µF. a MLCC capacitor larger than 8µF must be placed near the VOUT. The distance from VOUT to output MLCC must be less than 10mm. 3. To place APL5336 and output capacitors near the load is good for load transient response. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 12 www.anpec.com.tw APL5336 Application Information (Cont.) Recommended Minimum Footprint 4. Large current paths, the bold lines in Figure 1, must 0.024 8 7 6 5 8 0.072 have wide tracks. 5. For SOP-8P package, please solder the thermal pad 0.024 7 to the APL5336 to top-layer ground plane. Numerous vias 0.254mm in diameter should be used to connect 5 0.138 0.118 0.212 0.212 both top-layer and internal ground planes. The ground planes and PCB form a heat sink to channel major 6 0.072 PCB Layout Consideration (Cont.) power dissipation of the APL5336 into ambient air. Large ground plane is good for heatsinking. Optimum performance can only be achieved when the device is mounted on a PC board according to the board layout 1 2 0.050 diagrams which are shown as Figure 2. 3 4 Unit : Inch SOP-8 1 2 0.050 3 4 Unit : Inch SOP-8P APL5336 VIN C2 VCNTL VREF VOUT GND C5 C3 (optional) Figure 1 For dissipating heat VCNTL C2 + Ground C3 + C5 VIN <10mm VOUT SOP-8 VCNTL For dissipating heat Ground C2 + C3 + C5 VIN <10mm VOUT Ground SOP-8P Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 13 www.anpec.com.tw APL5336 Package Information SOP-8 D E E1 SEE VIEW A h X 45 ° c A 0.25 b GAUGE PLANE SEATING PLANE A1 A2 e L VIEW A S Y M B O L SOP-8 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.004 0.25 0.010 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° 8° Note: 1. Follow JEDEC MS-012 AA. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 14 www.anpec.com.tw APL5336 Package Information SOP-8P D SEE VIEW A E E1 THERMAL PAD E2 D1 h X 45 ° c A 0.25 b L 0 GAUGE PLANE SEATING PLANE A1 A2 e VIEW A S Y M B O L SOP-8P MILLIMETERS MIN. INCHES MAX. A MAX. MIN. 0.063 1.60 A1 0.00 A2 1.25 b 0.31 0.006 0.000 0.15 0.049 0.51 0.012 0.020 0.010 c 0.17 0.25 0.007 D 4.80 5.00 0.189 0.197 D1 2.25 3.50 0.098 0.138 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 0.118 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° e 1.27 BSC 0.050 BSC 8° Note : 1. Follow JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 15 www.anpec.com.tw APL5336 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 330.0±2.00 50 MIN. SOP-8(P) P0 4.0±0.10 T1 P1 8.0±0.10 C d D 12.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P2 D0 2.0±0.05 1.5+0.10 -0.00 D1 E1 20.2 MIN. 12.0±0.30 1.75±0.10 T 1.5 MIN. W A0 B0 F 5.5±0.05 K0 0.6+0.00 6.40±0.20 5.20±0.20 2.10±0.20 -0.40 (mm) Devices Per Unit Package Type SOP-8(P) Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 Quantity 2500 16 www.anpec.com.tw APL5336 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Time 25°C to Peak Temperature Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 17 www.anpec.com.tw APL5336 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness Volume mm <350 Volume mm ≥350 <2.5 mm ≥2.5 mm 240 +0/-5°C 225 +0/-5°C 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 Package Thickness 3 Volume mm <350 Volume mm 350-2000 3 Volume mm >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2008 18 www.anpec.com.tw