AS17xx Semicustom Bipolar Array Features Description Size (single tile) • 87 x 75 mils Expandability of array (to 2 or 4 tiles) The AS17xx is Astec’s proprietary semicustom bipolar array. This semicustom IC is a collection of individual transistors and resistors in a fixed configuration. The custom circuit is manufactured by creating a single metal mask to connect the components. This allows the designer to deal with only one mask for the IC layout instead of the actual 10 mask process. The semicustom array is useful for a wide range of functions, both analog and digital. In its simplest configuration, the AS17xx has 76 active devices available, but can be expanded to give up to four times this number in its largest configuration. This expandability of the array is a unique feature, allowing a whole range of semicustom circuits to be manufactured. Component Availability (single tile) • Small NPN • • • • Dual collector PNP • Pinch Resistors (3-terminal, 30kΩ) • • 48 21 Vertical PNP 4 Power NPN 3 Diffused Resistors (total) Cross-unders Buses Basic Electrical Specs • Transistor Matching (NPN & PNP) ≈300 kΩ 8 13 6 <2% • Primary voltage limitations: LVCEO 18 V BVCBO 30 V • Diffusion to substrate (Ground) • • 30 V NPN Parameters Beta fT (1mA) BVEBO 80–500 300 MHz 7V PNP Parameters: Beta fT (1mA) BVEBO 20–300 300 MHz 30 V © ASTEC Semiconductor Because Astec has ongoing manufacturing of high volume circuits on this array, incremental wafer costs for engineering purposes are low. Therefore quality and reliability can be maintained even with small volume or engineering lots. Since the silicon can be completely processed and held awaiting only the metal etch and passivation steps, extremely fast turn-around times can be achieved. The AS17xx bipolar array uses a standard “20 Volt” bipolar technology. Although quite similar to industry standard arrays, it has a number of important improvements. First, the ratio of PNPs to NPNs has been increased to allow for more modern design practice. Second, the process has been modified to allow for a deep collector diffusion (sinker) which not only improves the VCE(SAT) of the transistors, but also allows for the elimination of regions with thin oxide which historically plague semicustom die with electrostatic discharge reliability concerns. Third, a set of low resistance sinker resistors allows for bussing supply or signal lines without using active components for cross-unders. In addition, the specific component geometries have been further optimized to facilitate the layout compared to the industry standard arrays. Resistors are now in a binary weighted 500 / 1k / 2k / 4k sequence for more simple value calculations. The power devices use multiple standard size emitters 119 Semicustom Bipolar Array AS17xx so that they may also be used to create a device with an integral emitter area ratio with respect to a standard small NPN. The AS17xx bipolar array can be packaged in industry standard DIP or surface mount packages with 8 to 40 leads. The number of pads Pin Configuration — available on the AS17xx varies with the number of tiles used as follows: single tile per die = 18 pads, two tiles per die = 30 pads, and four tiles per die = 40 pads. The extra pads not used for bonding to leads can be used for wafer level testing, trimming, and debugging. Top view PDIP (N) AS1700-NPN Kit Part PDIP (N) AS1700-PNP Kit Part SUB 1 14 Vbe C 2 13 C B 3 12 B E 4 11 E C 5 10 C B 6 9 B E 7 8 E Die Configuration — PDIP (N) AS1700-PWR Kit Part SUB 1 14 C SUB 1 14 E C 2 13 C C 2 13 C B 3 12 B B 3 12 B E 4 11 E E 4 11 E C 5 10 C C 5 10 B B 6 9 B B 6 9 B E 7 8 E E 7 8 E Top view Figure 1. Single Tile Bipolar Array ASTEC Semiconductor 120 Semicustom Bipolar Array AS17xx Absolute Maximum Ratings Parameter Symbol Continuous Power Dissipated at 25° C Single Transistor Total Package Junction Temperature Storage Temperature Lead Temperature, Soldering 10 Seconds PD TJ TSTG TL Rating Unit 300 1400 150 –65 to 150 300 mW mW °C °C °C Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics All parameters measured at 25° C. Parameter Symbol Test Condition Min Typ Max Unit Collector-to-Emitter Breakdown Voltage LVCEO IC = 1 mA 20 35 V Collector-to-Base Breakdown Voltage BVCBO IC = 100 µA 50 60 V Emitter-to-Base Breakdown Voltage BVEBO IE = 10 µA 5 8 V Collector Cutoff Current ICEO VCE = 18 V 0 2 100 nA Collector-to-Emitter Saturation Voltage VCE SAT IB = 10 µA, IC = 100 µA 0 95 200 mV Base-to-Emitter Voltage VBE VCE = 3 V, IC = 100 µA 650 680 700 mV Static Forward Current-Transfer Ratio β (hFE) VCE = 3 V, IC = 100 µA 80 125 500 Early Voltage VA AS1700-NPN: Minimum NPN Transistor Matching (measuring ∆ IC) –150 IC = 200 µA –10 <1 V 10 % AS1700-PWR: Large NPN (20-emitter) Collector-to-Emitter Breakdown Voltage LVCEO IC = 1 mA 20 35 V Collector-to-Base Breakdown Voltage BVCBO IC = 100 µA 50 58 V Emitter-to-Base Breakdown Voltage BVEBO IE = 10 µA 5 7.6 V Collector Cutoff Current ICEO VCE = 18 V 0 2 100 nA Collector-to-Emitter Saturation Voltage VCE SAT IB = 200 µA, IC = 2 mA 0 20 200 mV Base-to-Emitter Voltage VBE VCE = 3 V, IC = 200 µA 650 680 700 mV Static Forward Current-Transfer Ratio β (hFE) VCE = 3 V, IC = 2 mA 80 125 500 Early Voltage VA ASTEC Semiconductor –150 121 V Semicustom Bipolar Array AS17xx Electrical Characteristics (cont’d) All parameters measured at 25° C. Parameter Symbol Test Condition Min Typ Max Unit Collector-to-Emitter Breakdown Voltage LVCEO IE = 100 µA 30 50 V Field-Effect Threshold Voltage VTF IE = 10 µA 36 V P + to Substrate Leakage ISUB IE = 100 µA, VB = 1 V 0 150 500 nA Collector Cutoff Current ICEO VCE = 18 V 0 2 100 nA Collector-to-Emitter Saturation Voltage VCE SAT IB = 10 µA, IE = 100 µA 0 150 200 mV Base-to-Emitter Voltage VEB VEC = 3 V, IE = 100 µA 630 690 700 mV Static Forward Current-Transfer Ratio β (hFE) VEC = 3 V, IE = 100 µA 20 60 300 Early Voltage VA AS1700-PNP: Lateral PNP –105 V Transistor Matching (measuring ∆ IE) IE = 200 µA –10 <1 10 % Double Collector Matching (meas. ∆ IE) IE = 200 µA –10 <1 10 % AS1700-PWR: Vertical PNP Collector-to-Emitter Breakdown Voltage LVCEO IE = 100 µA 30 50 Collector Cutoff Current ICEO VCE = 18 V 0 2 100 nA Collector-to-Emitter Saturation Voltage VCE SAT IB = 10 µA, IE = 100 µA 0 150 200 mV mV V Base-to-Emitter Voltage VEB VEC = 3 V, IE = 100 µA 650 680 700 Static Forward Current-Transfer Ratio β (hFE) VEC = 3 V, IE = 100 µA 20 125 500 ASTEC Semiconductor 122 Semicustom Bipolar Array AS17xx Typical Performance Curves Minimum NPN BETA vs IC Over Temperature (– 55° C to 125° C) VEBO Breakdown Voltage vs Temperature 300 VCE = 3 V 280 260 NPN (small) 240 IC = 10 µA 9 T = 125° C NPN (small) T = 100° C 220 T = 70° C T = 50° C VEBO (V) BETA 200 180 160 140 120 8 100 T = 25° C 80 60 T = 0° C 40 T = –25° C 7 20 T = –55° C 0 10 µA 100 µA 1 mA Current IC – 60 – 40 –20 10 mA 0 20 40 60 80 Temperature (° C) Figure 19 Figure 20 VCE SAT vs IC Over Temperature (– 55° C to 125° C) VBE SAT vs IC Over Temperature (– 55° C to 125° C) 500 1400 1300 Forced Beta: β = 10 450 1200 400 1100 T = 125° C 350 T = 70° C 300 T = 25° C 250 Forced Beta: β = 10 T = – 55° C 1000 V BE SAT (mV) VCE SAT (mV) 100 120 140 T = 0° C 200 T = – 55° C 150 900 800 700 600 T = 0° C 500 T = 25° C 400 300 100 T = 70° C 200 50 0 0 2 4 6 8 10 12 14 Current IC (mA) 16 18 0 10 µA 20 Figure 21 ASTEC Semiconductor T = 125° C 100 NPN (small) NPN (small) 100 µA 1 mA Current IC Figure 22 123 10 mA Semicustom Bipolar Array AS17xx Typical Performance Curves VBE vs IC Over Temperature (– 55° C to 125° C) VBE vs Temperature with Different IC 1000 1200 900 VCE = 3 V 1100 T = – 55° C 1000 T = 0° C 700 T = 25° C 900 T = 70° C 800 VBE (mV) VBE (mV) IC = 10 mA 800 700 600 600 500 IC = 5 mA IC = 1 mA IC = 100 µA 400 IC = 10 µA 300 T = 125° C 500 IC = 1 µA 200 400 100 VCE = 3 V 0 – 60 – 40 – 20 0 NPN (small) 300 1 µA 10 µA 100 µA Current IC 1 mA 10 mA Figure 23 NPN (small) 20 40 60 80 Temperature (° C) 100 120 140 Figure 24 BETA vs IC Over Temperature (– 55° C to 125° C) VEBO Breakdown Voltage vs Temperature 320 VCE = 3 V 9 IC = 10 µA NPN (large) 260 240 220 BETA NPN (large) T = 125° C T = 70° C T = 25° C 200 180 160 VEBO (V) 300 280 T = 0° C 140 8 120 100 T = – 55° C 80 60 40 20 0 10 µA 7 100 µA 1 mA 10 mA Current IC 100 mA – 60 – 40 – 20 Figure 25 0 20 40 60 80 Temperature (° C) Figure 26 ASTEC Semiconductor 124 100 120 140 Semicustom Bipolar Array AS17xx Typical Performance Curves VCE SAT vs IC Over Temperature (– 55° C to 125° C) VBE SAT vs IC Over Temperature (– 55° C to 125° C) 500 1100 450 1000 Forced Beta: β = 10 400 T = –55° C 900 T = 125° C VBE SAT (mV) VCE SAT (mV) 350 300 T = 25° C 250 T = 0° C 200 T = –55° C T = 0° C 800 700 600 T = 125° C 150 500 100 T = 25° C 400 50 T = 70° C NPN (large) NPN (large) 0 0 10 20 30 40 50 60 70 Current IC (mA) 80 90 300 10 µA 100 100 µA 1 mA Current IC Figure 27 VBE vs Temperature with Different IC 1100 1100 1000 VCE = 3 V 900 900 VBE (mV) T = – 55° C VBE (mV) IC = 100 mA 800 800 700 T = 0° C 600 T = 25° C 500 700 600 500 400 T = 70° C 400 300 IC = 50 mA IC = 10 mA IC = 1 mA IC = 100 µA T = 125° C 300 200 10 µA 1 mA 100 µA Current IC 10 mA 100 mA Figure 29 ASTEC Semiconductor IC = 10 µA VCE = 3 V NPN (large) 200 1 µA 100 mA Figure 28 VBE vs IC Over Temperature (– 55° C to 125° C) 1000 10 mA 100 –60 –40 –20 0 20 40 60 80 Temperature (° C) Figure 30 125 IC = 1 µA 100 120 140 Semicustom Bipolar Array AS17xx Typical Performance Curves BETA vs IE Over Temperature (– 55° C to 125° C) BETA vs IE Over Temperature (– 55° C to 125° C) 300 300 VCE = 3 V 280 260 240 Vertical PNP 240 220 220 200 180 200 180 T = 0° C 160 BETA BETA VCE = 3 V 280 260 Lateral PNP T = 25° C 140 T = 70° C 120 100 T = 25° C 160 T = 70° C 140 T = –55° C 120 T = –55° C 100 80 80 60 60 T = 125° C 40 T = 0° C T = 125° C 40 20 20 0 10 µA 100 µA 1 mA Current IE 0 10 µA 10 mA 100 µA Figure 31 10 mA Figure 32 VBE SAT vs Temperature (With different IC) VCE SAT vs IC 1000 1000 Forced Beta: β = 1 900 900 Lateral PNP 800 Forced Beta: β = 1 Lateral PNP 800 T = 25° C 700 VCE SAT (mV) 700 VCE SAT (mV) 1 mA Current IE 600 500 400 600 500 400 300 300 200 200 100 100 2 4 6 8 10 12 14 Current IC (mA) 16 18 IC = 10 mA IC = 5 mA IC = 1 mA IC = 100 µA IC = 10 µA 0 –60 –40 –20 0 0 0 IC = 20 mA 20 Figure 33 20 40 60 80 Temperature (° C) Figure 34 ASTEC Semiconductor 126 100 120 140 Semicustom Bipolar Array AS17xx Typical Performance Curves VBE vs IC Over Temperature (– 55° C to 125° C) VBE vs IC Over Temperature (– 55° C to 125° C) 1100 1500 1400 VCE = 3 V Lateral PNP 1000 Forced Beta: β = 1 1300 VBE SAT (mV) VBE (mV) 1100 T = 0° C 1000 900 900 T = –55° C 1200 T = 25° C T = 70° C 800 800 T = –55° C T = 0° C 700 600 T = 125° C 700 600 500 T = 125° C T = 25° C 500 400 T = 70° C 400 300 1 µA Lateral PNP 10 µA 100 µA Current IC 1 mA 300 1 µA 10 mA 10 µA Figure 35 100 µA Current IC 10 mA Figure 36 The Semicustom Application Resistor Summary The Design Considerations 8 - Pinch Resistors (≈30 kΩ ± 50%, use at ≤ 5 V) 80 - Base String Resistors Using full string lengths gives: 73 – 4 kΩ 7 – 1.5 kΩ Using separate pieces of the strings gives: 67 – 500 Ω 63 – 1 kΩ 43 – 2 kΩ 30 – 4 kΩ The designer should take advantage of the resistor and transistor matching available with ICs and not rely on the absolute values of parameters. If a certain emitter area is desired for current ratioing, several transistors can be connected in parallel to simulate this condition, or by using the desired emitter area of an NPN power device (when breadboarding use the previous method). When using the doublecollector PNP transistors, do not float one of the collectors; either tie them together or tie one to the substrate. Floating one of the collectors will severely reduce the beta. There are several values and types of resistors available on the AS17xx semicustom array as outlined in the resistor summary. ASTEC Semiconductor 100 mA Note: Do not try to use one resistor string for more than one resistor unless they are connected together in the circuit. Additional components and their resistances are as follows: 13 - Cross-unders (370 Ω for full length, and 190 Ω for half length) 6 - Buses (at 10 Ω between connection points) 127 Semicustom Bipolar Array AS17xx Non-Integratable Components Identify all non-integratable components such as inductors and capacitors. These will have to be supplied with external components. Note that junction capacitors can be formed using transistors with collector and emitter tied together for limited capacitance values. Minimizing Stray Effects (Parasitics, Currents, and Capacitance) The following steps are recommended: 1) Try to keep substrate currents as low as possible (under a few mA) to prevent isolation loss and cross-talk between adjacent components. If a component has a high substrate current, try to isolate it from the other components and keep it as close to the substrate bonding pad as possible. The substrate current should be measured for either each kit part or the whole breadboard (with all the substrates tied together) using a 10 Ω resistor connected to the most negative potential in the circuit. 2) Do not saturate any PNP. If this is unavoidable, limit the base current so that the substrate current in the kit part lead is kept low. This is because of the parasitic vertical PNP formed between the emitter, base and substrate in a lateral PNP will become active when the lateral PNP is saturated. 3) Do not use any diode-connected PNP over about 500 µA to avoid the above mentioned parasitic PNP. 4) Contact the N-layer (collector-plug) in the resistor-tubs to the most positive potential (this is for resistor-tub biasing and isolation, and is a concern only for the semicustom implementation of the circuit), and the substrate to the most negative potential in the circuit. 5) High-frequency oscillations can, on rare occasions, occur in the integrated circuit when the breadboard did not show any tendency toward oscillation. This can be caused by the stray capacitances in the breadboard, which are larger than those associated with the IC and tend to stabilize potentially unstable circuits. Therefore, every effort should be made to minimize stray capacitances in the breadboard. This can be done by using DIP sockets and soldered wire or printed circuit interconnects rather than the popular solderless plugin breadboards which have up to 10 pF of pin-to-pin capacitance. Breadboarding with Kit Parts All circuits should be breadboarded before being implemented on the semicustom array using AS1700 Kit Parts, (which are transistor arrays made using the AS17xx semicustom array). This breadboard will simulate as accurately as possible all stray effects and how the circuit will perform when implemented with the semicustom array. We recommend that standard carbon resistors be used to simulate the integrated resistors, or precision thin film resistors if accurate ratios are required. Evaluating your breadboard After obtaining satisfactory performance from the breadboard, evaluate the effects of resistor, transistor and temperature variations. We recommend simulating the worst-case resistance variations (which is 30% globally and 1% for matching and ratioing) on the breadboard by substituting the appropriate values for all resistors. Sensitivity to transistor parameter variations can be seen by interchanging kit parts. We also recommend that the breadboard be tested over the full operating temperature range of the circuit. ASTEC Semiconductor 128 Semicustom Bipolar Array AS17xx After testing is complete, make sure that the breadboard circuit is accurately reflected in the schematic by doing a thorough check to see if all modifications to the breadboard are included. with the other blocks. If the blocks are in sequence, the circuit can usually be divided so that only one or two connections are made between the blocks (other than power supply connections). Layout options Block location: Next, add up the number of devices and pads required by each block. Then select an area of the chip for each block. There are a few considerations which must be kept in mind for the block placement. First, the selected area must contain the required number of components and pads. Second, the various areas should be located so that interconnections between them are as easy as possible. Finally, the locations of the various pads to be bonded to pins and their relationships to each other and the blocks should be considered. Bond wires should not cross each other. After thoroughly testing the breadboard, begin the layout process. There are three options for doing the layout: • Customer layout - You do the layout and provide Astec with a completed layout sheet (at 500x - which Astec will provide) ready for entry into our CAD system. Astec will review the layout for design rule violations and advise you so that you can correct them yourself or elect to have Astec fix them. • Vendor layout - You may assign Astec the responsibility of the IC layout. • Customer supervised layout - You assign the layout implementation to Astec but retain the responsibility for the final form and content. Basically you are subcontracting Astec to do the IC layout under your direction. This option requires a great deal of communication between the customer and Astec, but can yield the greatest control for the customer while reducing the layout time. Cross-unders & buses: Cross-unders can be useful for small resistance values, but be careful of connections that can not tolerate cross-under resistance (see resistor summary), such as the base connections for a diode-biased current source, etc. To make sure that a connection can tolerate the cross-under resistance, insert the appropriate valued resistor in the breadboard and evaluate its effect on circuit performance. Buses have low resistance and are valuable for connecting functional blocks together, and busing power supply voltages. Layout guidelines We recommend that several copies of the layout on the data sheet be made to facilitate the layout process before working with the 500x layout sheet. The layout copies can be used to sketch various interconnect options, and work out any design problems that may be encountered because of the layout process. Thermal considerations: If one or more components dissipate heat, they should be located away from other components that require close matching. The matched components should be placed together an equal distance from the thermal source. This way both of the matched components will be heated equally. Total power dissipation in the circuit is a function of the package type and size. On average at least 500 mW can be dissipated without trouble. Larger packages can dissipate more heat. Functional blocks: We recommend that the circuit be broken down into functional blocks. The blocks are selected in such a way as to minimize the the number of interconnections ASTEC Semiconductor 129 Semicustom Bipolar Array AS17xx Signal & common coupling: If high frequency signals are present which have large amplitude swings, these lines should be separated as much as possible with respect to their pin locations because of inductive or capacitive coupling between their pins and bonding wires. Another coupling problem arises when there are long metal lines. For example, if there is a common ground line for both the input and output of an amplifier, the fluctuating current from the output could cause a voltage drop along the line that could effect the input. This coupling could cause distortion or oscillations. The solution to this problem is to run two separate ground lines to the ground pad. Resistor ratioing: Where matched resistor values or precise ratios are required, identical resistor constructs and orientations should be used. Identical resistors orientated 90° to each other may have different values due to directionally dependent fabrication and packaging tolerances. Component interconnection: We recommend numbering the components on the circuit schematic and using these numbers on the layout. Work on only one circuit block at a time and leave the block interconnections until all the blocks are finished. Start the layout by selecting several components of a block and placing them on the layout; sketch their interconnections and work outward marking the schematic as you go. Metal routing: The metal routing can be sketched on the layout sheet taking into account the design rule considerations as follows: • • The area around the outside of the chip has a metalized ring with numerous contacts to the substrate. The substrate must be connected to the most negative potential in the circuit. When laying out the circuit, the ground conductors should lead inward from the outer ring. There are several N-layer contacts for the different resistor tub areas that must be connected to the most positive potential in the circuit to maintain isolation. Bonding pads: The rules for bonding pad layouts are very simple. You must be able to draw a straight line from a bonding pad to its pin without crossing any other wires, and the pads should be evenly spaced around the chip. The pin assignments are arbitrary, but they should be organized such that the pin numbers correspond to the pads in a counter-clockwise rotation around the chip, and not some random pattern that would cause bonding wires to cross each other. Layout sheets (500x) are available upon request for final layout, and are used to make the metal interconnect mask and check spacing rules. We recommend that the metal interconnect be done on a clear film over the layout sheet with erasable markers before making the final layout. This will allow for modifications to be made with a minimum amount of effort. Design Rules: • • Current capacity of metal trace = 4 mA per micron of width Metal line to pad (active) = 24 microns (note: metal resistance ≈ 0.02 Ω per square) Minimum metal width = 8 microns Minimum spacing between metal traces = 8 microns ASTEC Semiconductor 130 Semicustom Bipolar Array AS17xx Functional Circuit Blocks The following circuits are presented as a guide to assist in circuit design using the AS17xx Semicustom Array.Complex circuit functions can be created from these elementry building blocks.These circuit blocks can be modified and improved to suit the designer’s needs in creating a complete system. Current Sources Here are a few examples of PNP current sources; NPN current sinks can easly be derived from the analog of these PNP examples. IIN IIN IOUT Figure 2. Simple PNP Current Source. Has Slower Frequency Response, and up to ±15% Tolerance Error. IOUT = IIN * (1 + 2/β) IIN IOUT Figure 3. Widlar Current Source, Moderate Frequency Response. IOUT = IIN * (1 + 2/β2) IOUT Figure 4. Wilson Current Source, Fast Frequency Response. IOUT = IIN * (1 + 1/2β2) Comparator Input Stages Several comparator input stages are illustrated below. VCC VCC VCC V– V+ VO V+ V– VO Figure 5. Simple NPN Type Comparator. ASTEC Semiconductor Figure 6. Simple NPN Type Comparator Input Stage. 131 V+ V– VO Figure 7. Improved PNP Type (Good GND Sensing) Comparator Input Stage. Semicustom Bipolar Array AS17xx Functional Circuit Blocks Voltage Regulators/References VCC R3 Q2 R2 Q1 VO R1 Figure 8. Zener Diode VZ = 7 V Figure 9. VBE Multipled Regulator. VOUT = VBE * R2 /R1 VCC V0 R1 – R2 + Q3 Q 2 5X Q1 Q1 20X R3 Q2 VO R1 R2 Figure 11. Brokaw Band Gap Reference. ∆VBE = V(R1) = VT * ln (A1/A2) VOUT = VBE(Q2) + V(R1) * 2 * R2/R1 Figure 10. Widlar Band Gap Reference. ∆VBE = V(R3) = VT * ln (A2/A1) VOUT = VBE(Q3) + (R2/R3) * ∆VBE ASTEC Semiconductor 132 Semicustom Bipolar Array AS17xx Functional Circuit Blocks Flip-Flop Here are two examples of flip-flop circuits. VCC Q VCC Load Resistor Set Reset Output Set Reset Figure 17. Fast, ECL Flip-Flop ASTEC Semiconductor Figure 18. Four Layer Latch Flip-Flop 133 Semicustom Bipolar Array AS17xx Functional Circuit Blocks Trimming Schemes There often arises the need to trim a parameter (i.e. voltage, current, oscillator frequency, offset null, etc.) to some particular value because of processing variations involved with wafer fabrication. We have developed two methods to accomplish this goal: 1) fuse link, where a fuse is blown to cause an open; and 2) zener zap, where a zener is taken well into breakdown until a short occurs. Fuse Link Fuse links can be used similar to zeners for trimming, but the fuses must be located on a bonding pad inside the pad cut because a fuse won’t blow if there is passivation over it. One possible trim scheme using fuse links is shown below. Metal Trace To Circuit Fuse Link Pad Figure 13. Figure 12. Zener Zap When using zener zap trim methods there are several points to keep in mind: the zener should be located near a pad, no cross-unders should be used to connect the zener with the pad, and the metal lines connecting the pad to the zener should be as thick as possible to allow the high current necessary to blow the zener. A few examples of the many possible trim schemes are shown in Figure 14, Figure 15 and Figure 16. Figure 14. Simple Trim Setup with 8 Trim Steps. Figure 15. Trim Scheme Using Only 3 Pads to Get 16 Trim Steps. ASTEC Semiconductor 134 Figure 16. Parallel Trim Scheme with 8 Trim Steps. Semicustom Bipolar Array AS17xx Spice Models: .MODEL Nmin NPN; Minimum NPN + (IS = 0.5FA BF = 200 NF = .995 VAF = 100 IKF = 20M NE = 1.45 + EG = 1.185 BR = 5 NR = 0.98 VAR = 30 IKR = 2M XTB = 0.3 + RB = 270 RC = 60 RE = 7 TRB1 = 1.5M XTI = 2.5 + CJE = 450FF VJE = 0.85 MJE = 0.36 TF = 300PS + CJC = 200FF VJC = 0.57 MJC = 0.47 + CJS = 1.4PF VJS = 0.31 MJS = 0.35) .MODEL Plat LPNP; Lateral PNP + (IS = 0.9FA BF = 80 NF = 1 IKF = 60U NE = 1.5 + EG = 1.2 BR = 30 NR = 0.98 IKR = 2M + RB = 30 RC = 200 RE = 15 TRC1 = 1.5M TRE1 = 1.5M + VAF = 45 VAR = 30 + CJE = 150FF VJE = 0.57 MJE = 0.47 TF = 30NS + CJC = 950FF VJC = 0.57 MJC = 0.47 XTB = 0.5 + CJS = 1.4PF VJS = 0.31 MJS = 0.35) .MODEL Pvert LPNP; Vertical PNP + (IS = 0.9FA BF = 100 NF = .995 VAF = 45 IKF = 1.5M + EG = 1.22 BR = 30 NR = 0.98 VAR = 30 IKR = 2M NE = 1.25 + RB = 350 RC = 200 RE = 300 TRC1 = 1.5M TRE1 = 1.5M + CJE = 150FF VJE = 0.57 MJE = 0.47 TF = 30NS + CJC = 1.6PF VJC = 0.57 MJC = 0.47 XTB = 0.5) .MODEL RBase RES; Base Resistor + (R = 1 TC1 = 2.1m TC2 = 7u) .MODEL RImp RES; Implant Resistor + (R = 1.0 TC1 = 4m TC2 = 6u) .MODEL RPinch RES; Pinch Resistor + (R = 1.0 TC1 = 7m) .MODEL Dzener D; + (BV = 7.2V IBV = 1uA RS = 270 IS = .1fA) ASTEC Semiconductor 135 Semicustom Bipolar Array AS17xx Component Summary Device Layout Components Available (single tile): Small NPN: 48 Dual collector PNP: 21 Vertical PNP 4 Power NPN 3 Diffused Resistors (total) ≈300 kΩ Pinch Resistors (3-terminal, 30kΩ) 8 Cross-unders 13 Buses 6 R F R R' F' R' Pinch Resistor with Field Contact C B C C E C Resistor Summary Resistor Summary: 8 - Pinch Resistors (≈30 kΩ ± 50%, use at ≤ 5 V) 80 - Base String Resistors Using full string lengths gives: 73 - 4 kΩ 7 - 1.5 kΩ Using separate pieces of the strings gives: 67 - 500 Ω 63 - 1 kΩ 43 - 2 kΩ 30 - 4 kΩ Additional components and their resistances are as follows: 13 - Cross-unders (370 Ω for full length, and 190 Ω for half length) 6 - Buses (at 10 Ω between connection points) Minimum NPN B E B B C B Vertical PNP C B E C' B Lateral PNP with Split Collector Design Rules Design Rules: • Minimum metal width = 8 microns • Minimum spacing between metal traces = 8 microns • Current capacity of metal trace = 4 mA per micron of width • Metal line to pad (active) = 24 microns (note: metal resistance ≈ 0.02 Ω per square) C B E E E E E E E E E B E B E B E E E E E E E E E Power (20x) NPN ASTEC Semiconductor 136 B C Semicustom Bipolar Array AS17xx Device Layout ASTEC Semiconductor 137 Semicustom Bipolar Array AS17xx Notes ASTEC Semiconductor 138