ALSC AS29LV400B

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• Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
• JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO; availability TBD
• Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
- DQ2 toggle bit
- RY/BY output
• Erase suspend/resume
- Supports reading data from or programming data
to a sector not being erased
• Low VCC write lock-out below 1.5V
• 10 year data retention at 150C
• 100,000 write/erase cycle endurance
• Organization: 512Kx8/256Kx16
• Sector architecture
- One 16K; two 8K; one 32K; and seven 64K byte sectors
- One 8K; two 4K; one 16K; and seven 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
• Single 2.7-3.6V power supply for read/write operations
• Sector protection
• High speed 70/80/90/120 ns address access time
• Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
• Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
• Hardware RE S E T pin
- Resets internal state machine to read mode
/RJLFEORFNGLDJUDP
RY/BY
VCC
VSS
RESET
DQ0–DQ15
Erase voltage
generator
Input/output
buffers
Program/erase
control
BYTE
Command
register
Program voltage
generator
Chip enable
Output enable
Logic
CE
OE
A-1
STB
VCC detector
Timer
Address latch
WE
Sector protect/
erase voltage
switches
STB
Data latch
Y decoder
Y gating
X decoder
Cell matrix
A0–A17
6HOHFWLRQJXLGH
Maximum access time
Maximum chip enable access time
Maximum output enable access time
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tCE
tOE
29LV400-70
70
70
30
29LV400-80
80
80
30
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29LV400-90
90
90
35
29LV400-120
120
120
50
Unit
ns
ns
ns
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48-pin TSOP
NC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AS29LV400
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
BY/RY
NC
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
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2
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6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AS29LV400
44-pin SO (availability TBD)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
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RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
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The AS29LV400 is an 4 megabit, 3.0 volt Flash memory organized as 512Kbyte of 8 bits/256Kbytes of 16 bits each. For flexible
Erase and Program capability, the 4 megabits of data is divided into eleven sectors: one 16K, two 8K, one 32K, and seven 64k
byte sectors; or one 8K, two 4K, one 16K, and seven 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16 data appears
on DQ0–DQ15. The AS29LV400 is offered in JEDEC standard 48-pin TSOP and 44-pin SO. This device is designed to be
programmed and erased with a single 3.0V VCC supply. The device can also be reprogrammed in standard EPROM programmers.
The AS29LV400 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To
eliminate bus contention the device has separate chip enable (C E ), write enable (WE ), and output enable (O E ) controls. Word
mode (×16 output) is selected by B YT E = high. Byte mode (×8 output) is selected by BY TE = low.
The AS29LV400 is fully compatible with the JEDEC single power supply Flash standard. The device uses standard microprocessor
write timings to send Write commands to the register. An internal state-machine uses register contents to control the erase and
programming circuitry. Write cycles also internally latch addresses and data needed for the Programming and Erase operations.
Data is read in the same manner as other Flash or EPROM devices. Use the Program command sequence to invoke the on-chip
programming algorithm that automatically times the program pulse widths, and verifies proper cell margin. Use the Erase
command sequence to invoke the automated on-chip erase algorithm that preprograms the sector when it is not already
programmed before executing the erase operation. The Erase command also times the erase pulse widths and verifies the proper
cell margins.
Boot sector architecture enables the system to boot from either the top (AS29LV400T) or the bottom (AS29LV400B) sector.
Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other
sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both the Program and the
Erase operations in all, or any combination of the eleven sectors. The device provides true background erase with Erase Suspend,
which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The Chip
Erase command will automatically erase all unprotected sectors.
When shipped from the factory, AS29LV400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is
programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change
bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no
effect on other sectors.
The device features a single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and
regulated voltages are provided for the Program and Erase operations. A low V CC detector automatically inhibits write operations
during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect the end of the
program or to erase operations. The device automatically resets to the Read mode after the Program or Erase operations are
completed. DQ2 indicates which sectors are being erased.
The AS29LV400 resists accidental erasure or spurious programming signals resulting from power transitions. The Control
register architecture permits alteration of memory contents only when successful completion of specific command sequences has
occured. During power up, the device is set to Read mode with all Program/Erase commands disabled if VCC is less than VLKO
(lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on O E , CE , or WE . To initiate Write
commands, CE and WE must be a logical zero and O E a logical 1.
When the device’s hardware R E S E T pin is driven low, any Program/Erase operation in progress is terminated and the internal
state machine is reset to Read mode. If the RE S E T pin is tied to the system reset circuitry and a system reset occurs during an
automated on-chip Program/Erase algorithm, the operating data in the address locations may become corrupted and require
rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.
The AS29LV400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are
programmed one at a time using the EPROM programming mechanism of hot electron injection.
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Mode
ID read MFR code
ID read device code
Read
Standby
Output disable
Write
Enable sector protect
Sector unprotect
Temporary sector
unprotect
Verify sector protect†
Verify sector unprotect†
Hardware Reset
CE
OE
WE
L
L
L
X
H
H
VID
VID
H
H
H
X
H
L
Pulse/L
Pulse/L
A0
L
H
A0
X
X
A0
L
L
A1
L
L
A1
X
X
A1
H
H
A6
L
L
A6
X
X
A6
L
H
A9
VID
VID
A9
X
X
A9
VID
VID
R E SE T
L
L
L
H
L
L
L
L
X
X
X
X
X
X
X
VID
L
L
X
L
L
X
H
H
X
L
L
X
H
H
X
L
H
X
VID
VID
X
H
H
L
H
H
H
H
H
H
H
H
DQ
Code
Code
DOUT
High Z
High Z
DIN
X
X
X
Code
Code
High Z
L = Low (<VIL) = logic 0; H = High (>VIH) = logic 1; VID = 10.0 ± 1.0V; X = don’t care.
In ×16 mode, BYTE = VIH. In ×8 mode, BYTE = VIL with DQ8-DQ14 in high Z and DQ15 = A-1.
†Verification of sector protect/unprotect during A9 = V
ID.
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Item
Description
Selected by A9 = VID(9.5V–10.5V), C E = O E = A1 = A6 = L, enabling outputs.
ID MFR code,
When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.
device code
When A0 is high (VIH), DOUT represents the device code for the AS29LV400.
Selected with CE = O E = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after C E is low
Read mode
and tOE after O E is low.
Selected with C E = H. Part is powered down, and ICC reduced to <1.0 µA when C E = VCC ± 0.3V = RE S E T.
If activated during an automated on-chip algorithm, the device completes the operation before entering
Standby
standby.
Output disable Part remains powered up; but outputs disabled with O E pulled high.
Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command
register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
Write
on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE,
whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.
Hardware protection circuitry implemented with external programming equipment causes the device to
Enable
disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector
sector protect
protect algorithm on page 12.
Disables sector protection for all sectors using external programming equipment. All sectors must be
Sector
protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect
unprotect
algorithm on page 12.
Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
Verify sector
programming equipment. Determine if sector protection exists in a system by writing the ID read command
protect/
sequence and reading location XXX02h, where address bits A12–17 select the defined sector addresses. A
unprotect
logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.
Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to R ES E T
Temporary
to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected
sector
sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal
unprotect
of +10V from R ES E T.
Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data
RE SE T
may be corrupted.
Deep
Hold RESET low to enter deep power down mode (<1 µA). Recovery time to start of first read cycle is 50ns.
power down
Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data is
Automatic
available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new
sleep mode
data is returned within standard access times.
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Sector
0
1
2
3
4
5
6
7
8
9
10
Bottom boot sector architecture (AS29LV400B)
×8
×16
Size (Kbytes)
00000h–03FFFh 00000h–01FFFh
16
04000h–05FFFh 02000h–02FFFh
8
06000h–07FFFh 03000h–03FFFh
8
08000h–0FFFFh 04000h–07FFFh
32
10000h–1FFFFh 08000h–0FFFFh
64
20000h–2FFFFh 10000h–17FFFh
64
30000h–3FFFFh 18000h–1FFFFh
64
40000h–4FFFFh 20000h–27FFFh
64
50000h–5FFFFh 28000h–2FFFFh
64
60000h–6FFFFh 30000h–37FFFh
64
70000h–7FFFFh 38000h–3FFFFh
64
Top boot sector architecture (AS29LV400T)
×8
×16
Size (Kbytes)
00000h–0FFFFh 00000h–07FFFh
64
10000h–1FFFFh 08000h–0FFFFh
64
20000h–2FFFFh 10000h–17FFFh
64
30000h–3FFFFh 18000h–1FFFFh
64
40000h–4FFFFh 20000h–27FFFh
64
50000h–5FFFFh 28000h–2FFFFh
64
60000h–6FFFFh 30000h–37FFFh
64
70000h–77FFFh 38000h–3BFFFh
32
78000h–79FFFh 3C000h–3CFFFh
8
7A000h–7BFFFh 3D000h–3DFFFh
8
7C000h–7FFFFh 3E000h–3FFFFh
16
In word mode, there are one 8K word, two 4K word, one 16K word, and seven 32K word sectors. Address range is A17–A-1 if B YT E = VIL; address range is
A17–A0 if B YT E = VIH.
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Sector
0
1
2
3
4
5
6
7
8
9
10
A17
0
0
0
0
0
0
0
1
1
1
1
Bottom boot sector address
(AS29LV400B)
A16 A15 A14 A13 A12
0
0
0
0
X
0
0
0
1
0
0
0
0
1
1
0
0
1
X
X
0
1
X
X
X
1
0
X
X
X
1
1
X
X
X
0
0
X
X
X
0
1
X
X
X
1
0
X
X
X
1
1
X
X
X
A17
0
0
0
0
1
1
1
1
1
1
1
Top boot sector address
(AS29LV400T)
A16
A15
A14
A13
A12
0
0
X
X
X
0
1
X
X
X
1
0
X
X
X
1
1
X
X
X
0
0
X
X
X
0
1
X
X
X
1
0
X
X
X
1
1
0
X
X
1
1
1
0
0
1
1
1
0
1
1
1
1
1
X
A6
A1
5($'FRGHV
Mode
A17–A12
MFR code (Alliance Semiconductor)
×8 T boot
×8 B boot
×16 T boot
×16 B boot
Device code
Sector protection
A0
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
Sector address
L
H
L
Code
52h
B9h
BAh
22B9h
22BAh
01h protected
00h unprotected
Key: L =Low (<VIL); H = High (>VIH); X =Don’t care
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Command
sequence
Required 1st bus cycle 2nd bus cycle
bus write
cycles Address Data Address Data
Reset/Read
Reset/
Read
×16
×8
1
3
×16
XXXh
555h
AAAh
F0h
AAh
555h
Read
Address
2AAh
555h
×16
Autosele
×8
ct
ID Read
×16
AAAh
555h
3
AAAh
Unlock
bypass
×16
×8
AAh
2AAh
555h
×16
×8
3
Unlock bypass
program
2
Unlock bypass
reset
2
×16
Chip
Erase
×8
Sector
Erase
×8
×16
6
6
555h
AAAh
555
AAA
AAh
XXX
A0h
XXX
90h
555h
AAAh
555h
AAAh
AAh
AAh
Sector Erase
Suspend
1
XXXh
B0h
Sector Erase
Resume
1
XXXh
30h
1
2
3
4
5
6
90h
AAAh
55h
555h
AAAh
55h
2AAh
555h
2AA
555
55h
XXX
00h
2AAh
555h
555h
AAAh
555
55h
Program
data
555h
90h
AAAh
Program
address
2AAh
90h
555h
555h
AAh
F0h
555h
2AAh
AAAh
4
555h
AAAh
55h
AAh
Program
55h
555h
555h
×8
Address Data
4th bus cycle
Address
Data
Read Address
Read
Data
01h
Device code
22B9h (T)
22BAh (B)
02h
Device code
B9h(T)
BAh(B)
00h
MFR code
0052h
5th bus cycle
6th bus cycle
Address Data Address Data
Read
Data
2AAh
AAh
×8
3rd bus cycle
55h
55h
AAA
555h
AAAh
555h
AAAh
A0h
52h
XXX02h
Sector
protection
0001h = protected
0000h = unprotected
XXX04h
Sector
protection
0001h=protected
0000h=unprotected
Program
Address
Program
Data
20h
80h
80h
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
55h
555h
AAAh
Sector
Address
Bus operations defined in "Mode definitions," on page 3.
Reading from and programming to non-erasing sectors allowed in Erase
Suspend mode.
Address bits A11-A17 = X = Don’t Care for all address commands
except where Program Address and Sector Address are required.
Data bits DQ15-DQ8 are don’t care for unlock and command cycles.
The Unlock Bypass command must be initiated before the Unlock
Bypass Program command.
The Unlock Bypass Reset command returns the device to reading array
data when it is in the unlock bypass mode.
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Item
Reset/Read
Description
Initiate read or reset operations by writing the Read/Reset command sequence into the command
register. This allows the microprocessor to retrieve data from the memory. Device remains in read
mode until command register contents are altered.
Device automatically powers up in read/reset state. This feature allows only reads, therefore
ensuring no spurious memory content alterations during power up.
AS29LV400 provides manufacturer and device codes in two ways. External PROM programmers
typically access the device codes by driving +10V on A9. AS29LV400 also contains an ID Read
command to read the device code with only +3V, since multiplexing +10V on address lines is
generally undesirable.
ID Read
Initiate device ID read by writing the ID Read command sequence into the command register.
Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command
sequence with a read sequence from address XXX01h to return device code.
To verify write protect status on sectors, read address XXX02h. Sector addresses A17–A12 produce
a 1 on DQ0 for protected sector and a 0 for unprotected sector.
Hardware Reset
Byte/word
Programming
Exit from ID read mode with Read/Reset command sequence.
Holding RE S E T low for 500 ns resets the device, terminating any operation in progress; data
handled in the operation is corrupted. The internal state machine resets 20 µs after RE S E T is driven
low. RY/BY remains low until internal state machine resets. After R E S ET is set high, there is a delay
of 50 ns for the device to permit read operations.
Programming the AS29LV400 is a four bus cycle operation performed on a byte-by-byte or wordby-word basis. Two unlock write cycles precede the Program Setup command and program data
write cycle. Upon execution of the program command, no additional CPU controls or timings are
necessary. Addresses are latched on the falling edge of C E or WE , whichever is last; data is latched
on the rising edge of CE or WE , whichever is first. The AS29LV400’s automated on-chip program
algorithm provides adequate internally-generated programming pulses and verifies the
programmed cell margin.
Check programming status by sampling data on the RY/BY pin, or either the DATA polling (DQ7)
or toggle bit (DQ6) at the program address location. The programming operation is complete if
DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/BY pin = high.
The AS29LV400 ignores commands written during programming. A hardware reset occurring
during programming may corrupt the data at the programmed location.
AS29LV400 allows programming in any sequence, across any sector boundary. Changing data from
0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1
(exceeded programming time limits); reading this data after a read/reset operation returns a 0.
When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this
state, a Reset command returns the device to read mode.
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Item
Description
The unlock bypass feature increases the speed at which the system programs bytes or words to the
device because it bypasses the first two unlock cycles of the standard program command sequence.
To initiate the unlock bypass command sequence, two unlock cycles must be written, then
followed by a third cycle which has the unlock bypass command, 20h.
Unlock Bypass
Command Sequence
The device then begins the unlock bypass mode. In order to program in this mode, a two cycle
unlock bypass program sequence is required. The first cycle has the unlock bypass program
command, A0h. It is followed by a second cycle which has the program address and data. To
program additional data, the same sequence must be followed.
The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the
Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by
issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first
cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don’t care for
both cycles. The device then returns to reading array data.
Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional
unlock write cycles; and finally the Chip Erase command.
Chip Erase
Sector Erase
Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip
erase algorithm is invoked with the Chip Erase command sequence, AS29LV400 automatically
programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV400
returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding
time limit.
Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional
unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by
addressing any location in the sector. The address is latched on the falling edge of WE ; the
command, 30h is latched on the rising edge of WE . The sector erase operation begins after a sector
erase time-out.
To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to
erase after following the six bus cycle operation above. Timing between writes of additional sectors
must be less than the erase time-out period, or the AS29LV400 ignores the command and erasure
begins. During the time-out period any falling edge of WE resets the time-out. Any command
(other than Sector Erase or Erase Suspend) during time-out period resets the AS29LV400 to read
mode, and the device ignores the sector erase command string. Erase such ignored sectors by
restarting the Sector Erase command on the ignored sectors.
The entire array need not be written with 0s prior to erasure. AS29LV400 writes 0s to the entire
sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected
sectors unaffected. AS29LV400 requires no CPU control or timing signals during sector erase
operations.
Automatic sector erase begins after sector erase time-out from the last rising edge of WE from the
sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling
address must be performed on addresses that fall within the sectors being erased. AS29LV400
returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit.
9/26/01; V.0.9.9.2
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Item
Description
Erase Suspend allows interruption of sector erase operations to read data from or program data to a
sector not being erased. Erase suspend applies only during sector erase operations, including the
time-out period. Writing an Erase Suspend command during sector erase time-out results in
immediate termination of the time-out period and suspension of erase operation.
AS29LV400 ignores any commands during erase suspend other than Read/Reset, Program or Erase
Resume commands. Writing the Erase Resume Command continues erase operations. Addresses are
Don’t Care when writing Erase Suspend or Erase Resume commands.
Erase Suspend
AS29LV400 takes 0.2–15 µs to suspend erase operations after receiving Erase Suspend command.
To determine completion of erase suspend, either check DQ6 after selecting an address of a sector
not being erased, or poll RY/B Y. Check DQ2 in conjunction with DQ6 to determine if a sector is
being erased. AS29LV400 ignores redundant writes of Erase Suspend.
While in erase-suspend mode, AS29LV400 allows reading data (erase-suspend-read mode) from or
programming data (erase-suspend-program mode) to any sector not undergoing sector erase;
these operations are treated as standard read or standard programming mode. AS29LV400 defaults
to erase-suspend-read mode while an erase operation has been suspended.
Sector Protect
Ready/Busy
9/26/01; V.0.9.9.2
Write the Resume command 30h to continue operation of sector erase. AS29LV400 ignores
redundant writes of the Resume command. AS29LV400 permits multiple suspend/resume
operations during sector erase.
When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated
for about <1 µs. When attempting to erase a protected sector, DATA polling and
Toggle Bit 1 (DQ6) are activated for about <5 µs. In both cases, the device returns to read mode
without altering the specified sectors.
RY/BY indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or
completed (RY/B Y = high). The device does not accept Program/Erase commands when
RY/BY = low. RY/B Y = high when device is in erase suspend mode. RY/BY = high when device
exceeds time limit, indicating that a program or erase operation has failed. RY/BY is an open drain
output, enabling multiple RY/BY pins to be tied in parallel with a pull up resistor to VCC.
$OOLDQFH6HPLFRQGXFWRU
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Temporary sector
unprotect mode
No
START
START
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
Wait 1 µs
Wait 1 µs
Protect all sectors:
The shaded portion of
the sector protct
algorithm must be
initiated for all
unprotected sectors
before calling the
sector unprotect
First Write
Cycle=60h?
Yes
Set up sector
address
Sector protect:
write 60h to sector
address with
A6=0, A1=1,
A0=0
No
All sectors
protected?
Yes
Sector unprotect:
write 60h to sector
address with
A6=1, A1=1,
A0=0
Verify sector
protect; write 40h
to sector address
with A6=0,
A1=1, A0=0
PLSCNT=25?
Wait 15 ms
Set up first
sector address
Read from sector
address with A6=0,
A1=1, A0=0
No
No
Verify sector
unprotect; write 40h
to sector address
with A6=1,
A1=1, A0=0
Increment
PLSCNT
Read from sector
address with A6=1,
A1=1, A0=0
Data=01h?
No
Yes
Set up next
sector address
Yes
Device failed
Protect
another
sector?
Temporary sector
unprotect mode
Yes
Wait 150 µs
Increment
PLSCNT
No
First Write
Cycle=60h?
Yes
PLSCNT
=1000?
No
Remove VID
from RESET#
No
Data=00h?
Yes
Yes
Device failed
Write reset
command
Last sector
verified?
No
Yes
Remove VID
from RESET#
Sector protect
complete
Write reset
command
Sector unprotect
complete
9/26/01; V.0.9.9.2
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DATA polling (DQ7)
Toggle bit 1 (DQ6)
Exceeding time limit
(DQ5)
Sector erase timer
(DQ3)
Toggle bit 2 (DQ2)
Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects
complement of data last written when read during the automated on-chip program algorithm (0
during erase algorithm); reflects true data when read after completion of an automated on-chip
program algorithm (1 after completion of erase agorithm).
Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when C E or
O E toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the
fourth pulse of WE during programming; after the rising edge of the sixth WE pulse during chip
erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors,
DQ6 toggles for <1 µs during program mode writes, and <5 µs during erase (if all selected sectors
are protected).
Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains
active. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming or
sector erase, the sector is defective (in this case, reset the device and execute a program or erase
command sequence to continue working with functional sectors). Attempting to program 0 to 1
will set DQ5 = 1.
Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands
will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and
after each Sector Erase command to verify that the command was accepted.
During sector erase, DQ2 toggles with O E or C E only during an attempt to read a sector being
erased. During chip erase, DQ2 toggles with O E or CE for all addresses. If DQ5 = 1, DQ2 toggles
only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use
DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend
mode.
:ULWHRSHUDWLRQVWDWXV
Standard mode
Erase suspend mode
Exceeded time limits
Status
Auto programming
Program/erase in auto erase
Read erasing sector
Read non-erasing sector
Program in erase suspend
Auto programming (byte)
Program/erase in auto erase
Program in erase suspend
(non-erase suspended sector)
DQ7
DQ7
0
1
Data
DQ7
DQ7
0
DQ6
Toggle
Toggle
No toggle
Data
Toggle
Toggle
Toggle
DQ5
0
0
0
Data
0
1
1
DQ3
N/A
1
N/A
Data
N/A
N/A
N/A
DQ2
No toggle
Toggle†
Toggle
Data
Toggle†
No toggle
Toggle†
RY/B Y
0
0
1
1
0
1
1
DQ7
Toggle
1
N/A
No toggle
1
DQ2 toggles when an erase-suspended sector is read repeatedly.
DQ6 toggles when any address is read repeatedly.
DQ2 = 1 if byte address being programmed is read during erase-suspend program mode.
†DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase.
9/26/01; V.0.9.9.2
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START
START
Write erase command sequence
(see below)
Write program command sequence
(see below)
DATA polling or toggle bit
successfully completed
DATA polling or toggle bit
successfully completed
Erase complete
Increment address
Last
Chip erase command sequence
×16 mode (address/data):
Individual sector/multiple sector
erase command sequence
×16 mode (address/data):
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector address/30h
NO
address?
YES
Programming completed
Program command sequence
×16 mode (address/data):
555h/AAh
2AAh/55h
555h/A0h
Sector address/30h
Program address/program data
Sector address/30h
optional sector erase commands
† The system software should check the status of DQ3 prior to and following each
subsequent sector erase command to ensure command completion. The device may
not have accepted the command if DQ3 is high on second status check.
9/26/01; V.0.9.9.2
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Unlock bypass command sequence
x16 mode (address/data)
START
555h/AAh
Write unlock
bypass command
(3 cycles)
2AAh/55h
555h/20h
Write unlock
bypass program command
(2 cycles)
Unlock bypass program
command sequence
x16 mode (address/data)
DATA polling or
toggle bit
successfully completed
xxxh/A0h
program address/
Increment
address
Last
address?
program data
NO
Unlock bypass reset
command sequence
x16 mode (address/data)
YES
xxxh/90h
Write unlock
bypass reset command
(2 cycles)
xxxh/00h
Programming completed
9/26/01; V.0.9.9.2
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7RJJOHELWDOJRULWKP
Read byte (DQ0–DQ7)
Address = VA†
Read byte (DQ0–DQ7)
Address = don’t care
DQ7
=
data
?
DQ6
=
toggle
?
YES DONE
NO
NO
DQ5
NO
=
1
?
YES
YES
Read byte (DQ0–DQ7)
Address = VA
Read byte (DQ0–DQ7)
Address = don’t care
YES†
DQ6
=
toggle†
?
DONE
NO†
NO
DONE
YES
FAIL
FAIL
† VA = Byte address for programming. VA = any of the sector
addresses within the sector being erased during Sector Erase. VA =
valid address equals any non-protected sector group address
during Chip Erase.
‡ DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not
change simultaneously.
9/26/01; V.0.9.9.2
DONE
YES
DQ5
=
1
?
DQ7
=
data‡
?
NO
†DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling
when DQ5 changes to 1.
$OOLDQFH6HPLFRQGXFWRU
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Parameter
9&& ±9
Symbol Test conditions
Input load current
ILI
VIN = VSS to VCC, VCC = VCC MAX
A9 Input load current
ILIT
VCC = VCC MAX, A9 = 10V
Output leakage current
ILO
VOUT = VSS to VCC, VCC = VCC MAX
Active current, read @ 5MHz
ICC1
Active current, program/erase
ICC2
Automatic sleep mode*
ICC3
Standby current
ISB
Deep power down current3
IPD
Input low voltage
Min
Max
±1
µA
35
µA
-
±1
µA
C E = VIL, O E = VIH
-
20
mA
C E = VIL, O E = VIH
-
100
mA
C E = VIL, O E = VIH;
-
5
µA
C E = VCC - 0.3V, R E S ET = VCC - .3V
-
5
µA
R E S E T = 0.3V
-
5
µA
VIL
-0.5
0.8
V
Input high voltage
VIH
0.7×VCC
VCC + 0.3
V
Output low voltage
VOL
IOL = 4.0mA, VCC = VCC MIN
-
0.45
V
Output high voltage
VOH
IOH = -2.0 mA, VCC = VCC MIN
0.85×VCC
-
V
Low VCC lock out voltage
VLKO
1.5
-
V
Input HV select voltage
VID
9
11
V
VIL= 0.3V, VIH = VCC - 0.3V
-
Unit
* Automatic sleep mode enables the deep power down mode when addresses are stable for 150 ns. Typical sleep mode current is 200 nA.
9/26/01; V.0.9.9.2
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JEDEC
Symbol
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
Std Symbol
tRC
tACC
tCE
tOE
tOES
tDF
tDF
tAXQX
tOH
tOEH
tPHQV
tRH
tREADY
tRP
-70
Min Max
70
70
70
30
0
20
20
Parameter
Read cycle time
Address to output delay
Chip enable to output
Output enable to output
Output enable setup time
Chip enable to output High Z
Output enable to output High Z
Output hold time from addresses,
first occurrence of CE or OE
Output enable hold time: Read
Output enable hold time:
Toggle and data polling
R E SE T high to output delay
R E SE T pin low to read mode
R E SE T pulse
-80
-90
-120
Min Max Min Max Min Max
80
90
120
80
90
120
80
90
120
30
35
50
0
0
0
20
30
30
20
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
0
-
0
-
0
-
0
-
ns
10
-
10
-
10
-
10
-
ns
10
-
10
-
10
-
10
-
ns
500
50
10
500
50
10
-
500
50
10
-
500
50
10
-
ns
µs
ns
5HDGZDYHIRUP
tRC
Addresses stable
Addresses
tACC
CE
tDF
tOE
tOES
OE
tOEH
WE
tCE
Outputs
High Z
tOH
Output valid
High Z
tRH
R ES E T
9/26/01; V.0.9.9.2
$OOLDQFH6HPLFRQGXFWRU
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-70
-80
-90
WE FRQWUROOHG
-120
Min Max Unit
JEDEC
Symbol
Std Symbol Parameter
Min
Max
Min
Max
Min
Max
tAVAV
tAVWL
tWC
tAS
Write cycle time
Address setup time
70
0
-
80
0
-
90
0
-
120
0
-
ns
ns
tWLAX
tDVWH
tAH
tDS
Address hold time
Data setup time
45
35
-
45
35
-
45
45
-
50
50
-
ns
ns
tWHDX
tGHWL
tDH
tGHWL
Data hold time
Read recover time before write
0
0
-
0
0
-
0
0
-
0
0
-
ns
ns
tELWL
tWHEH
tCS
tCH
C E setup time
C E hold time
0
0
-
0
0
-
0
0
-
0
0
-
ns
ns
tWLWH
tWHWL
tWP
tWPH
Write pulse width
Write pulse width high
35
30
-
35
30
-
35
30
-
50
30
-
ns
ns
:ULWHZDYHIRUP
WE FRQWUROOHG
WWC
3rd bus cycle
555h
Addresses
WAS
DATA polling
Program address
Program address
WAH
WCH
CE
WGHWL; tOES
OE
WWP
WE
DATA
9/26/01; V.0.9.9.2
WCS
WWHWH1 or 2
WWPH
WDH
A0h
WDS
Program
data
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DOUT
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-70
-80
-90
Max
C E FRQWUROOHG
-120
Min Max
Unit
JEDEC
Symbol
Std Symbol
Parameter
Min
Max
Min
Max
Min
tAVAV
tAVEL
tWC
tAS
Write cycle time
Address setup time
70
0
-
80
0
-
90
0
-
120
0
-
ns
ns
tELAX
tDVEH
tAH
tDS
Address hold time
Data setup time
45
35
-
45
35
-
45
45
-
50
50
-
ns
ns
tEHDX
tGHEL
tDH
tGHEL
Data hold time
Read recover time before write
0
0
-
0
0
-
0
0
-
0
0
-
ns
ns
tWLEL
tEHWH
tWS
tWH
WE setup time
WE hold time
0
0
-
0
0
-
0
0
-
0
0
-
ns
ns
tELEH
tEHEL
tCP
tCPH
C E pulse width
C E pulse width high
35
30
-
35
30
-
35
30
-
50
30
-
ns
ns
:ULWHZDYHIRUP
C E FRQWUROOHG
DATA polling
Addresses
555h
Program address
tWC
tAS
Program address
tAH
WE
tGHEL, tOES
OE
tCP
tWHWH1 or 2
CE
tCPH
tDH
DATA
A0h
Program
data
DQ 7
DOUT
tDS
9/26/01; V.0.9.9.2
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JEDEC
Symbol
-70
-80
-90
-120
Min
Max
Std
Symbol
Parameter
Min
Max
Min
Max
Min
Max
tVIDR
VID rise and fall time
500
-
500
-
500
-
500
-
ns
tRSP
RE S E T setup time for
temporary sector unprotect
4
-
4
-
4
-
4
-
µs
Unit
7HPSRUDU\VHFWRUXQSURWHFWZDYHIRUP
10V
0 or 3V
R E S ET
tVIDR
CE
0 or 3V
tVIDR
Program/erase command sequence
WE
tRSP
RY/B Y
$&SDUDPHWHUV²R E SE T
JEDEC
Symbol
-70
-80
-90
-120
Std
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tRP
tRH
RE S E T pulse
RE S E T High time before Read
500
-
50
500
-
50
500
-
50
500
-
50
ns
ns
tREADY
RE S E T Low to Read mode
-
10
-
10
-
10
-
10
µs
R ES E TZDYHIRUP
tRP
RESET
tRP
tREADY
RY/BY
tRH
DQ
status
status
valid data
valid data
(UDVHZDYHIRUP
îPRGH
tWC
Addresses
tAS
555h
2AAh
555h
555h
2AAh
Sector address
tAH
CE
tGHWL
OE
tWP
tWC
WE
tWPH
tCS
10h for Chip Erase
tDH
Data
AAh
55h
80h
AAh
55h
30h
tDS
9/26/01; V.0.9.9.2
$OOLDQFH6HPLFRQGXFWRU
P. 20 of 26
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JEDEC
Symbol
-80
Min Max
-90
Min Max
-120
Min Max
-
50
-
50
-
50
-
µs
0
-
0
-
0
-
0
-
ns
90
-
90
-
90
-
90
-
ns
Std Symbol
Parameter
Min
-
tVCS
VCC setup time
50
-
tRB
-
tBUSY
Recovery time from RY/BY
Program/erase valid to RY/BY delay
-70
Max
Unit
RY/BYZDYHIRUP
CE
Rising edge of last WE signal
WE
RY/B Y
tri-stated open-drain
tBUSY
Program/erase
operation
tRB
VCC
tVCS
'$7$SROOLQJZDYHIRUP
tCH
CE
tDF
tOE
OE
tOEH
WE
tCE
tOH
DQ7
Output DQ Input DQ7
Output
High Z
tWHWH1 or 2
7RJJOHELWZDYHIRUP
CE
tOEH
WE
OE
DQ6
tOE
tDH
9/26/01; V.0.9.9.2
toggle
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toggle
no toggle
P. 21 of 26
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-70
Max
-80
Min Max
-90
Min Max
-120
Min Max
JEDEC
Symbol
Std Symbol
Parameter
-
tELFL/tELFH
tFLQZ
C E to BYTE switching Low or High
B YT E switching Low to output High-Z
-
10
30
-
10
30
-
10
35
-
10
40
ns
ns
-
tFHQZ
B YT E switching High to output Active
70
-
80
-
90
-
120
-
ns
Min
%<7(UHDGZDYHIRUP
CE
OE
B YTE
Word
to
Byte
tELFL
DQ15/A-1
tELFH
B YTE
Byte
to
Word
DQ0-DQ14
Data output
DQ0-DQ14
DQ0-DQ7
Data output
DQ15 output
tFLQZ
DQ0-DQ14
DQ0-DQ7
Data output
DQ15/A-1
Address input
Address input
DQ0-DQ14
Data output
DQ15 output
tFHQV
B YTE ZULWHZDYHIRUP
CE
falling edge of last WE signal
WE
BY TE
See Erase/Program operations table for tAS and tAH specifications.
tSET
(tAS)
tHOLD (tAH)
6HFWRUSURWHFWXQSURWHFW
R E S ET #
VID
VIH
SA, A6,
A1, A0
Don’t care
Valid*
Don’t care
Valid*
Don’t care
Valid*
Don’t care
Verify
40h
Don’t care
Status
Sector protect/unprotect
DATA
CE#
60h
1 µs
60h
Sector protect: 100 µs
Sector unprotect: 10 ms
WE#
OE#
* For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0.
9/26/01; V.0.9.9.2
$OOLDQFH6HPLFRQGXFWRU
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Unit
$6/9
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9
1
RUHTXLYDOHQW
.Ω
'HYLFHXQGHUWHVW
.Ω
&/
966
1
RUHTXLYDOHQW
966
966
7HVWVSHFLILFDWLRQV
-70,
-90,
Test Condition
Output Load
-80
-120
Output Load Capacitance CL (including jig capacitance)
30
Unit
1 TTL gate
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement reference levels
Output timing measurement reference levels
100
pF
5
0.0-3.0
ns
V
1.5
1.5
V
V
(UDVHDQGSURJUDPPLQJSHUIRUPDQFH
Parameter
Sector erase and verify-1 time (excludes 00h programming
prior to erase)
Byte
Word
Programming time
Chip programming time
Erase/program cycles*
Min
Limits
Typical
Max
Unit
-
1.0
15
sec
-
10
15
7.2
100,000
300
360
27
-
µs
µs
sec
cycles
* Erase/program cycle test is not verified on each shipped unit.
/DWFKXSWROHUDQFH
Parameter
Min
Max
Unit
Input voltage with respect to VSS on A9, OEand RESET pin
-1.0
+12.0
V
Input voltage with respect to VSS on all DQ, address, and control pins
-0.5
VCC+0.5
V
Current
-100
+100
mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
9/26/01; V.0.9.9.2
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Parameter
Symbol
VCC
VSS
VIH
VIL
Supply voltage
Input voltage
Min
+2.7
0
1.9
–0.5
Max
+3.6
0
VCC + 0.3
0.8
Unit
V
V
V
V
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Parameter
Input voltage (Input or DQ pin)
Input voltage (A9 pin, OE , RES ET )
Power supply voltage
Operating temperature
Storage temperature (plastic)
Short circuit output current
Symbol
VIN
VIN
VCC
TOPR
TSTG
IOUT
Min
–0.5
–0.5
-0.5
–55
–65
-
Max
VCC+ 0.5
+12.5
+4.0
+125
+150
150
Unit
V
V
V
°C
°C
mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
7623SLQFDSDFLWDQFH
Symbol
CIN
COUT
CIN2
Parameter
Input capacitance
Output capacitance
Control pin capacitance
Test setup
VIN = 0
VOUT = 0
VIN = 0
Typ
6
8.5
8
Max
7.5
12
10
Unit
pF
pF
pF
Test setup
VIN = 0
VOUT = 0
VIN = 0
Typ
6
8.5
8
Max
7.5
12
10
Unit
pF
pF
pF
62SLQFDSDFLWDQFHDYDLODEOLW\7%'
Symbol
CIN
COUT
CIN2
Parameter
Input capacitance
Output capacitance
Control pin capacitance
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Parameter
Temp.(°C)
150°
125°
Minimum pattern data retention time
9/26/01; V.0.9.9.2
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Min
10
20
Unit
years
years
P. 24 of 26
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Package dimensions
b
e
48-pin
12×20
c
A2
L
pin 1
A
A1
pin 48
pin 24
D
Hd
pin 25
48-pin
α
Min
Max
–
1.20
0.05
0.15
0.95
1.05
0.17
0.27
0.15 nominal
18.20
18.60
0.50 nominal
11.90
12.10
19.80
20.20
0.50
0.70
0°
5°
A
A1
A2
b
c
D
e
E
Hd
L
α
E
6PDOO2XWOLQHSODVWLFSDFNDJH62
Package dimensions
JEDEC MO - 175 AA
44-pin SO
Min
Max
(mm)
(mm)
A
–
3.1
A1
0.05
–
A2
2.5
2.9
b
0.25
0.45
c
0.09
0.25
d
28.0
28.4
e
12.4
12.8
E
1.27 (typical)
He
16.05 (typical)
l
0.73
1.3
9/26/01; V.0.9.9.2
c
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
e He
SO
1
2
3
4
5
6
7
8
0–10°
9 10 11 12 13 14 15 16 17 18 19 20 21 22
d
A2
A
A1
b
l
E
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Package \ Access Time
70ns(commercial
and industrial)
80ns(commercil
and industrial)
90ns(commercial
and industrial)
120ns(commercial and
industrial)
TSOP, 12×20 mm, 48-pin
Top boot configuration
TSOP, 12×20 mm, 48-pin
Bottom boot configuration
SO*, 13.3 mm, 44-pin
Top boot configuration
SO, 13.3 mm, 44-pin
Bottom boot configuration
AS29LV400T-70TC
AS29LV400T-70TI
AS29LV400B-70TC
AS29LV400B-70TI
AS29LV400T-70SC
AS29LV400T-70SI
AS29LV400B-70SC
AS29LV400B-70SI
AS29LV400T-80TC
AS29LV400T-80TI
AS29LV400B-80TC
AS29LV400B-80TI
AS29LV400T-80SC
AS29LV400T-80SI
AS29LV400B-80SC
AS29LV400B-80SI
AS29LV400T-90TC
AS29LV400T-90TI
AS29LV400B-90TC
AS29LV400B-90TI
AS29LV400T-90SC
AS29LV400T-90SI
AS29LV400B-90SC
AS29LV400B-90SI
AS29LV400T-120TC
AS29LV400T-120TI
AS29LV400B-120TC
AS29LV400B-120TI
AS29LV400T-120SC
AS29LV400T-120SI
AS29LV400B-120SC
AS29LV400B-120SI
VKDGHGDUHDLQGLFDWHVDGYDQFHGLQIRUPDWLRQDYDLODELOLW\RI62SDFNDJHLV7%'
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AS29LV
400
3V Flash
EEPROM
prefix
Device T= Top boot configuration
number B= Bottom boot configuration
9/26/01; V.0.9.9.2
X
–XXX
X
X
Address
access time
Package:
S = SO*
T = TSOP
Temperature range:
C = Commercial: 0°C to 70°C
I = Industrial: -40°C to 85°C
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X
Options:
B = Burn-in
H = High ISB (<1mA)
Blank= Standard
P. 26 of 26
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under
development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or
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express agreed to in Alliance’s Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance’s Terms and Conditions of Sale. The purchase of
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for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.