ALSC AS7C1024

November 2000
AS7C1024
AS7C31024
®
5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)
Features
• 2.0V data retention
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
• AS7C1024 (5V version)
• AS7C31024 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
-
- 10/12/15/20 ns address access time
- 5/6/8/10 ns output enable access time
• Low power consumption: ACTIVE
300 mil SOJ
400 mil SOJ
8 × 20mm TSOP I
8 × 13.4 mm sTSOP I
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
- 825 mW (c) / max @ 12 ns
- 360 mW (AS7C31024) / max @ 12 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024) / max CMOS
- 36 mW (AS7C31024) / max CMOS
Logic block diagram
Pin arrangement
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
I/O7
512 ×256×8
Array
(1,048,576)
Sense amp
Row decoder
Input buffer
I/O0
Control
circuit
A9
A10
A11
A12
A13
A14
A15
A16
Column decoder
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AS7C1024
AS7C31024
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
32-pin TSOP I
(8 x 20mm)
VCC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
WE
OE
CE1
CE2
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Selection guide
AS7C1024-10
AS7C31024-10
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
AS7C1024
AS7C31024
AS7C1024
AS7C31024
10
5
150
100
10
10
AS7C1024-12 AS7C1024-15 AS7C1024-20
AS7C31024-12 AS7C31024-15 AS7C31024-20
12
15
20
6
8
10
140
125
110
90
80
75
10
10
15
10
10
15
Unit
ns
ns
mA
mA
mA
mA
Shaded areas contain advance information.
11/29/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS7C1024
AS7C31024
®
Functional description
The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 131,072 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/8/10 ns
are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with
multiple-bank systems.
When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume ISB power.
If the bus is static, then full standby power is reached (I SB1 or ISB2). For example, the AS7C31024 is guaranteed not to exceed
0.33mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid
bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable ( OE) or write
enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high.
The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output
enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
AS7C1024
Vt1
–0.50
+7.0
V
AS7C31024
Vt1
-0.50
+5.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–
1.0
W
Storage temperature (plastic)
Tstg
–65
+150
°C
Ambient temperature with V CC applied
Tbias
–55
+125
°C
DC current into outputs (low)
IOUT
–
20
mA
Voltage on VCC relative to GND
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE1
CE2
WE
OE
Data
Mode
H
X
X
X
High Z
Standby (ISB, ISB1)
X
L
X
X
High Z
Standby (ISB, ISB1)
L
H
H
H
High Z
Output disable (ICC)
L
H
H
L
DOUT
Read (ICC)
L
H
L
X
DIN
Write (ICC)
Key: X = Don’t Care, L = Low, H = High
2
ALLIANCE SEMICONDUCTOR
11/29/00
AS7C1024
AS7C31024
®
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature
Device
Symbol
Min
Nominal
Max
Unit
AS7C1024
VCC
4.5
5.0
5.5
V
AS7C31024
VCC
3.0
3.3
3.6
V
AS7C1024
VIH
2.2
–
VCC + 0.5
V
AS7C31024
VIH
2.0
–
VCC + 0.5
V
VIL†
–0.5
–
0.8
V
commercial
TA
0
–
70
°C
industrial
TA
–40
–
85
°C
† V min = –3.0V for pulse width less than t
IL
RC/2.
DC operating characteristics (over the operating range)
-10
-12
-15
-20
Unit
Parameter
Sym
Test conditions
Device
Min Max Min Max Min Max Min Max
Input leakage
current
|ILI| VCC = Max, VIN = GND to VCC
–
1
–
1
–
1
–
1
µA
Output leakage
current
|ILO|
VCC = Max, CE1 = VIH or
CE2 = VIL, VOUT = GND to VCC
–
1
–
1
–
1
–
1
µA
Operating
power supply
current
AS7C1024
VCC = Max, CE1 = VIL,
CE2 = VIH, f = fMax, I OUT = 0
AS7C31024
mA
–
150
–
140
–
125
–
110
ICC
–
100
–
90
–
80
–
75
VCC = Max, CE1 ≥ VIH and/or AS7C1024
CE2 ≤ VIL, VIN = VIH or VIL,
AS7C31024
f = fMax, IOUT = 0mA
–
80
–
75
–
65
–
60
ISB
–
60
–
50
–
40
–
35
AS7C1024
–
10
–
10
–
10
–
15
AS7C31024
–
10
–
10
–
10
–
15
Standby power
supply current
Output voltage
mA
mA
ISB1
VCC = Max, CE1 ≥ VCC–0.2V
VIN ≤ GND + 0.2V or
VIN ≥ VCC –0.2V, f = 0
VOL
IOL = 8 mA, V CC = Min
–
0.4
–
0.4
–
0.4
–
0.4
V
VOH
IOH = –4 mA, VCC = Min
2.4
–
2.4
–
2.4
–
2.4
–
V
mA
Shaded areas contain advance information.
Capacitance (f = 1 MHz, T a = 25 °C, VCC = NOMINAL)
11/29/00
Parameter
Symbol
Signals
Test conditions
Max
Unit
Input capacitance
CIN
A, CE1, CE2, WE, OE
VIN = 0V
5
pF
I/O capacitance
CI/O
I/O
VIN = VOUT = 0V
7
pF
ALLIANCE SEMICONDUCTOR
3
AS7C1024
AS7C31024
®
Read cycle (over the operating range)
-10
-12
-15
-20
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Read cycle time
tRC
10
–
12
–
15
–
20
–
ns
Address access time
tAA
–
10
–
12
–
15
–
20
ns
3
Chip enable (CE1) access time
tACE1
–
10
–
12
–
15
–
20
ns
3, 12
Chip enable (CE2) access time
tACE2
–
10
–
12
–
15
–
20
ns
3, 12
Output enable (OE) access time
tOE
–
3
–
3
–
4
–
5
ns
Output hold from address change
tOH
2
–
3
–
3
–
3
–
ns
5
CE1 Low to output in low Z
tCLZ1
3
–
3
–
3
–
3
–
ns
4, 5, 12
CE2 High to output in low Z
tCLZ2
3
–
3
–
3
–
3
–
ns
4, 5, 12
CE1 Low to output in high Z
tCHZ1
–
3
–
3
–
4
–
5
ns
4, 5, 12
CE2 Low to output in high Z
tCHZ2
–
3
–
3
–
4
–
5
ns
4, 5, 12
OE Low to output in low Z
tOLZ
0
–
0
–
0
–
0
–
ns
4, 5
OE High to output in high Z
tOHZ
–
3
–
3
–
4
–
5
ns
4, 5
Power up time
tPU
0
–
0
–
0
–
0
–
ns
4, 5, 12
Power down time
tPD
–
10
–
12
–
15
–
20
ns
4, 5, 12
Parameter
Notes
Key to switching waveforms
Rising input
Falling input
Undefined / don’t care
Read waveform 1 (address controlled)
tRC
Address
tAA
tOH
DOUT
Data valid
Read waveform 2 (CE1, CE2, and OE controlled)
tRC1
CE1
CE2
tOE
OE
DOUT
Current
supply
4
tOHZ
tCHZ1, tCHZ2
tOLZ
tACE1, tACE2
tCLZ1, tCLZ2
tPU
Data valid
tPD
50%
50%
ALLIANCE SEMICONDUCTOR
ICC
ISB
11/29/00
AS7C1024
AS7C31024
®
Write cycle (over the operating range)
-10
-12
-15
-20
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Write cycle time
tWC
10
–
12
–
15
–
20
–
ns
Chip enable (CE1) to write end
tCW1
9
–
10
–
12
–
12
–
ns
12
Chip enable (CE2) to write end
tCW2
9
–
10
–
12
–
12
–
ns
12
Address setup to write end
tAW
9
–
10
–
12
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
0
–
ns
Write pulse width
tWP
7
–
8
–
9
–
12
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
0
–
ns
Data valid to write end
tDW
6
–
6
–
9
–
10
–
ns
Data hold time
tDH
0
–
0
–
0
–
0
–
ns
4, 5
Write enable to output in high Z
tWZ
–
5
–
5
–
5
–
5
ns
4, 5
Output active from write end
tOW
3
–
3
–
3
–
3
–
ns
4, 5
Parameter
Notes
12
Shaded areas contain advance information.
Write waveform 1 ( WE controlled)
tAW
tWC
tAH
Address
tWP
WE
tAS
tDW
DIN
tDH
Data valid
tWZ
tOW
DOUT
Write waveform 2 (CE1 and CE2 controlled)
tAW
tWC
tAH
Address
tAS
tCW1, tCW2
CE1
CE2
tWP
WE
tWZ
DIN
tDW
tDH
Data valid
D OUT
11/29/00
ALLIANCE SEMICONDUCTOR
5
AS7C1024
AS7C31024
®
Data retention characteristics (over the operating range)
Parameter
Symbol
VCC for data retention
VDR
Data retention current
ICCDR
Chip deselect to data retention time
tCDR
Operation recovery time
Test conditions
VCC = 2.0V
CE1 ≥ VCC–0.2V or
CE2 ≤ 0.2V
VIN ≥ VCC–0.2V or
VIN ≤ 0.2V
tR
Input leakage current
Device
Min
Max
Unit
2.0
–
V
AS7C1024
–
5
mA
AS7C31024
–
1
mA
0
–
ns
tRC
–
ns
–
1
µA
| ILI |
Data retention waveform
Data retention mode
VCC
VDR ≥ 2.0V
VCC
VCC
tCDR
tR
VDR
VIH
CE1
VIH
AC test conditions
–
–
–
–
5V output load: see Figure B or Figure C.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Thevenin equivalent:
168W
DOUT
+1.728V (5V and 3.3V)
+5V
+3.3V
480W
+3.0V
GND
90%
10%
D OUT
255W
90%
2 ns
Figure A: Input pulse
10%
C(14)
320W
DOUT
255W
GND
Figure B: 5V Output load
C(14)
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
6
During V CC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
This parameter is sampled and not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, and C.
tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE1 and OE are Low and CE2 is High for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
CE1 and CE2 have identical timing.
2V data retention applies to commercial temperature operating range only.
C=30pF, except all high Z and low Z parameters, C=5pF.
ALLIANCE SEMICONDUCTOR
11/29/00
AS7C1024
AS7C31024
®
Typical DC and AC characteristics
1.4
1.0
0.8
0.6
ISB
0.4
0.2
0.6
ISB
0.4
0.0
–55
MAX
Normalized access time
1.2
1.1
1.0
0.9
NOMINAL
Supply voltage (V)
Output sink current (mA)
Ta = 25° C
100
80
60
40
20
0
VCC
Output voltage (V)
0.04
–10
35
80
125
Ambient temperature (°C)
-55
1.2
1.1
1.0
0.9
-10
35
80
125
Ambient temperature (°C)
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
1.4
VCC = VCC(NOMINAL)
Ta = 25° C
1.0
0.8
0.6
0.4
0.2
0.0
–10
35
80
125
Ambient temperature (°C)
0
Output sink current IOL
vs. output voltage VOL
120
30
Ta = 25° C
100
80
60
40
20
25
50
75
Cycle frequency (MHz)
100
Typical access time change ∆tAA
vs. output capacitive loading
35
VCC = VCC(NOMINAL)
VCC = VCC (NOMINAL)
25
20
15
10
5
0
0
0.2
VCC = VCC(NOMINAL)
1.3
140
VCC = VCC (NOMINAL)
120
1
1.2
0.8
–55
MAX
Output source current I OH
vs. output voltage VOH
140
5
1.4
Ta = 25° C
VCC = VCC(NOMINAL)
25
Normalized access time tAA
vs. ambient temperature T a
1.5
1.3
0.8
MIN
625
Normalized ICC
1.4
Normalized access time
NOMINAL
Supply voltage (V)
Normalized access time tAA
vs. supply voltage VCC
1.5
Output source current (mA)
0.8
0.2
0.0
MIN
11/29/00
ICC
1.0
Normalized supply current ISB1
vs. ambient temperature Ta
Normalized ISB1 (log scale)
1.2
ICC
Normalized ICC, ISB
Normalized ICC, ISB
1.2
Normalized supply current ICC, ISB
vs. ambient temperature T a
Change in tAA (ns)
1.4
Normalized supply current ICC, I SB
vs. supply voltage VCC
0
0
VCC
Output voltage (V)
ALLIANCE SEMICONDUCTOR
0
250
500
750
Capacitance (pF)
1000
7
AS7C1024
AS7C31024
®
Package dimensions
A
D
B
S
E1 E
A
A1
B
b
c
D
E
E1
e
eA
L
a
S
L
e
A1
b
Seating
Plane
Pin 1
α
c
eA
D
B
e
A
E1 E2 A1
Seating
Plane
b
Pin 1
A
A1
A2
B
b
c
D
E
E1
E2
e
c
A2
E
b
e
α
D
Hd
32-pin SOJ 300 mil 32-pin SOJ 400 mil
Min
Max
Min
Max
0.145
0.145
0.025
0.025
0.086
0.105
0.086
0.115
0.026
0.032
0.026
0.032
0.014
0.020
0.015
0.020
0.006
0.013
0.007
0.013
0.820
0.830
0.820
0.830
0.250
0.275
0.360
0.380
0.292
0.305
0.395
0.405
0.330
0.340
0.435
0.445
0.050 BSC
0.050 BSC
c
A2
L
E
pin 1
pin 32
pin 16
pin 17
A
A1
A
A1
A2
b
c
D
e
E
Hd
L
α
8
32-pin PDIP
Min
Max
0.180
0.015
0.045
0.055
0.015
0.021
0.008
0.012
1.571
0.300
0.325
0.280
0.295
0.100 BSC
0.330
0.370
0.110
0.142
0°
15°
0.043
ALLIANCE SEMICONDUCTOR
32-pin TSOP 8×20
Min
Max
–
1.20
0.05
0.15
0.95
1.05
0.17
0.27
0.10
0.21
18.20
18.60
0.50 nominal
7.80
8.20
19.80
20.20
0.50
0.70
0°
5°
11/29/00
AS7C1024
AS7C31024
®
Ordering codes
Package \ Access
time
Plastic SOJ, 300 mL
Plastic SOJ, 400 mL
TSOP 8×20
Volt/Temp
10 ns
12 ns
15 ns
20 ns
5V commercial
AS7C1024-10TJC
AS7C1024-12TJC
AS7C1024-15TJC
AS7C1024-20TJC
5V industrial
NA
AS7C1024-12TJI
AS7C1024-15TJI
AS7C1024-20TJI
3.3V commercial
AS7C31024-10TJC
AS7C31024-12TJC
AS7C31024-15TJC
AS7C31024-20TJC
3.3V industrial
NA
AS7C31024-12TJI
AS7C31024-15TJI
AS7C31024-20TJI
5V commercial
AS7C1024-10JC
AS7C1024-12JC
AS7C1024-15JC
AS7C1024-20JC
5V industrial
NA
AS7C1024-12JI
AS7C1024-15JI
AS7C1024-20JI
3.3V commercial
AS7C31024-10JC
AS7C31024-12JC
AS7C31024-15JC
AS7C31024-20JC
3.3V industrial
NA
AS7C31024-12JI
AS7C31024-15JI
AS7C31024-20JI
5V commercial
NA
AS7C1024-12TC
AS7C1024-15TC
AS7C1024-20TC
5V industrial
NA
AS7C1024-12TI
AS7C1024-15TI
AS7C1024-20TI
3.3V commercial
NA
AS7C31024-12TC
AS7C31024-15TC
AS7C31024-20TC
3.3V industrial
NA
AS7C31024-12TI
AS7C31024-15TI
AS7C31024-20TI
NA: not available
Shaded areas contain advance information.
Part numbering system
AS7C
X
1024
–XX
X
X
SRAM
prefix
Blank=5V CMOS
3=3.3V CMOS
Device
number
Access
time
Package: TP=PDIP 300 mil
T=TSOP 8×20
J=SOJ 400 mil
TJ=SOJ 300 mil
Temperature range
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C
11/29/00
ALLIANCE SEMICONDUCTOR
9
Copyright ©2000 Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and Intelliwatt™ are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of
their respective companies. Alliance reserves the right to make changes to this web site and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this web site. Alliance does not
assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to fitness for a particular purpose, merchantability, or infringement
of any intellectual property rights, except as expressly agreed to in Alliance's Terms and Conditions of Sale (available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of
Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.