February 2005 AS7C33128PFD32B AS7C33128PFD36B ® 3.3V 128K X 32/36 pipeline burst synchronous SRAM Features • • • • • • • • Organization: 131,072 words × 32 or 36 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package • • • • • • • Individual byte write and global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs Logic block diagram LBO CLK ADV ADSC ADSP CLK CE CLR 17 A[16:0] D CE Address register CLK GWE BWE BWd 15 128K × 32/36 Memory array 17 36/32 D DQd Q Byte write registers CLK 36/32 D DQc Q Byte write registers CLK BWc D DQb Q Byte write registers CLK BWb D DQa Q Byte write registers CLK BWa CE0 CE1 CE2 ZZ Q0 Burst logic Q1 17 Q D 4 OE Output registers CLK Q Enable CE register CLK Input registers CLK D Enable Q delay register CLK Power down 36/32 DQ [a:d] OE Selection guide –200 –166 –133 Units 5 6 7.5 ns Maximum clock frequency 200 166 133 MHz Maximum clock access time 3.0 3.5 4 ns Maximum operating current 375 350 325 mA Maximum standby current 130 100 90 mA Maximum CMOS standby current (DC) 30 30 30 mA Minimum cycle time 1/31/05; v.1.1 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. 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AS7C33128PFD32B AS7C33128PFD36B ® 4 Mb Synchronous SRAM products list1,2 Org 256KX18 Part Number AS7C33256PFS18B Mode PL-SCD Speed 200/166/133 MHz 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33128PFD32B AS7C33128PFD36B AS7C33256FT18B AS7C33128FT32B AS7C33128FT36B AS7C33256NTD18B AS7C33128NTD32B AS7C33128NTD36B AS7C33256NTF18B AS7C33128NTF32B AS7C33128NTF36B PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM 1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 1/31/05; v.1.1 Alliance Semiconductor P. 2 of 19 AS7C33128PFD32B AS7C33128PFD36B ® 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TQFP 14 × 20 mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS NC VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPc/NC DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 NC VDD NC VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd/NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A A Pin arrangement Note: Pins 1,30,51,80 are NC for ×32 1/31/05; v.1.1 Alliance Semiconductor P. 3 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Functional description The AS7C33128PFD32B and AS7C33128PFD36B are high-performance CMOS 4-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 131,072 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for highest frequency on any given technology. Timing for these devices is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP and PowerPC™1-based systems in computing, datacom, instrumentation, and telecommunications systems. Fast cycle times of 5.0/6.0/7.5 ns with clock access times (tCD) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled Low, and both address strobes are High. Burst mode is selectable with the LBO input. With LBO unconnected or driven High, burst operations use a Pentium® count sequence. With LBO driven LOW, the device uses a linear count sequence suitable for PowerPC™ and many other applications. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s). BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled Low. Address is incremented internally to the next burst address if BWn and ADV are sampled Low. This device operates in double-cycle deselect feature during read cycles. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are as follows: • ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC. • WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High). • Master chip enable CE0 blocks ADSP, but not ADSC. AS7C33128PFD32B and AS7C33128PFD36B family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package TQFP capacitance Parameter Input capacitance I/O capacitance Symbol Test conditions Min Max Unit CIN* VIN = 0V - 5 pF VOUT = 0V - 7 pF CI/O * * Guaranteed not tested TQFP thermal resistance Description Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 Symbol Typical Units 1–layer θJA 40 °C/W 4–layer θJA 22 °C/W θJC 8 °C/W 1 This parameter is sampled 1 PowerPC™ is a trademark International Business Machines Corporation. 1/31/05; v.1.1 Alliance Semiconductor P. 4 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Signal descriptions Signal I/O Properties CLK I CLOCK A,A0,A1 I SYNC Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information. CE1, CE2 I SYNC Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. ADSP I SYNC Address strobe processor. Asserted LOW to load a new bus address or to enter standby mode. ADSC I SYNC Address strobe controller. Asserted LOW to load a new address or to enter standby mode. ADV I SYNC Advance. Asserted LOW to continue burst read/write. GWE I SYNC Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d] control write enable. BWE I SYNC Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs. BW[a,b,c,d] I SYNC Write enables. Used to control write of individual bytes when GWE = HIGH and BWE = Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write cycle. If all BW[a:d] are inactive the cycle is a read cycle. OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. LBO I STATIC Selects Burst mode. When tied to VDD or left floating, device follows Interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. NC - - DQ[a,b,c,d] Description Clock. All inputs except OE, ZZ, LBO are synchronous to this clock. No connect Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 1/31/05; v.1.1 Alliance Semiconductor P. 5 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Write enable truth table (per byte) Function GWE BWE BWa BWb BWc BWd L X X X X X Write All Bytes H L L L L L Write Byte a H L L H H H Write Byte c and d H L H H L L H H X X X X H L H H H H Read Key: X = don’t care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal. Asynchronous Truth Table Operation Snooze mode ZZ H L L L L Read Write Deselected OE X L H X X I/O Status High-Z Dout High-Z Din, High-Z High-Z Notes: 1. X means “Don’t Care” 2. ZZ pin is pulled down internally 3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Snooze mode means power down state of which stand-by current does not depend on cycle times 5. Deselected means power down state of which stand-by current depends on cycle times Burst sequence table Interleaved burst address (LBO = 1) 1st Address nd Linear burst address (LBO = 0) A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 1st Address nd A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 2 Address 01 00 11 10 2 Address 01 10 11 00 3rd Address 10 11 00 01 3rd Address 10 11 00 01 11 10 01 10 th 4 Address 1/31/05; v.1.1 11 10 01 00 th 4 Address Alliance Semiconductor P. 6 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Synchronous truth table[4] CE01 CE1 CE2 ADSP ADSC H L L L L L L L L X X X X H H H H L X H X H X L L X X H H H H X X X X X X X X H X X X X X X X H H L L L L X X X X X X X X L X X X X X L H L H L L H H H H H H X X X X H H X H X L X L X L X X L L H H H H H H H H L H H H H ADV WRITE[2] X X X X X X X X X L L H H L L H H X L L H H X X X X X X X H H H H H H H H H H L L L L L OE Address accessed CLK Operation DQ X X X X X L H L H L H L H L H L H X X X X X NA NA NA NA NA External External External External Next Next Current Current Next Next Current Current External Next Next Current Current L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H L to H Deselect Deselect Deselect Deselect Deselect Begin read Begin read Begin read Begin read Continue read Continue read Suspend read Suspend read Continue read Continue read Suspend read Suspend read Begin write Continue write Continue write Suspend write Suspend write Hi−Z Hi−Z Hi−Z Hi−Z Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z Q Hi−Z D3 D D D D 1 X = don’t care, L = low, H = high 2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information. 3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time 4 ZZ pin is always Low. 1/31/05; v.1.1 Alliance Semiconductor P. 7 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Absolute maximum ratings Parameter Symbol Min Max Unit VDD, VDDQ –0.5 +4.6 V Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V Pd – 1.8 W Short circuit output current IOUT – 20 mA Storage temperature Tstg –65 +150 o C +135 o C Power supply voltage relative to GND Power dissipation Temperature under bias Tbias –65 Stresses greater than those listed under “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. Recommended operating conditions at 3.3V I/O Parameter Symbol Min Nominal Max Unit Supply voltage for inputs VDD 3.135 3.3 3.465 V Supply voltage for I/O VDDQ 3.135 3.3 3.465 V Vss 0 0 0 V Symbol Min Nominal Max Unit Supply voltage for inputs VDD 3.135 3.3 3.465 V Supply voltage for I/O VDDQ 2.375 2.5 2.625 V Vss 0 0 0 V Ground supply Recommended operating conditions at 2.5V I/O Parameter Ground supply 1/31/05; v.1.1 Alliance Semiconductor P. 8 of 19 AS7C33128PFD32B AS7C33128PFD36B ® DC electrical characteristics for 3.3V I/O operation Parameter Sym Conditions Min Max Unit current† |ILI| VDD = Max, 0V < VIN < VDD -2 2 µA Output leakage current |ILO| OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA Input high (logic 1) voltage VIH Address and control pins 2* VDD+0.3 I/O pins 2* VDDQ+0.3 Input low (logic 0) voltage VIL Address and control pins -0.3** 0.8 I/O pins -0.5** 0.8 Output high voltage VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – V Output low voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 V Input leakage V V DC electrical characteristics for 2.5V I/O operation Parameter Sym Conditions Min Max Unit Input leakage current† |ILI| VDD = Max, 0V < VIN < VDD -2 2 µA Output leakage current |ILO| OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ -2 2 µA Input high (logic 1) voltage VIH Address and control pins 1.7* VDD+0.3 V I/O pins 1.7* VDDQ+0.3 V Input low (logic 0) voltage VIL Address and control pins -0.3** 0.7 V I/O pins -0.3** 0.7 V Output high voltage VOH IOH = –4 mA, VDDQ = 2.375V 1.7 – V Output low voltage VOL IOL = 8 mA, VDDQ = 2.625V – 0.7 V † LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA. * VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC **V IL min = -1.5 for pulse width less than 0.2 X tCYC IDD operating conditions and maximum limits Parameter Operating power supply current1 Sym ICC ISB Standby power supply current Conditions CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax, IOUT = 0 mA, ZZ < VIL All VIN ≤ 0.2V or > VDD – 0.2V, Deselected, f = fMax, ZZ < VIL -200 -166 -133 Unit 375 350 325 mA 130 100 90 ISB1 Deselected, f = 0, ZZ < 0.2V, all VIN ≤ 0.2V or ≥ VDD – 0.2V 30 30 30 ISB2 Deselected, f = fMax, ZZ ≥ VDD – 0.2V, all VIN ≤ VIL or ≥ VIH 30 30 30 mA 1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading. 1/31/05; v.1.1 Alliance Semiconductor P. 9 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Timing characteristics over operating range –200 Parameter –166 –133 Notes1 Sym Min Max Min Max Min Max Unit Clock frequency fMax – 200 – 166 – 133 MHz Cycle time tCYC 5 – 6 – 7.5 – ns Clock access time tCD – 3.0 – 3.5 – 4.0 ns Output enable LOW to data valid tOE – 3.0 – 3.5 – 4.0 ns Clock HIGH to output Low Z tLZC 0 – 0 – 0 – ns 2,3,4 Data output invalid from clock HIGH tOH 1.5 – 1.5 – 1.5 – ns 2 Output enable LOW to output Low Z tLZOE 0 – 0 – 0 – ns 2,3,4 Output enable HIGH to output High Z tHZOE – 3.0 – 3.5 – 4.0 ns 2,3,4 Clock HIGH to output High Z tHZC – 3.0 – 3.5 – 4.0 ns 2,3,4 tOHOE 0 – 0 – 0 – ns Clock HIGH pulse width tCH 2.0 – 2.4 – 2.5 – ns 5 Clock LOW pulse width tCL 2.3 – 2.4 – 2.5 – ns 5 Address setup to clock HIGH tAS 1.4 – 1.5 – 1.5 – ns 6 Data setup to clock HIGH tDS 1.4 – 1.5 – 1.5 – ns 6 Write setup to clock HIGH tWS 1.4 – 1.5 – 1.5 – ns 6,7 Chip select setup to clock HIGH tCSS 1.4 – 1.5 – 1.5 – ns 6,8 Address hold from clock HIGH tAH 0.4 – 0.5 – 0.5 – ns 6 Data hold from clock HIGH tDH 0.4 – 0.5 – 0.5 – ns 6 Write hold from clock HIGH tWH 0.4 – 0.5 – 0.5 – ns 6,7 Chip select hold from clock HIGH tCSH 0.4 – 0.5 – 0.5 – ns 6,8 ADV setup to clock HIGH tADVS 1.4 – 1.5 – 1.5 – ns 6 ADSP setup to clock HIGH tADSPS 1.4 – 1.5 – 1.5 – ns 6 ADSC setup to clock HIGH tADSCS 1.4 – 1.5 – 1.5 – ns 6 ADV hold from clock HIGH tADVH 0.4 – 0.5 – 0.5 – ns 6 ADSP hold from clock HIGH tADSPH 0.4 – 0.5 – 0.5 – ns 6 ADSC hold from clock HIGH tADSCH 0.4 – 0.5 – 0.5 – ns 6 Output enable HIGH to invalid output 1 See “Notes” on page 16. Snooze Mode Electrical Characteristics Description Current during Snooze Mode ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current 1/31/05; v.1.1 Conditions Symbol ZZ > VIH ISB2 tPDS tPUS tZZI tRZZI Alliance Semiconductor Min Max Units 30 mA cycle cycle cycle 2 2 2 0 P. 10 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Key to switching waveforms Rising input Falling input don’t care Undefined Timing waveform of read cycle tCYC tCL tCH CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC LOAD NEW ADDRESS tAH tAS A1 Address A2 tWS A3 tWH GWE, BWE tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV ADV inserts wait states OE tOE tHZOE tLZOE Dout Q(A1) Read Q(A1) Suspend Read Q(A1) Read Q(A2) tCD tHZC tOH Q(A2) Q(A2Ý01) Q(A2Ý10) Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Burst Burst Read Suspend Burst Burst Burst Burst Read Read Q(A3) DSEL* Read Read Read Read Read Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11) Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care. *Outputs are disabled within two clk cycles after DSEL command 1/31/05; v.1.1 Alliance Semiconductor P. 11 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Timing waveform of write cycle tCYC tCL tCH CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC ADSC LOADS NEW ADDRESS tAS tAH A1 Address A3 A2 tWS tWH tADVS tADVH tDS tDH BWE BW[a:d] tCSS tCSH CE0, CE2 CE1 ADV SUSPENDS BURST ADV OE Din D(A1) Read Q(A1) Suspend Write D(A1) D(A2) Read Q(A2) D(A2Ý01) Suspend Write D(A 2) D(A2Ý01) D(A2Ý10) D(A2Ý11) D(A3) ADV ADV ADV Suspend Burst Burst Burst Write Write Write D(A 2Ý01) Write D(A 2Ý01) D(A 2Ý10) D(A 2Ý11) D(A3Ý01) Write D(A 3) D(A3Ý10) Burst Write D(A 3Ý01) ADV Burst Write D(A 3Ý10) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. 1/31/05; v.1.1 Alliance Semiconductor P. 12 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Timing waveform of read/write cycle (ADSP Controlled; ADSC High) tCYC tCL tCH CLK tADSPH tADSPS ADSP tAH tAS A2 A1 Address A3 tWH tWS GWE CE0, CE2 CE1 tADVH tADVS ADV OE tDS tDH Din D(A2) tOE tCD tLZC Dout DSEL Read Q(A1) tHZOE Q(A1) Suspend Read Q(A1) tOH tLZOE Q(A3) Read Q(A2) Suspend Write D(A 2) Read Q(A3) ADV Burst Read Q(A 3Ý01) Q(A3Ý01) ADV Burst Read Q(A 3Ý10) Q(A3Ý10) Q(A3Ý11) ADV Burst Read Q(A 3Ý11) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. 1/31/05; v.1.1 Alliance Semiconductor P. 13 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Timing waveform of read/write cycle (ADSC controlled, ADSP = HIGH) tCYC tCL tCH CLK tADSCS tADSCH ADSC tAS A1 ADDRESS A5 A4 A3 A2 A7 A6 tWS tAH A8 A9 tWH GWE tCSS tCSH CE0,CE2 CE1 ADV OE tOE Q(A1) Dout tLZOE tHZOE tLZOE Q(A2) Q(A3) Q(A8) Q(A4) D(A5) READ Q(A1) 1/31/05; v.1.1 READ Q(A2) READ Q(A3) READ Q(A4) Q(A9) tDH tDS Din tOH D(A6) D(A7) WRITE WRITE WRITE D(A6) D(A7) D(A5) Alliance Semiconductor READ Q(A8) READ Q(A9) P. 14 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Timing waveform of power down cycle tCH tCYC tCL CLK tADSPS tADSPS ADSP ADSC A2 A1 ADDRESS tWH tWS GWE tCSS tCSH CE0,CE2 CE1 ADV OE tOE Din tLZOE tHZOE D(A2) D(A2(Ý01)) tHZC Dout Q(A1) tPUS tPDS ZZ Recovery Cycle ZZ Normal Operation Mode ZZ Setup Cycle tZZI tRZZI Isupply ISB2 READ SUSPEND Q(A1) READ Q(A1) 1/31/05; v.1.1 Sleep State Alliance Semiconductor READ SUSPEND CONQ(A2) WRITE TINUE D(A2) WRITE D(A2 Ý01) P. 15 of 19 AS7C33128PFD32B AS7C33128PFD36B ® AC test conditions • Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. • Input pulse level: GND to 3V. See Figure A. Thevenin equivalent: • Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O • Input and output timing reference levels: 1.5V. +3.0V 90% 10% GND 90% 10% Figure A: Input waveform DOUT Z0 = 50Ω 50Ω DOUT VL = 1.5V for 3.3V I/O; 353Ω / 1538Ω 30 pF* = V DDQ/2 for 2.5V I/O Figure B: Output load (A) 319Ω / 1667Ω 5 pF* GND *including scope and jig capacitance Figure C: Output load (B) Notes 1 For test conditions, see AC Test Conditions, Figures A, B, C. 2 This parameter measured with output load condition in Figure C. 3 This parameter is sampled, but not 100% tested. 4 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage. 5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL. 6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled. 7 Write refers to GWE, BWE, BW[a:d]. 8 Chip select refers to CE0, CE1, CE2. 1/31/05; v.1.1 Alliance Semiconductor P. 16 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Package Dimensions 100-pin quad flat pack (TQFP) Hd TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e b e He E 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 L 0.45 0.75 L1 α D 1.00 nominal 0° 7° α Dimensions in millimeters c L1 L 1/31/05; v.1.1 Alliance Semiconductor A1 A2 P. 17 of 19 AS7C33128PFD32B AS7C33128PFD36B ® Ordering information Package Width –200 –166 –133 TQFP x32 AS7C33128PFD32B-200TQC AS7C33128PFD32B-166TQC AS7C33128PFD32B-133TQC TQFP x32 AS7C33128PFD32B-200TQI AS7C33128PFD32B-166TQI AS7C33128PFD32B-133TQI TQFP x36 AS7C33128PFD36B-200TQC AS7C33128PFD36B-166TQC AS7C33128PFD36B-133TQC TQFP x36 AS7C33128PFD36B-200TQI AS7C33128PFD36B-166TQI AS7C33128PFD36B-133TQI Note Add suffix ‘N’ to the above part numbers for lead free parts (Ex. AS7C33128PFD32B-166TQCN) Part numbering guide AS7C 33 128 PF D 32/36 B –XXX TQ C/I X 1 2 3 4 5 6 7 8 9 10 11 1. Alliance Semiconductor SRAM prefix 2. Operating voltage: 33=3.3V 3. Organization: 128=128K 4. Pipeline mode 5. Deselect: D=Double cycle deselect 6. Organization: 32 = x32; 36 = x36 7. Production version: B= Product revision 8. Clock speed (MHz) 9. Package type: TQ=TQFP 10. Operating temperature: C=Commercial (0° C to 70° C); I=Industrial (-40° C to 85° C) 11. N=Lead Free Part 1/31/05; v.1.1 Alliance Semiconductor P. 18 of 19 ® AS7C33128PFD32B AS7C33128PFD36B ® Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 Copyright © Alliance Semiconductor All Rights Reserved Part Number: AS7C33128PFD32B-36B Document Version: v.1.1 www.alsc.com © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. 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