100344 Low Power 8-Bit Latch with Cut-Off Drivers General Description The 100344 contains eight D-type latches, individual inputs (Dn), outputs (Qn), a common enable pin (E), latch enable (LE), and output enable pin (OEN). A Q output follows its D input when both E and LE are LOW. When either E or LE (or both) are HIGH, a latch stores the last valid data present on its D input prior to E or LE going HIGH. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a normal ECL LOW level. This allows the output emitter-followers to turn off when the termination supply is −2.0V, presenting a high impedance to the data bus. This high impedance reduces termination power and prevents loss of low state noise margin when several loads share the bus. The 100344 outputs are designed to drive a doubly terminated 50Ω transmission line (25Ω load impedance). All inputs have 50 kΩ pull-down resistors. Features n n n n n n Cut-off drivers Drives 25Ω load Low power operation 2000V ESD protection Voltage compensated operating range = −4.2V to −5.7V Available to MIL-STD-883 Logic Symbol Pin Names Description D0–D7 Data Inputs E Enable Input LE Latch Enable Input OEN Output Enable Input Q0–Q7 Data Outputs DS100317-4 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak DS100317-2 DS100317-1 © 1998 National Semiconductor Corporation DS100317 www.national.com 100344 Low Power 8-Bit Latch with Cut-Off Drivers August 1998 Logic Diagram DS100317-5 Truth Table Inputs Outputs Dn E LE OEN L L L L L H L L L H X H X L Latched (Note 1) X X H L Latched (Note 1) X X X H Cutoff Qn H = HIGH Voltage level L = LOW Voltage level Cutoff = lower-than-LOW state X = Don’t Care Note 1: Retains data present before either LE or E go HIGH. www.national.com 2 Absolute Maximum Ratings (Note 2) ≥2000V ESD (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Recommended Operating Conditions Above which the useful life may be impaired Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) Case Temperature (TC) Military Supply Voltage (VEE) −65˚C to +150˚C +175˚C −7.0V to +0.5V VEE to +0.5V −100 mA −55˚C to +125˚C −5.7V to −4.2V Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Military Version DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C Symbol VOH Parameter Output HIGH Voltage Conditions Min Max Units TC −1025 −870 mV 0˚C to −1085 −870 mV −55˚C VIN = VIH (Max) Loading with −1830 −1620 mV 0˚C to or VIL (Min) 25Ω to −2.0V −1830 −1555 mV −55˚C −1035 mV 0˚C to −1085 mV −55˚C VIN = VIH (Min) Loading with −1610 mV 0˚C to or VIL (Max) 25Ω to −2.0V −1555 mV Notes +125˚C VOL Output LOW Voltage (Notes 4, 5, 6) +125˚C VOHC Output HIGH Voltage +125˚C VOLC Output LOW Voltage (Notes 4, 5, 6) +125˚C VOLZ Cutoff LOW Voltage −55˚C 0˚C to VIN = VIH (Min) mV +125˚C or VIL (Max) mV −55˚C to −1950 −1850 VIH Input HIGH Voltage −1165 −870 −55˚C +125˚C VIL Input LOW Voltage −1830 −1475 mV −55˚C to +125˚C IIL Input LOW Current 0.50 µA −55˚C to Input HIGH Current 240 340 IEE µA µA −205 −73 Guaranteed LOW Signal for All Inputs VEE = −4.2V mA (Notes 4, 5, 6, 7) (Notes 4, 5, 6, 7) (Notes 4, 5, 6, 7) 0˚C to +125˚C VIN = VIH (Max) (Notes 4, 5, 6) Inputs Open VEE = −4.2V to −4.8V VEE = −4.2V to −5.7V (Notes 4, 5, 6) −55˚C to −73 for All Inputs −55˚C Power Supply Current −195 Guaranteed HIGH Signal (Notes 4, 5, 6) VIN = VIL (Min) VEE = −5.7V +125˚C IIH OEN = HIGH +125˚C Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 5: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 6: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 7: Guaranteed by applying specified input condition and testing VOH/VOL. 3 www.national.com AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Dn to Output tPLH Propagation Delay tPHL LE, E to Output TC = −55˚C TC = +25˚C TC = +125˚C Min Max Min Max Min Max 0.50 2.60 0.70 2.60 0.70 3.10 ns Figures 1, 2 (Notes 8, 9, 10, 12) 0.80 3.30 1.00 3.30 1.10 3.80 ns Figures 1, 4 (Notes 8, 9, 10, 12) ns Figures 1, 2 (Notes 8, 9, 10, 12) ns Figures 1, 3 tPZH Propagation Delay 1.00 4.60 1.10 4.20 1.20 4.40 tPHZ OEN to Output 0.70 3.00 0.70 2.80 0.70 3.20 0.40 2.50 0.40 2.40 0.40 2.70 tTLH Transition Time tTHL 20% to 80%, 80% to 20% ts Setup Time th Units Conditions (Note 11) D0–D7 1.50 1.50 1.70 ns Figures 1, 3 D0–D7 0.60 0.60 0.60 ns Figures 1, 3 LE, E 2.40 2.40 2.40 ns Figures 1, 3 Hold Time tpw(H) Notes Pulse Width HIGH (Note 11) (Note 11) (Note 11) Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 9: Screen tested 100% on each device at +25˚C temperature only, Subgroup A9. Note 10: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11. Note 11: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data). Note 12: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching. Test Circuitry DS100317-6 Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 25Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit www.national.com 4 Switching Waveforms DS100317-7 FIGURE 2. Propagation Delay and Cutoff Times DS100317-8 FIGURE 3. Setup, Hold and Pulse Width Times DS100317-9 FIGURE 4. Propagation Delay LE, E to Q 5 www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) NS Package Number J24E 24-Lead Quad Cerpak (F) NS Package Number W24B 7 www.national.com 100344 Low Power 8-Bit Latch with Cut-Off Drivers LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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