AT27LV512A Features • • • • • • • • • • Fast Read Access Time - 90 ns Dual Voltage Range Operation Low Voltage Power Supply Range, 3.0V to 3.6V or Standard 5V ± 10% Supply Range Compatible with JEDEC Standard AT27C512 Low Power CMOS Operation 20 µA max. (less than 1 µA typical) Standby for VCC = 3.6V 29 mW max. Active at 5 MHz for VCC = 3.6V JEDEC Standard Packages 32-Lead PLCC 28-Lead 330-mil SOIC 28-Lead TSOP High Reliability CMOS Technology 2,000V ESD Protection 200 mA Latchup Immunity Rapid Programming Algorithm - 100 µs/byte (typical) CMOS and TTL Compatible Inputs and Outputs JEDEC Standard for LVTTL Integrated Product Identification Code Commercial and Industrial Temperature Ranges 512K (64K x 8) Low Voltage OTP CMOS EPROM Description The AT27LV512A is a high performance, low power, low voltage 524,288 bit one-time programmable read only memory (OTP EPROM) organized as 64K by 8 bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode operation, making it ideal for fast, portable systems using battery power. Atmel’s innovative design techniques provide fast speeds that rival 5V parts while keeping the low power consumption of a 3.3V supply. At VCC = 3.0V, any byte can be accessed in less than 90 ns. With a typical power dissipation of only 18 mW at 5 MHz and VCC = 3.3V, the AT27LV512A consumes less than one fifth the power of a standard 5V EPROM. (continued) Pin Configurations Pin Name Function A0 - A15 Addresses O0 - O7 Outputs CE Chip Enable OE/VPP Output Enable NC No Connect SOIC Top View AT27LV512A PLCC Top View TSOP Top View Type 1 Note: PLCC Package Pins 1 and 17 are DON’T CONNECT. 0607A 3-85 Description (Continued) System Considerations Standby mode supply current is typically less than 1 µA at 3.3V. Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. The AT27LV512A is available in industry standard JEDEC-approved one-time programmable (OTP) plastic PLCC, SOIC, and TSOP packages. All devices feature two-line control (CE, OE) to give designers the flexibility to prevent bus contention. The AT27LV512A operating with VCC at 3.0V produces TTL level outputs that are compatible with standard TTL logic devices operating at VCC = 5.0V. The device is also capable of standard 5-volt operation making it ideally suited for dual supply range systems or card products that are pluggable in both 3-volt and 5-volt hosts. Atmel’s AT27LV512A has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper programming algorithms and voltages. The AT27LV512A programs exactly the same way as a standard 5V AT27C512R and uses the same programming equipment. 3-86 AT27LV512A AT27LV512A Absolute Maximum Ratings* Block Diagram Temperature Under Bias .................. -40°C to +85°C Storage Temperature...................... -65°C to +125°C Voltage on Any Pin with Respect to Ground......................... -2.0V to +7.0V (1) Voltage on A9 with Respect to Ground ...................... -2.0V to +14.0V (1) VPP Supply Voltage with Respect to Ground....................... -2.0V to +14.0V (1) *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V dc which may undershoot to 2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V dc which may be exceeded if certain precautions are observed (consult application notes) and which may overshoot to +7.0 volts for pulses of less than 20 ns. Operating Modes Mode \ Pin Read (2) Output Rapid PGM VIL Disable (2) Standby CE (2) Program (3) Inhibit (3) VIL VIH VIL VIH OE/VPP VIL VIH X VPP VPP Ai VCC Ai X (1) X Ai X Outputs VCC (2) DOUT VCC (2) High Z VCC (2) High Z VCC (3) DIN VCC (3) High Z (4) Product Identification (3, 5) VIL VIL Notes: 1. X can be VIL or VIH. 2. Read, output disable, and standby modes require, 3.0V ≤ VCC ≤ 3.6V, or 4.5V ≤ VCC ≤ 5.5V. 3. Refer to Programming Characteristics. Programming modes require VCC = 6.5V. A9 = VH A0 = VIH or VIL A1 - A15 = VIL VCC (3) Identification Code 4. VH = 12.0 ± 0.5V. 5. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte. 3-87 DC and AC Operating Conditions for Read Operation AT27LV512A Operating Temperature (Case) Com. Ind. VCC Power Supply -90 -12 -15 0°C - 70°C 0°C - 70°C 0°C - 70°C -40°C - 85°C -40°C - 85°C -40°C - 85°C 3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 5V ± 10% 5V ± 10% 5V ± 10% DC and Operating Characteristics for Read Operation Symbol Parameter Condition Min Max Units VCC = 3.0V to 3.6V ILI ILO IPP1 (2) Input Load Current VIN = 0V to VCC ±1 µA Output Leakage Current VOUT = 0V to VCC ±5 µA VPP = VCC 10 µA ISB1 (CMOS), CE = VCC ± 0.3V 20 µA ISB2 (TTL), CE = 2.0 to VCC + 0.5V 100 µA 8 mA VPP (1) Read/Standby Current VCC (1) Standby Current ISB f = 5 MHz, IOUT = 0 mA, CE = VIL ICC VCC Active Current VIL Input Low Voltage -0.6 0.8 V VIH Input High Voltage 2.0 VCC + 0 .5 V VOL Output Low Voltage IOL = 2.0 mA 0.4 V VOH Output High Voltage IOH = -2.0 mA 2.4 V VCC = 4.5V to 5.5V ILI ILO IPP1 (2) Input Load Current VIN = 0V to VCC ±1 µA Output Leakage Current VOUT = 0V to VCC ±5 µA VPP = VCC 10 µA ISB1 (CMOS), CE = VCC ± 0.3V 100 µA ISB2 (TTL), CE = 2.0 to VCC + 0.5V 1 mA f = 5 MHz, IOUT = 0 mA, CE = VIL 20 mA VPP (1) Read/Standby Current ISB VCC (1) Standby Current ICC VCC Active Current VIL Input Low Voltage -0.6 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VOL Output Low Voltage IOL = 2.1 mA 0.4 V VOH Output High Voltage IOH = -400 µA Note: 3-88 2.4 1. VCC must be applied simultaneously with or before OE/VPP, and removed simultaneously with or after OE/VPP. AT27LV512A V AT27LV512A AC Characteristics for Read Operation (VCC = 3.0V to 3.6V and 4.5V to 5.5V) -90 Symbol tACC (3) Parameter Condition Min -12 Max Min -15 Max Min Max Units Address to Output Delay CE = OE/VPP = VIL 90 120 150 ns tCE (2) CE to Output Delay OE/VPP = VIL 90 120 150 ns tOE (2, 3) OE/VPP to Output Delay CE = VIL 50 50 60 ns 40 40 50 ns tDF (4, 5) OE/VPP or CE High to Output Float, whichever occurred first tOH Output Hold from Address, CE or OE/VPP, whichever occurred first Notes: 0 0 0 ns 2, 3, 4, 5. - see AC Waveforms for Read Operation. AC Waveforms for Read Operation (1) Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified. 2. OE/VPP may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE. 3. OE/VPP may be delayed up to tACC - tOE after the address is valid without impact on tACC. 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as the point when data is no longer driven. 3-89 Output Test Load Input Test Waveform and Measurement Level tR, tF < 20 ns (10% to 90%) Note: CL = 100 pF including jig capacitance. Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ Max Units CIN 4 6 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note: 3-90 Conditions 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. AT27LV512A AT27LV512A Programming Waveforms (1) Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. DC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, OE/VPP = 13.0 ± 0.25V Limits Symbol Parameter Test Conditions ILI Input Load Current VIN = VIL, VIH VIL Input Low Level VIH Input High Level VOL Output Low Voltage IOL = 2.1 mA VOH Output High Voltage IOH = -400 µA ICC2 VCC Supply Current (Program and Verify) IPP2 OE/VPP Current VID A9 Product Identification Voltage Min Max Units 10 µA -0.6 0.8 V 2.0 VCC + 0.5 V 0.4 V 2.4 CE = VIL 11.5 V 25 mA 25 mA 12.5 V 3-91 AC Programming Characteristics Rapid Programming Algorithm TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, OE/VPP = 13.0 ± 0.25V A 100 µs CE pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and OE/VPP is raised to 13.0V. Each address is first programmed with one 100 µs CE pulse without verification. Then a verification / reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. OE/VPP is then lowered to VIL and VCC to 5.0V. All bytes are read again and compared with the original data to determine if the device passes or fails. Symbol Parameter Test Conditions* (1) Limits Min Max Units Address Setup Time 2 µs tOES OE/VPP Setup Time 2 µs tOEH OE/VPP Hold Time 2 µs tDS Data Setup Time 2 µs tAH Address Hold Time 0 µs tDH Data Hold Time 2 µs tDFP CE High to Output Float Delay (2) 0 tAS tVCS VCC Setup Time tPW 130 µs 2 CE Program Pulse Width (3) ns 95 (2) 105 µs 1 µs tDV Data Valid from CE tVR OE/VPP Recovery Time 2 µs tPRT OE/VPP Pulse Rise Time During Programming 50 ns *AC Conditions of Test: Input Rise and Fall Times (10% to 90%).............20 ns Input Pulse Levels..................................0.45V to 2.4V Input Timing Reference Level.................0.8V to 2.0V Output Timing Reference Level..............0.8V to 2.0V Notes: 1. VCC must be applied simultaneously or before OE/VPP and removed simultaneously or after OE/VPP. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven —see timing diagram. 3. Program Pulse width tolerance is 100 µsec ± 5%. Atmel’s 27LV512A Integrated Product Identification Code (1) Pins Codes Manufacturer Device Type Note: 3-92 A0 O7 O6 O5 O4 O3 O2 O1 O0 0 1 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 Hex Data 1E 0D 1. The AT27LV512A has the same Product Identification Code as the AT27C512R. Both are programming compatible. AT27LV512A AT27LV512A Ordering Information ICC (mA) tACC (ns) Active Standby 90 8 120 150 Ordering Code Package Operation Range 0.02 AT27LV512A-90JC AT27LV512A-90RC AT27LV512A-90TC 32J 28R 28T Commercial (0°C to 70°C) 8 0.02 AT27LV512A-90JI AT27LV512A-90RI AT27LV512A-90TI 32J 28R 28T Industrial (-40°C to 85°C) 8 0.02 AT27LV512A-12JC AT27LV512A-12RC AT27LV512A-12TC 32J 28R 28T Commercial (0°C to 70°C) 8 0.02 AT27LV512A-12JI AT27LV512A-12RI AT27LV512A-12TI 32J 28R 28T Industrial (-40°C to 85°C) 8 0.02 AT27LV512A-15JC AT27LV512A-15RC AT27LV512A-15TC 32J 28R 28T Commercial (0°C to 70°C) 8 0.02 AT27LV512A-15JI AT27LV512A-15RI AT27LV512A-15TI 32J 28R 28T Industrial (-40°C to 85°C) Package Type 32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 28R 28 Lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28 Lead, Thin Small Outline Package (TSOP) 3-93