Features • Single 2.7V - 3.6V Supply • Fast Read Access Time – 200 ns • Automatic Page Write Operation • • • • • • • • – Internal Address and Data Latches for 64 Bytes – Internal Control Timer Fast Write Cycle Times – Page Write Cycle Time: 10 ms Maximum – 1- to 64-byte Page Write Operation Low Power Dissipation – 15 mA Active Current – 20 µA CMOS Standby Current Hardware and Software Data Protection Data Polling for End of Write Detection High Reliability CMOS Technology – Endurance: 10,000 Cycles – Data Retention: 10 Years JEDEC Approved Byte-wide Pinout Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Option 256K (32K x 8) Battery-Voltage Parallel EEPROMs AT28BV256 1. Description The AT28BV256 is a high-performance electrically erasable and programmable readonly memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 200 µA. The AT28BV256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by Data polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s AT28BV256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 0273J–PEEPR–10/06 2. Pin Configurations 2.2 Pin Name Function A0 - A14 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 32-lead PLCC – Top View 2.3 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 A8 A9 A11 NC OE A10 CE I/O7 I/O6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 28-lead TSOP – Top View OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 I/O1 I/O2 GND DC I/O3 I/O4 I/O5 A6 A5 A4 A3 A2 A1 A0 NC I/O0 4 3 2 1 32 31 30 A7 A12 A14 DC VCC WE A13 2.1 28-lead PDIP, SOIC – Top View Note: 2 1. PLCC package pins 1 and 17 are Don’t Connect. AT28BV256 0273J–PEEPR–10/06 AT28BV256 3. Block Diagram 4. Absolute Maximum Ratings* Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V 3 0273J–PEEPR–10/06 5. Device Operation 5.1 Read The AT28BV256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. 5.2 Byte Write A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. 5.3 Page Write The page write operation of the AT28BV256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28BV256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. For each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 5.4 Data Polling The AT28BV256 features Data Polling to indicate the end of a write cycle. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. Data Polling may begin at anytime during the write cycle. 5.5 Toggle Bit In addition to Data Polling, the AT28BV256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. 5.6 Data Protection If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel® has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4 AT28BV256 0273J–PEEPR–10/06 AT28BV256 5.6.1 Hardware Protection Hardware features protect against inadvertent writes to the AT28BV256 in the following ways: (a) VCC power-on delay – once VCC has reached 1.8V (typical) the device will automatically time out 10 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. 5.6.2 Software Data Protection A software-controlled data protection feature has been implemented on the AT28BV256. Software data protection (SDP) helps prevent inadvertent writes from corrupting the data in the device. SDP can prevent inadvertent writes during power-up and power-down as well as any other potential periods of system instability. The AT28BV256 can only be written using the software data protection feature. A series of three write commands to specific addresses with specific data must be presented to the device before writing in the byte or page mode. The same three write commands must begin each write operation. All software write commands must obey the page mode write timing specifications. The data in the 3-byte command sequence is not written to the device; the address in the command sequence can be utilized just like any other location in the device. Any attempt to write to the device without the 3-byte sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. 5.7 Device Identification An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. 5 0273J–PEEPR–10/06 6. DC and AC Operating Range AT28BV256-20 Operating Temperature (Case) -40°C - 85°C VCC Power Supply 2.7V - 3.6V 7. Operating Modes Mode CE OE WE I/O Read VIL VIL VIH DOUT Write(2) VIL VIH VIL DIN X High Z Standby/Write Inhibit (1) VIH X Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X High Z VIL High Z Chip Erase Notes: VIL VH (3) 1. X can be VIL or VIH. 2. Refer to AC programming waveforms. 3. VH = 12.0V ± 0.5V. 8. DC Characteristics Symbol Parameter Condition ILI Input Load Current ILO Max Units VIN = 0V to VCC + 1V 10 µA Output Leakage Current VI/O = 0V to VCC 10 µA ISB VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V 50 µA ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 15 mA VIL Input Low Voltage 0.6 V VIH Input High Voltage VOL Output Low Voltage IOL = 1.6 mA VOH Output High Voltage IOH = -100 µA 6 Min 2.0 V 0.3 2.0 V V AT28BV256 0273J–PEEPR–10/06 AT28BV256 9. AC Read Characteristics AT28BV256-20 Symbol Parameter tACC Min Max Units Address to Output Delay 200 ns (1) CE to Output Delay 200 ns tOE(2) OE to Output Delay 0 80 ns tDF(3)(4) CE or OE to Output Float 0 55 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 tCE ns 10. AC Read Waveforms(1)(2)(3)(4) tCE tOE tDF tACC Notes: tOH 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 7 0273J–PEEPR–10/06 11. Input Test Waveforms and Measurement Level tR, tF < 20 ns 12. Output Test Load 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol Typ Max Units Conditions CIN 4 6 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note: 8 1. This parameter is characterized and is not 100% tested. AT28BV256 0273J–PEEPR–10/06 AT28BV256 14. AC Write Characteristics Symbol Parameter tAS, tOES Address, OE Set-up Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Set-up Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 200 ns tDS Data Set-up Time 50 ns tDH, tOEH Data, OE Hold Time 0 ns tDV Time to Data Valid Note: Min Max Units NR(1) 1. NR = No Restriction. 15. AC Write Waveforms 15.1 WE Controlled tOES tAS tOEH tAH tCH tCS tWPH tWP tDV 15.2 tDH tDS CE Controlled tOES tAS tOEH tAH tCH tCS tWPH tWP tDV tDS tDH 9 0273J–PEEPR–10/06 16. Page Mode Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 200 ns tBLC Byte Load Cycle Time tWPH Write Pulse Width High 150 100 µs ns 17. Programming Algorithm(1)(2)(3) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(3) LOAD LAST BYTE TO LAST ADDRESS(3) Notes: ENTER DATA PROTECT STATE 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Data protect state will be re-activated at the end of program cycle. 3. 1 to 64 bytes of data are loaded. 18. Software Protected Program Cycle Waveforms(1)(2)(3) tWP tAS tAH tWPH tBLC tDH tDS tWC Notes: 1. A0 - A14 must conform to the addressing sequence for the first three bytes as shown above. 2. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 3. OE must be high only when WE and CE are both low. 10 AT28BV256 0273J–PEEPR–10/06 AT28BV256 19. Data Polling Characteristics(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time Min Max OE to Output Delay tWR Write Recovery Time Units 0 ns 0 ns (2) tOE Notes: Typ ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 7. 20. Data Polling Waveforms tOEH tDH tWR tOE 21. Toggle Bit Characteristics(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time Min OE to Output Delay tOEHP OE High Pulse tWR Max Units 10 ns 10 ns (2) tOE Notes: Typ ns Write Recovery Time 150 ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 7. 22. Toggle Bit Waveforms tOEH tDH tOE tWR Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 11 0273J–PEEPR–10/06 23. Normalized ICC Graphs 12 AT28BV256 0273J–PEEPR–10/06 AT28BV256 24. Ordering Information 25. Standard Package tACC (ns) ICC (mA) Active 200 Note: Standby Ordering Code Package Operation Range 0.02 AT28BV256-20JI AT28BV256-20PI AT28BV256-20SI AT28BV256-20TI 32J 28P6 28S 28T Industrial (-40° to 85° C) 15 1. See Valid Part Numbers table below. 26. Green Package Option (Pb/Halide-free) tACC (ns) ICC (mA) Active 200 15 Standby Ordering Code Package Operation Range 0.02 AT28BV256-20JU AT28BV256-20TU AT28BV256-20SU AT28BV256-20PU 32J 28T 27S 28T Industrial (-40° to 85° C) 27. Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers AT28BV256 Speed 20 Package and Temperature Combinations JI, PI, SI, TI, TU, JU, SU, PU 28. Die Products Reference Section: Parallel EEPROM Die Products Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) 13 0273J–PEEPR–10/06 29. Packaging Information 29.1 32J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) D2 Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 14 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 32J B AT28BV256 0273J–PEEPR–10/06 AT28BV256 29.2 28P6 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – D 36.703 – 37.338 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AB. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). e NOTE Note 2 Note 2 2.540 TYP 09/28/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P6 REV. B 15 0273J–PEEPR–10/06 29.3 28S – SOIC Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 0.51(0.020) 0.33(0.013) 7.60(0.2992) 10.65(0.419) 7.40(0.2914) 10.00(0.394) PIN 1 1.27(0.50) BSC TOP VIEW 18.10(0.7125) 17.70(0.6969) 2.65(0.1043) 2.35(0.0926) 0.30(0.0118) 0.10(0.0040) SIDE VIEWS 0.32(0.0125) 0.23(0.0091) 0º ~ 8º 1.27(0.050) 0.40(0.016) 8/4/03 R 16 2325 Orchard Parkway San Jose, CA 95131 TITLE 28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) JEDEC Standard MS-013 DRAWING NO. REV. 28S B AT28BV256 0273J–PEEPR–10/06 AT28BV256 29.4 28T – TSOP PIN 1 0º ~ 5º c Pin 1 Identifier Area D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 D 13.20 13.40 13.60 D1 11.70 11.80 11.90 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. L1 NOTE 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.55 BASIC 12/06/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. REV. 28T C 17 0273J–PEEPR–10/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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