AV9107C-13 Integrated Circuit Systems, Inc. CPU Frequency Generator General Description The AV9107C-13 offers a tiny footprint solution for generating two simultaneous clocks. The AV9107C-13 uses a 20 MHz crystal to generate two PLL synthesis outputs of 20 and 40 MHz. The Output enable pin will tristate the 40 MHz output when low (maintaining the 20 MHz output runing in both logic levels). The power pin takes the device to a low current condition, shutting off the PLL and forcing both outputs low, when the PD# pin is low. There is a built-in pull-up on both the OE and PD# inputs. Features Patented on-chip Phase-Locked Loop with VCO for clock generation Provides two synthesized clocks Generates 20 and 40 MHz output frequencies. On-chip loop filter Low power CMOS technology Single +3.3 or +5 volt power supply 8-pin SOIC package The device has advanced features which include on-chip loop filters, tristate outputs, and power-down capability. A minimum of external components - two decoupling capacitors and an optional ferrite bead - are all that are required for jitterfree operation. Pin Configuration Block Diagram Note: Crystal is 20 MHz AV 9107-13 RevB052197 AV9107C-13 Functionality (at 14.318) MHz reference frequency input) OE CLK1 CLK2 0 20 MHz Tristate 1 20 MHz 40 MHz Pin Descriptions PIN NUMBER PIN NAME TYPE 1 OE Input 2 GND PWR Ground. 3 X1/CLK0 Input Crystal Input or Input Clock frequency. Typically 20MHz crystal. DESCRIPTION Output Enable - Tristates the 40 MHz output when low. Pull-Up 4 X2 5 PD# Output Crystal Output (No Connect when clock used.). 6 CLK1 7 VDD PWR Digital power supply (+5V DC). 8 CLK2 Output Clock2 output, divided by 2 from clock1 output, for 20MHz with 20MHz crystal. Output is synthesized. Input Power Down. Shuts off chip when low outputs are driven low. Internall pull-up. Output Clock 1 output 40MHz with 20MHz crystal. Frequency Accuracy and Calculation Allowable Input and Output Frequencies The accuracy of the frequencies produced by the AV9107C depends on the input frequency and the desired actual output frequency. The formula for calculating the exact output frequency is as follows: Output Frequency = Input Frequency X The input frequency should be between 12 and 40 MHz and the A/B ratio should not exceed 24. The output should fall in the range of 12 to 80 MHz for CLK1 dnd CLK2. (See specification for 3.3V and 5V condition details). A B Output Enable The Output Enable feature tristates the CLK1 output clock pin. This places the selected output pins in a high inpedance state to allow for system level diagnostic testing. The divideby-2 output of CLK2 remains active on the AV9107C-13 for any OE state. Where A = 2, 3, 4 ... 128, and B = 2, 3, 4 ...32. For example, to calculate the actual output frequency for a video monitor expecting a 44.900 MHz clock and using a 14.318 MHz input clock, the closest A/B ratio is 69/22, which gives an output of 44.906 MHz (within 0.02% of the target frequency). Generally, the AV9107 can produce frequencies within 0.1% of the desired output. Power Down The power down pin shuts off the entire chip to save current. A few milliseconds are required to reach full functioning speed from a power down state. 2 AV9107C-13 Absolute Maximum Ratings AVDD, VDD referenced to GND . . . . . . . . . . . . . . . 7V Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 5.0V Operating VDD = +4.5V to +5.5V; TA =0°C to 70°C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - - 0.8 V Input Low Voltage VIL Input High Voltage VIH 2.0 - - V Input Low Current IIL VIN=0V - 6.0 16.0 µA VIN=VDD Input High Current IIH 2.0 - 2.0 µA Output Low Voltage VOL IOL=10mA - 0.25 0.40 V Output High Voltage, Note 1 VOH IOH=-30mA 2.4 3.25 - V Output Low Current, Note 1 IOL VOL=0.8V 22.0 35.0 - mA Output High Current, Note 1 IOH VOH=2.0V - -50.0 -35.0 mA Supply Current IDD No load - 18.0 40.0 mA Fd With respect to typical frequency Note 1 - 0.002 0.05 % Note 2 - 12.0 50.0 µA VIN = VDD -1V - 380.0 800.0 k ohms Output Frequency Change over Supply and Temperature Stand by Supply Current IDDSTDBY Pull-up Resistor, Note 1 Rpu AC Characteristics Output Rise Time 0.8 to 2.0V, Note 1 Tr 15pF load - 0.65 1.60 ns Output Fall Time 2.0 to 0.8V, Note 1 Tf 15pF load - 0.55 1.2 ns Rise Time 20% to 80% VDD, Note 1 Tr 15pF load - 1.5 3.5 ns Fall Time 80% to 20% VDD, Note 1 Tf 15pF load - 1.1 2.2 ns Duty Cycle, Note 1 Dt 15pF load 45.0 - 55.0 % Jitter, One Sigma, Note 1 Tjis 10,000 samples - 40.0 120.0 ps Jitter, Absolute, Notes 1, 3 Tjab 10,000 samples -500.0 200 500.0 ps Input Frequency, Note 1 Fi Output Frequency, Note 1 Fo Power-up Time, Note 1 Tpu Note 1: Note2: Note3: Clock1 14 20 40 MHz 28 40 80 MHz - 130 300 µs Parameter is guaranteed by design and characterization. Not 100% tested in production. AV9107C-13 with the power down pin low (active). Absolute jitter measured as the shortest and longest period difference to the mean period of the sample set. 3 AV9107C-13 Electrical Characteristics at 3.3V Operating VDD = +3.0V to +3.7V; TA =0°C to 70°C unless otherwise stated DC Characteristics MIN TYP MAX Input Low Voltage PARAMETER SYMBOL VIL TEST CONDITIONS - - 0.20VDD UNITS V Input High Voltage VIH 0.7VDD - - V Input Low Current, Note1 IIL VIN=0V - 2.5 7.0 µA Input High Current, Note 1 IIH VIN=VDD -2.0 - 2.0 µA Output Low Voltage, Note 1 VOL IOL=6mA - 0.15 0.1xVDD V Output High Voltage, Note 1 VOH IOH=-5mA 0.85xVDD 0.92xVDD - V Output Low Current, Note 1 IOL VOL=0.2VDD 15.0 22.0 - mA Output High Current, Note 1 IOH VOL=0.7VDD - -17.0 -10.0 mA Supply Current, Note 1 IDD Unloaded - 11.0 25.0 mA Standby Supply Current, Notes 1, 2 IDDSTDBY - 13.0 40.0 µA Output Frequency Change over Supply and Temperature, Note1 Fd With respect to typical frequency - 0.002 0.01 % Pull-up Resistor, Note 1 Rpu VIN = VDD - 0.5V - 0.55 1.0 M ohms AC Characteristics Rise Time 20% to 80% VDD, Note 1 Tr 15pF load - 2.0 3.4 ns Fall Time 80% to 20% VDD, Note 1 Tf 15pF load - 1.2 2.2 ns Duty Cycle, Note 1 Dt 15pF load @ 50% 42 - 52 % Jitter, One Sigma, Note 1 Tjis 10,000 samples - 40.0 120.0 ps Jitter, Absolute, Notes 1, 3 Tjab 10,000 samples 500.0 200 500.0 ps 12 20 25 MHz Input Frequency, Note 1 Fi Output Frequency, Note 1 Fo Power-up Time, Note 1 Tpu Note 1: Note2: Note3: Clock1 24 40 50 MHz - 265 500 µs Parameter is guaranteed by design and characterization. Not 100% tested in production. AV9107C-13 with the power down pin low (active). Absolute jitter measured as the shortest and longest period difference to the mean period of the sample set. 4 AV9107C-13 8-Pin Plastic SOIC Package Ordering Information AV9107C-13CS08 Example: XXX XXXX-PPP M X#W Lead Count & Package Width Lead Count=1, 2 or 3 digits W=.3 SOIC or .6 DIP; None=Standard Width Package Type S=SOIC Pattern Number (2 or 3 digit number for parts with ROM code patterns, if applicable) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 5