Revised August 2001 74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. ■ Compatible with PC100 DIMM module specifications Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Ouputs (O n) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The 74VCX16835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74VCX16835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 1.65V–3.6V VCC supply operation ■ 3.6V tolerant inputs and outputs ■ tPD (CLK to O n) 4.2ns max for 3.0V to 3.6V VCC 5.2ns max for 2.3V to 2.7V VCC 9.2ns max for 1.65V to 1.95V VCC ■ Power-down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ Static Drive (IOH/IOL) ±24mA @ 3.0V ±18mA @ 2.3V ±6mA @ 1.65V ■ Latchup performance exceeds 300 mA ■ ESD performance: Human body model > 2000V Machine model >200V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC (OE to GND) through a pulldown resistor; the minimum value of the resistor is determined by the current sourcing capability of the driver. Ordering Code: Order Number 74VCX16835GX (Note 2) 74VCX16835MTD (Note 3) Package Number BGA54A (Preliminary) MTD56 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS500173 www.fairchildsemi.com 74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs October 1998 74VCX16835 Connection Diagrams Pin Descriptions Pin Names Pin Assignment for TSSOP Description OE Output Enable Input (Active LOW) LE Latch Enable Input CLK Clock Input I1 - I18 Data Inputs O1 - O18 3-STATE Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O2 O1 NC GND I1 I2 B O4 O3 NC NC I3 I4 C O6 O5 VCC VCC I5 I6 D O8 O7 GND GND I7 I8 E O10 O9 GND GND I9 I10 F O12 O11 GND GND I11 I12 G O14 O13 VCC VCC I13 I14 H O16 O15 OE CLK I15 I16 J O17 O18 LE GND I18 I17 Truth Table Inputs Pin Assignment for FBGA Outputs OE LE CLK In On H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H L L H X O0 (Note 4) L L L X O0 (Note 5) H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance ↑ = LOW-to-HIGH Clock Transition Note 4: Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 5: Output level before the indicated steady-state input conditions were established. (Top Thru View) www.fairchildsemi.com 2 74VCX16835 Logic Diagram 3 www.fairchildsemi.com 74VCX16835 Absolute Maximum Ratings(Note 6) Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Recommended Operating Conditions (Note 8) Power Supply Output Voltage (VO) Operating −0.5V to +4.6V Outputs 3-STATE Outputs Active (Note 7) DC Input Diode Current (IIK) VI < 0V −0.5 to VCC + 0.5V −50 mA −50 mA VO > VCC +50 mA Output Voltage (VO) ±50 mA Storage Temperature Range (TSTG) 0V to VCC 0V to 3.6V VCC = 3.0V to 3.6V ±24 mA VCC = 2.3V to 2.7V ±18 mA VCC = 1.65V to 2.3V DC VCC or Ground Current per Supply Pin (ICC or Ground) Output in Active States Output in 3-STATE Output Current in IOH/IOL DC Output Source/Sink Current (IOH/IOL) 1.2V to 3.6V −0.3V to 3.6V Input Voltage DC Output Diode Current (IOK) VO < 0V 1.65V to 3.6V Data Retention Only ±100 mA ±6 mA Free Air Operating Temperature (TA) −65°C to +150 °C −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 6: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation. Note 7: IO Absolute Maximum Rating must be observed. Note 8: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW. DC Electrical Characteristics (2.7V < VCC ≤ 3.6V) Symbol Parameter Conditions VCC (V) VIH HIGH Level Input Voltage 2.7–3.6 VIL LOW Level Input Voltage 2.7–3.6 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage VCC − 0.2 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 2.2 IOH = −24 mA 3.0 2.7–3.6 0.2 IOL = 12 mA 2.7 0.4 IOL = 18 mA 3.0 0.4 0V ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0V ≤ VO ≤ 3.6V VI = VIH or VIL IOFF Power Off Leakage Current 0V ≤ (VI, VO) ≤ 3.6V ICC Quiescent Supply Current VI = VCC or GND VCC ≤ (VI, VO) ≤ 3.6V (Note 9) VIH = VCC − 0.6V www.fairchildsemi.com 4 V 3.0 0.55 2.7–3.6 ±5.0 µA 2.7–3.6 ±10 µA 0 10 µA 2.7–3.6 2.7–3.6 Note 9: Outputs disabled or 3-STATE only. V V IOL = 100 µA IOL = 24 mA Units V 0.8 2.7–3.6 Input Leakage Current Increase in ICC per Input Max 2.0 IOH = −100 µA II ∆ICC Min 20 ±20 750 µA µA Symbol Parameter VCC Conditions (V) VIH HIGH Level Input Voltage 2.3 - 2.7 VIL LOW Level Input Voltage 2.3 - 2.7 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage IOH = −100 µA Min Max 1.6 V 0.7 2.3 -2.7 VCC − 0.2 IOH = −6 mA 2.3 2.0 IOH = −12 mA 2.3 1.8 IOH = −18 mA 2.3 1.7 Units V V IOL = 100 µA 2.3 - 2.7 IOL = 12mA 2.3 0.4 IOL = 18 mA 2.3 0.6 2.3 - 2.7 ±5.0 µA 2.3 - 2.7 ±10 µA µA II Input Leakage Current 0V ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0V ≤ VO ≤ 3.6V VI = V IH or VIL 0.2 IOFF Power Off Leakage Current 0V ≤ (VI, VO) ≤ 3.6V 0 10 ICC Quiescent Supply Current VI = V CC or GND 2.3 - 2.7 20 VCC ≤ (VI, VO) ≤ 3.6V (Note 10) 2.3 - 2.7 ±20 V µA Note 10: Outputs disabled or 3-STATE only. DC Electrical Characteristics (1.65V ≤ VCC < 2.3V) Symbol Parameter Conditions VCC (V) VIH HIGH Level Input Voltage 1.65 - 2.3 VIL LOW Level Input Voltage 1.65 - 2.3 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage IOH = −100 µA Min Max 0.65 × VCC V 0.35 × V CC 1.65 - 2.3 VCC − 0.2 IOH = −6 mA 1.65 1.25 IOL = 100 µA 1.65 - 2.3 0.2 1.65 0.3 IOL = 6mA II Input Leakage Current 0V ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0V ≤ VO ≤ 3.6V IOFF Power Off Leakage Current 0V ≤ (VI, VO) ≤ 3.6V ICC Quiescent Supply Current VI = V CC or GND VI = V IH or VIL VCC ≤ (VI, VO) ≤ 3.6V (Note 11) Units V V V 1.65 - 2.3 ±5.0 µA 1.65 - 2.3 ±10 µA 0 10 µA 1.65 - 2.3 20 ±20 µA Note 11: Outputs disabled or 3-STATE only. 5 www.fairchildsemi.com 74VCX16835 DC Electrical Characteristics (2.3V ≤ VCC ≤ 2.7V) 74VCX16835 AC Electrical Characteristics (Note 12) TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω Symbol Parameter VCC = 3.3V ± 0.3V Min Max 250 VCC = 2.5 ± 0.2V VCC = 1.8 ± 0.15V Min Min Max 200 Units Max fMAX Maximum Clock Frequency tPHL, Propagation Delay 100 MHz tPLH Bus to Bus tPHL, Propagation Delay tPLH Clock to Bus tPHL, Propagation Delay tPLH LE to Bus 0.6 3.8 0.8 4.9 1.5 9.8 ns tPZL, tPZH Output Enable Time 0.6 3.8 0.8 4.9 1.5 9.8 ns tPLZ, tPHZ Output Disable Time 0.6 3.9 0.8 4.5 1.5 7.6 ns tS Setup Time 1.5 1.5 2.5 ns tH Hold Time 0.7 0.7 1.0 ns tW Pulse Width 1.5 1.5 4.0 ns tOSHL Output to Output Skew tOSLH (Note 13) 0.6 3.3 0.8 4.2 1.5 8.4 ns 1.4 4.2 1.5 5.2 2.0 9.2 ns 0.5 0.5 0.75 ns Note 12: For CL=50pF, add approximately 300ps to the AC maximum specification. Note 13: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). AC Electrical Characteristics Over Load (Note 14) TA = −0°C to +85°C, RL = 500Ω VCC = 3.3V ± 0.15V Symbol CL = 0 pF Parameter CL = 50 pF Units Min Max Min Max tPHL, tPLH Propagation Delay Bus to Bus 0.7 2.1 1.0 3.6 ns tPHL, tPLH Propagation Delay Clock to Bus 1.5 3.0 1.7 4.5 ns tPHL, tPLH Propagation Delay LE to Bus 0.7 2.6 1.0 4.1 ns tPZL, tPZH Output Enable Time 0.7 2.6 1.0 4.1 ns tPLZ, tPHZ Output Disable Time 0.7 2.7 1.0 4.2 tPHL, tPLH SSO Prop Delay Clock to Bus (Note 15) 1.5 3.3 tS Setup Time 1.5 1.5 ns tH Hold Time 0.7 0.7 ns ns ns Note 14: This parameter is guaranteed by characterization but not tested. Note 15: SSO = Simultaneous Switching Output. Any output combination of LOW-to-HIGH and/or HIGH-to-LOW transition. Dynamic Switching Characteristics Symbol VOLP VOLV VOHV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Quiet Output Dynamic Valley VOH www.fairchildsemi.com Conditions CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V 6 VCC TA=+25°C (V) Typical 1.8 0.35 2.5 0.7 3.3 0.9 1.8 −0.35 2.5 −0.7 3.3 −0.9 1.8 1.3 2.5 1.7 3.3 2.0 Units V V V Symbol Parameter Conditions TA = +25°C Typical Units CIN Input Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V, or 3.3V, 3.5 pF CI/O Input/Output Capacitance VI = 0V, or VCC, VCC = 1.8V, 2.5V or 3.3V 5.5 pF CPD Power Dissipation Capacitance VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V 13 pF IOUT - VOUT Characteristics IOH versus VOH FIGURE 1. Characteristics for Output - Pull Up Driver IOL versus VOL FIGURE 2. Characteristics for Output - Pull Down Driver 7 www.fairchildsemi.com 74VCX16835 Capacitance 74VCX16835 AC Loading and Waveforms FIGURE 3. AC Test Circuit TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V; VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V to ± 0.15V tPZH, tPHZ GND FIGURE 5. 3-STATE Output High Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0ns, 10% to 90% FIGURE 4. Waveform for Inverting and Non-inverting Functions tr = tf ≤ 2.0ns, 10% to 90% FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0ns, 10% to 90% Symbol www.fairchildsemi.com VCC 3.3V ± 0.3V 2.5V ± 0.2V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 Vx VOL + 0.3V VOL + 0.15V VOL + 0.15V Vy VOH − 0.3V VOH − 0.15V VOH − 0.15V 8 1.8 ± 0.15V 74VCX16835 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary 9 www.fairchildsemi.com 74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10