AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 5-Port Gigabit Ethernet Switch with Embedded Memory Document No.: AX88655-1.0 / V1.0 / Mar, 12,2002 Features • • • • • • • • • 5-Port Gigabit Ethernet switch integrating MACs, packet buffer memory and switching engine with GMII/MII interface Full Duplex 1000 Mbit/s. Full and Half Duplex 10/100 Mbit/s Supports auto-sensing or manual selection for speed and duplex capability with an embedded MPU Store-and-forward operation support Performs full wire-speed switching with no HOL blocking Broadcast storm control Quality-of-Service provisioning on 802.1P tag and port-pairs with two priority queues Embedded 128K Byte SRAM for packet buffer • • • • • • • • • • Integrated two-way Address-Lookup engine and table for 4K MAC addresses Programmable aging mechanism for the two-way 4K MAC addresses table Full-duplex IEEE 802.3x flow control Half-duplex back pressure flow control Port trunking for high-bandwidth links Provides 5 GPIO ports Provides EEPROM interface for auto-configuration System clock input is one 27MHz Crystal and one 125MHz Oscillator 2.5 and 3.3V operations 3.3 I/Os and packaged in 256-pin PQFP Product Description The AX88655 is a 5-Port 10/100/1000 Mbps Ethernet switch with GMII or MII Interface. The switch controller provides network system manufacturers the ideal platform for building smart and cost-effective backbone switches for small to medium sized businesses. The AX88655 5-Port 10/100/100 BASE-T single chip switch controllers combine the benefits of network simplicity, flexibility and high integration. Its highly integrated feature set enables network system manufacturers to build smart switches for the fast-growing small to medium business market segment. Benefits of AX88655 Switches are below. Ø Simplicity Provides a smart, simple and low maintenance plug-and-play network interconnect system for small to medium size businesses Ø Flexibility Highly scalable configuration allows system manufacturers to enable or disable a range of features to best meet their target price point Ø Integration Highly integrated design drives down overall switch manufacturing costs. Target Applications ü ü ü 5-Port Gigabit Layer 2 Switches for workgroup High-port count Layer 2 switches with trunking High performance solution of Ethernet backbone Always contact ASIX for possible updates before starting a design. This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. ASIX ELECTRONICS CORPORATION 4F, NO.8, Hsin Ann Rd., Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-563-9799 First Released Date: 01/31/2002 http://www.asix.com.tw AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch System Block Diagram AX88655P Switch Controller EEPROM 5 * 10/100/1000 Mbps PHYs 2 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch CONTENTS 1.0 AX88655 OVERVIEW ............................................................................................................. 6 1.1 GENERAL DESCRIPTION ..................................................................................................................... 6 1.2 AX88655 BLOCK DIAGRAM ................................................................................................. 6 1.3 PIN CONNECTION DIAGRAM ............................................................................................................. 7 2.0 I/O DEFINITION ............................................................................................................................................... 8 2.1 GMII/MII INTERFACE ........................................................................................................................ 8 2.1.1 GMII Interface Port 0 ................................................................................................................................ 8 2.1.2 GMII Interface Port 1 ................................................................................................................................ 9 2.1.3 GMII Interface Port 2 ................................................................................................................................ 9 2.1.4 GMII Interface Port 3 ................................................................................................................................ 9 2.1.5 GMII Interface Port 4 .............................................................................................................................. 10 2.2 MISCELLANEOUS ................................................................................................................................. 10 3.0 FUNCTIONAL DESCRIPTION ................................................................................... 12 3.1 INTRODUCTION ..................................................................................................................................... 12 3.2 PACKET FILTERING AND FORWARDING PROCESS ................................................................. 12 3.3 MAC ADDRESS ROUTING, LEARNING AND AGING PROCESS .......................................... 12 3.4 FULL DUPLEX 802.3X FLOW CONTROL ..................................................................................... 12 3.5 HALF DUPLEX BACK PRESSURE CONTROL .............................................................................. 12 3.6 MII POLLING ......................................................................................................................................... 12 3.7 PORT-BASED QOS: PORT-PAIR ................................................................................................... 13 4.0 REGISTER DESCRIPTIONS ......................................................................................... 14 4.1 REGISTER 00.................................................................................................................................................... 14 4.2 REGISTER 01.................................................................................................................................................... 14 4.3 REGISTER 02.................................................................................................................................................... 14 4.4 REGISTER 03.................................................................................................................................................... 15 4.5 REGISTER 04.................................................................................................................................................... 15 4.6 REGISTER 05.................................................................................................................................................... 15 4.7 REGISTER 06.................................................................................................................................................... 15 4.8 REGISTER 07.................................................................................................................................................... 15 4.9 REGISTER 08.................................................................................................................................................... 15 4.10 REGISTER 09.................................................................................................................................................. 15 4.11 REGISTER 0A................................................................................................................................................. 15 4.12 REGISTER 0B ................................................................................................................................................. 16 4.13 REGISTER 0C ................................................................................................................................................. 16 4.14 REGISTER 0D................................................................................................................................................. 16 4.15 REGISTER 0E ................................................................................................................................................. 16 4.16 REGISTER 0F.................................................................................................................................................. 17 4.17 REGISTER 10.................................................................................................................................................. 17 4.18 REGISTER 11.................................................................................................................................................. 18 4.19 REGISTER 12.................................................................................................................................................. 18 4.20 REGISTER 13.................................................................................................................................................. 18 4.21 REGISTER 14.................................................................................................................................................. 18 3 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 5.0 ELECTRICAL SPECIFICATION AND TIMING ..................................... 19 5.1 ABSOLUTE MAXIMUM RATINGS ................................................................................................... 19 5.2 GENERAL OPERATION CONDITIONS ............................................................................................ 19 5.3 DC CHARACTERISTICS ..................................................................................................................... 19 5.4 AC SPECIFICATIONS ........................................................................................................................... 20 5.4.1 X_IN Signal Timing.................................................................................................................................. 20 5.4.2 Reset Signal Timing ................................................................................................................................. 20 5.4.3 GMII Transmit/Receive Signals Timing.................................................................................................... 21 5.4.4 100 Mbps MII Transmit/Receive Signals Timing ...................................................................................... 22 5.4.5 10 Mbps MII Transmit/Receive Signals Timing ........................................................................................ 23 6.0 PACKAGE INFORMATION .......................................................................................... 25 APPENDIX A: SYSTEM APPLICATIONS ............................................................... 26 A.1 AX88655 AS 5-PORT SOHO HIGH TRAFFIC POWER USER SWITCH ...................................................................... 26 A.2 AX88655 AS 5-PORT SMART SWITCH (DIP SWITCH CONFIGURABLE) ................................................................. 26 A.3 AX88655 FOR 10/100MBPS ETHERNET BACKBONE .......................................................................................... 27 A.4 AX88655 FOR SUPER SERVER TRUNKING APPLICATION .................................................................................... 27 APPENDIX B: DESIGN NOTE .............................................................................................. 28 B.1 USING MII I/F CONNECTS TO MAC.................................................................................................................. 28 APPENDIX C: WEIGHT SETTING FOR QOS..................................................... 29 DEMONSTRATION CIRCUIT (A) : AX88658 SMART SWITCH ... 30 4 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch FIGURES FIG-1 AX88655 BLOCK DIAGRAM ........................................................................................................... 6 FIG-2 AX88655 PIN DIAGRAM................................................................................................................... 7 5 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 1.0 AX88655 Overview 1.1 General Description The AX88655 Gigabit switch controller supports five 10/100/1000 Mbps ports in wire-speed operation. The AX88655 Gigabit switch controller provides five 10/100/1000 Ethernet ports with GMII/MII interface. For each ports, the AX88655 supports GMII (802.3ab) interface with full-duplex operation at Gigabit speed, full- or half-duplex operation at 10/100 Mbps speed and polls the status of PHYs with an embedded MPU. Embedded 128K bytes SRAM as a packet buffer operates with an internal 90MHz clock. For efficient utilization of the packet buffer, there are 1024 128-byte page-links totally in the buffer. The device supports 4K internal MAC addresses which are shared by all ports with an embedded 32K byte SSRAM. The learning/routing engine is implemented with a two-way hash/linear algorithm to reduce possibility of routing collision. Basically the AX88655 supports non-blocking wire speed forwarding rate and no Head-of-Line (HOL) blocking issue. The AX88655 provides two flow-control mechanisms to avoid loss of data: an optional jamming based backpressure flow control in the half-duplex operation and IEEE 802.3x in the full-duplex mode. To support Quality of Service (QoS), each output port has two priority queues and their assignment can be based on the 802.1p priority field or Port-Pair setting. Each output port retrieves the frames from the shared buffer based on queuing and sends them to the transmitting (Tx) FIFO. 1.2 AX88655 Block Diagram GMII PHY 10/100/1000 MAC GMII PHY 10/100/1000 MAC Routing /Learning Engine Address Look-up Table GMII PHY 10/100/1000 MAC High Speed Switch Fabric GMII PHY 10/100/1000 MAC GMII PHY 10/100/1000 MAC Buffer Manager Packet Buffer GPIO General Purpose I/O Interface (GPIO) Configuration Logic EEPROM Interface Fig-1 AX88655 Block Diagram 6 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 NC NC NC NC VSS VSS VSS VSS NC NC VDD25 VSS GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 NC NC NC NC VDD33 /RST VSS SYSCLK NC MDC MDIO SDC SDIO VDD25 GCLK VSS VSS /SYSCLK_EN /GCLK_EN SID4 SID3 SID2 SID1 SID0 VDD25 VSS TX_EN4 TXD4[7] TXD4[6] TXD4[5] TXD4[4] TXD4[3] TXD4[2] TXD4[1] TXD4[0] TX_CLK4 VDD25 GTX_CLK4 VSS RX_DV4 RX_CLK4 RXD4[7] RXD4[6] RXD4[5] RXD4[4] RXD4[3] RXD4[2] 1.3 Pin Connection Diagram 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 RXD4[1] RXD4[0] COL4 CRS4 VDD25 VSS TX_EN3 TXD3[7] TXD3[6] TXD3[5] TXD3[4] TXD3[3] TXD3[2] TXD3[1] TXD3[0] TX_CLK3 VDD25 GTX_CLK3 VSS RX_DV3 RX_CLK3 RXD3[7] RXD3[6] RXD3[5] RXD3[4] RXD3[3] RXD3[2] RXD3[1] RXD3[0] COL3 CRS3 VDD25 VSS25 TX_EN2 TXD2[7] TXD2[6] TXD2[5] TXD2[4] TXD2[3] TXD2[2] TXD2[1] TXD2[0] TX_CLK2 VDD25 GTX_CLK2 VSS RX_DV2 RX_CLK2 RXD2[7] RXD2[6] RXD2[5] RXD2[4] RXD2[3] RXD2[2] RXD2[1] RXD2[0] COL2 CRS2 VDD25 VSS25 TX_EN1 TXD1[7] TXD1[6] TXD1[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 AX88655P 10/100/1000Mbps Ethernet Switch Controller 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 TXD0[4] TXD0[5] TXD0[6] TXD0[7] TX_EN0 VSS VDD25 NC NC VSS VSS VSS VSS NC NC NC NC VSS VSS VSS NC VDD25 NC NC NC NC NC NC NC NC NC NC VSS VDD33 X_IN X_OUT AVBB25 AVDD25A AVSS25A FILTER AVSS25D AVDD25D NC CRS1 COL1 RXD1[0] RXD1[1] RXD1[2] RXD1[3] RXD1[4] RXD1[5] RXD1[6] RXD1[7] RX_CLK1 RX_DV1 VSS GTX_CLK1 VDD25 TX_CLK1 TXD1[1] TXD1[1] TXD1[2] TXD1[3] TXD1[4] 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 96 VSS VSS VSS NC VDD25 NC NC NC NC NC NC NC NC NC NC VSS VDD25 NC NC VSS VSS VSS VSS NC NC NC NC VSS VSS VSS NC VDD25 NC NC NC NC NC NC NC NC NC NC VSS25 VDD25 CRS0 COL0 RXD0[0] RXD0[1] RXD0[2] RXD0[3] RXD0[4] RXD0[5] RXD0[6] RXD0[7] RX_CLK0 RX_DV0 VSS GTX_CLK0 VDD25 TX_CLK0 TXD0[0] TXD0[1] TXD0[2] TXD0[3] Fig-2 AX88655 Pin Diagram 7 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 2.0 Pin Descriptions 2.0 I/O Definition The following terms describe the AX88655 pin-out: All pin names with the “/” suffix are asserted low. The following abbreviations are used in following Tables. I O I/O OD Input Output Input/Output Open Drain PU PD P Pull Up Pull Down Power Pin 2.1 GMII/MII Interface 2.1.1 GMII Interface Port 0 Pin No. Signal Name I/O GTX_CLK0 O 250 TX_EN0 O 5 TXD0[7:0] O 4 – 1, 256 – 253 TX_CLK0 I/PD 252 COL0 I/PD 238 CRS0 I/PD 237 RX_DV0 I 248 RX_CLK0 I 247 RXD0[7:0] I/PD 246 - 239 Description 125MHz Clock Output: it is a continuous 125 MHz clock output to giga-PHY operating at 1000BASE-T. That is, it is a timing reference for TX_EN0 and TXD0[7:0] Transmit Enable: When TX_EN0 is asserted, data on TXD0[7:0] are transmitted onto PHY. TX_EN0 is synchronous to GTX_CLK0 in 1000BASE-T mode and synchronous to TX_CLK0 in 10/100BASE-T mode. Transmit Data: Synchronous to the rising of GTX_CLK0 in 1000BASE-T mode. And synchronous to rising edge of TX_CLK0 in 10/100BASE-T mode. MII Transmit Clock Input: TX_EN0 and TXD0[3:0] are synchronous to the rising edge of this clock in 10/100BASE-T mode. Collision Detect: Active high to indicate that there is collision occurred in half duplex mode. In full duplex mode COL0 is always low. Carrier Sense: Active high if there is carrier on medium. In half duplex mode CRS0 is also asserted during transmission and asynchronous to any clock. Receive Data Valid: Active high to indicate that data presented on RXD0[7:0] is valid and synchronous to RX_CLK0. Receive Clock Input: 125, 25 and 2.5 MHz is running at 1000/100/10 BASE-T mode respectively. RX_DV0 and RXD0[7:0] are synchronous to rising edge of this clock. Receive Data: Data received by the PHY are presented on RXD0 and synchronous to RX_CLK0. RXD0[3:0] is valid in 10/100/1000BASE-T and RXD[7:4] is valid only in 1000BASE-T modes. 8 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 2.1.2 GMII Interface Port 1 Signal Name I/O Pin No. Description GTX_CLK1 O 57 125MHz Clock Output: Please references section 2.1.1. TX_EN1 O 68 Transmit Enable: Please references section 2.1.1. TXD1[7:0] O 67 – 60 Transmit Data: Please references section 2.1.1. TX_CLK1 COL1 CRS1 RX_DV1 RX_CLK1 RXD1[7:0] I/PD I/PD I/PD I I I/PD 59 45 44 55 54 53 - 46 MII Transmit Clock Input: Please references section 2.1.1. Collision Detect: Please references section 2.1.1. Carrier Sense: Please references section 2.1.1. Receive Data Valid: Please references section 2.1.1. Receive Clock Input: Please references section 2.1.1. Receive Data: Please references section 2.1.1. 2.1.3 GMII Interface Port 2 Pin No. Signal Name I/O Description GTX_CLK2 O 84 125MHz Clock Output: Please references section 2.1.1. TX_EN2 O 95 Transmit Enable: Please references section 2.1.1. TXD2[7:0] O 94 – 87 Transmit Data: Please references section 2.1.1. TX_CLK2 COL2 CRS2 RX_DV2 RX_CLK2 RXD2[7:0] I/PD I/PD I/PD I I I/PD 86 72 71 82 81 80 - 73 MII Transmit Clock Input: Please references section 2.1.1. Collision Detect: Please references section 2.1.1. Carrier Sense: Please references section 2.1.1. Receive Data Valid: Please references section 2.1.1. Receive Clock Input: Please references section 2.1.1. Receive Data: Please references section 2.1.1. 2.1.4 GMII Interface Port 3 Pin No. Signal Name I/O Description GTX_CLK3 O 111 125MHz Clock Output: Please references section 2.1.1. TX_EN3 O 122 Transmit Enable: Please references section 2.1.1. TXD3[7:0] O 121 – 114 Transmit Data: Please references section 2.1.1. TX_CLK3 COL3 CRS3 RX_DV3 RX_CLK3 RXD3[7:0] I/PD I/PD I/PD I I I/PD 113 99 98 109 108 107 - 100 MII Transmit Clock Input: Please references section 2.1.1. Collision Detect: Please references section 2.1.1. Carrier Sense: Please references section 2.1.1. Receive Data Valid: Please references section 2.1.1. Receive Clock Input: Please references section 2.1.1. Receive Data: Please references section 2.1.1. 9 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 2.1.5 GMII Interface Port 4 Signal Name I/O Pin No. Description GTX_CLK4 O 138 125MHz Clock Output: Please references section 2.1.1. TX_EN4 O 149 Transmit Enable: Please references section 2.1.1. TXD4[7:0] O 148 – 141 Transmit Data: Please references section 2.1.1. TX_CLK4 COL4 CRS4 RX_DV4 RX_CLK4 RXD4[7:0] I/PD I/PD I/PD I I I/PD 140 126 125 136 135 134 - 127 MII Transmit Clock Input: Please references section 2.1.1. Collision Detect: Please references section 2.1.1. Carrier Sense: Please references section 2.1.1. Receive Data Valid: Please references section 2.1.1. Receive Clock Input: Please references section 2.1.1. Receive Data: Please references section 2.1.1. 2.2 Miscellaneous Signal Name I/O Pin No. Description X_IN I 35 X_OUT O 36 I I I/PU I/PU 161 168 157 158 FILTER /RST MDIO I I I/O/PU 40 170 165 MDC SDIO O I/O/PU 166 163 Crystal or OSC 27MHz Input: This is a clock source of PLL. The PLL will generate a 90MHz internal clock. Crystal 27MHz Output: This pin should be floating with single-ended external clock. OSC 125MHz Input: 125MHz Clock for GMII System Clock Input: 85 ~ 90MHz Clock for switch kernel GCLK Enable: 0) use GCLK; 1) Reserved System Clock Enable: 0) use SYSCLK; 1) 90MHz generated by internal PLL circuit from X_IN clock source. FILTER: For internal PLL circuit use. Reset: Active Low Station Management Data In/Out: PHY Management Data Input and Output. Station Management Data Clock Out: PHY Management Clock. EEPROM Data In/Out: EEPROM Serial Data Input and Output. SDC I/O/PU 164 SID[4:0] I/PD I/PD I/PD I/UP I/UP I/O/PU 156, 155, 154, 153, 152 180 - 176 GCLK SYSCLK /GCLK _EN /SYSCLK_EN GPIO[4:0] EEPROM Data Clock In/Out: EEPROM Serial Clock. (Note: It is output pin if the embedded MPU is active; otherwise as input pin) Switch ID: MPU can identify the switch and PHYs with this ID. Default is “00011b”. General Purpose I/O: The 5 GPIOs can be programmed for special application. (Note: The function is not released to user normally. Please contact with ASIX directly if any requirement) 10 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch NC N/A VDD33 VDD25 I P VSS P AVBB25 AVDD25A AVSS25A AVDD25D AVSS25D P P P P P 8, 9, 41, 15, 16, NC: No Connect. 17, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 43, 167, 172, 173, 174, 175, 183, 184, 189, 190, 191, 192, 196, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 210, 211, 216, 217, 218, 219, 223, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234 34, 171, 3.3V +/-5% Supply Voltage. 7, 22, 2.5V +/-5% Supply Voltage. 58, 70, 85, 97, 112, 124, 139, 151, 162, 182, 197, 209, 224, 236, 251 6, 10, 11, 12, Ground 13, 18, 19, 20, 33, 56, 69, 83,96, 110, 123, 137, 150, 157, 159, 160, 167, 169, 181, 185, 186, 187, 188, 193, 194, 195, 208, 212, 213, 214, 215, 220, 221, 222, 235, 249 37 Ground for PLL 38 2.5V +/-5% Supply Voltage for PLL. 39 Ground for PLL 42 2.5V +/-5% Supply Voltage for PLL. 41 Ground for PLL 11 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 3.0 Functional Description 3.1 Introduction In general, the AX88655 device is a highly integrated Layer 2 switch. It supports five 10/100/1000 ports with on-chip MACs. It also supports integrated switching logic, packet queuing memory and packet storage memory. The AX88655 is capable of routing-and-forwarding packets at wire speed on all ports regardless of packet size. It is a low cost solution for five ports Gigabit Ethernet backbone switch design. No CPU interface is required; After power on reset, AX88655 provide an auto load configuration setting function through a 2 wire serial EEPROM interface to access external EEPROM device, and AX88655 can easily be configured to support trunking, QoS, IEEE 802.3x flow control threshold setting, broadcast storm control ...etc functions. An overview of AX88658’s major functional blocks is shown in Fig-1. 3.2 Packet Filtering and Forwarding Process The switch use simple store-and-forward algorithm as packet switching method. After receives incoming packets, the packets will be stored to the embedded memory first. The AX88655 searches in the Address-Lookup Table with DA of the packet. The packet will be forward to its destination port, if this packet’s DA hits; otherwise this packet will be broadcasted. Of course, only good packets will be forward. Conditions of good packets are below: 1. CRC is correct. 2. 64 Bytes < PacketLength < 1518/1522 Bytes 3. Not local packets, That is, it is a local packets if its SourcePort is its DestinationPort. 4. Not PAUSE or other control packets. 5. Not the same trunking group. 3.3 MAC Address Routing, Learning and Aging Process The switch supports 4K MAC entries for switching. Two-way dynamic address learning is performed by each good unicast packet is completely received. And linear/XOR hash algorithm of the static address learning is achieved by EEPROM configuration. On the other hand, the routing process is performed whenever the packet’s DA is captured. If the DA can not get a hit result, the packet is going to broadcast. Only the learned address entries are scheduled in the aging machine. If one station does not transmit any packet for a period of time, the belonging MAC address will be kicked out from the address table. The aging out time can be program automatically through the EEPROM configuration. (Default value is 300 seconds) 3.4 Full Duplex 802.3x Flow Control In full duplex mode, AX88655 supports the standard flow control mechanism defined in IEEE 802.3x standard. It enables the stopping of remote node transmissions via a PAUSE frame information interaction. When space of the packet buffer is less than the initialization setting threshold value, AX88655 will send out a PAUSE-ON packet with pause time equal to “xFFF” to stop the remote node transmission. And then AX88655 will send out a PAUSE-OFF packet with pause time equal to zero to inform the remote node to retransmit packet if has enough space to receive packets. 3.5 Half Duplex Back Pressure Control In half duplex mode, AX88655 provide a backpressure control mechanism to avoid dropping packets during network conjection situation. When space of the packet buffer is less than the initialization setting threshold value, AX88655 will send a JAM pattern in the input port when it senses an incoming packet, thus force a collision to make the remote node transmission back off and will effectively avoid dropping packets. And then AX88655 will not send out a JAM packet any more if has enough space to receive one packet. 3.6 MII Polling The AX88655 supports PHY management through the serial MDIO/MDC interface. That is, the AX88655 access related 12 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch register of PHYs via MDIO/MDC interface after power on reset. The AX88655 will periodically and continuously poll and update the link status and link partner’s ability which include speed, duplex mode, and 802.3x flow control capable status of the connected PHY devices through MDIO/MDC serial interface. 3.7 Port-Based QoS: Port-Pair AX88655 provides 4 Port-Pairs for bandwidth management. Users can assign any two ports as one Port-Pair with internal registers basically. Any packets will put the high priority queue of the Port-Pair when send the packets each other. That is, two ports of each Port-Pair will obtain more bandwidth than other ports when congestion. In addition, one port can be as the highest priority port if one All_Bit of a Port-Pair is active. That is, user can assign format of the Port-Pair as OnePort-to-All and every packets of the OnePort will put in the high priority transmit queue of other ports. 13 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 4.0 Register Descriptions Registers Table Summary: Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 00 H Reserved 0000 H 01 H Reserved 0000 H 02 H Reserved RxFlowCtrl[4:0] Reserved TxFlowCtrl[4:0] 0000 H 03 H Reserved 0000 H 04 H Reserved 0000 H 05 H Reserved 0000 H 06 H Reserved 0000 H 07 H Reserved 1215 H 08 H Reserved 7777 H 09 H Reserved 7777 H 0A H PortPair1[7:0] PortPair0[7:0] 0000 H 0B H PortPair3[7:0] PortPair2[7:0] 0000 H 0C H LowQueueWeight[3:0] Reserved lw_LowQueueDiscardLimit [9:0] 1060 H 0D H HighQueueWeight[3:0] MaxStorm lw_HighQueueDiscardLimit [9:0] 1060 H 0E H Res. PTO MPL Reserved SR SP NSB Reserved QoS[1:0] AE HM Res. 8880 H 0F H Reserved MaxAge[8:0] 1865 H 10 H Reserved Trunk30[2:0] Reserved 00C0 H 11 H Reserved LowQueueFlowCtrlMark[9:0] 0010 H 12 H MaxJam[5:0] HighQueueFlowCtrlMark[9:0] 2810 H 13 H Reserved hw_LowQueueDiscardLimit[9:0] 0070 H 14 H Reserved hw_HighQueueDiscardLimit[9:0] 0070 H Notes: 1. The word “Reserved” = “Res.” on the above table. Notes: 2. Care must be taken that the “Reserved” registers should keep the default value always. Change of any reserved value may be resulting in unpredictable conditions. Notes: 3. The registers can be accessed by internal MPU only. The MPU will read in configuration table, located on EEPROM at somewhere address, and programs the above registers when every time power on or after system reset. 4.1 Register 00 BIT 15:0 R/W R/W DESCRIPTION Reserved 4.2 Register 01 BIT 15:0 R/W R/W DESCRIPTION Reserved 4.3 Register 02 BIT 15:13 R/W R/W DESCRIPTION Reserved 14 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 12:8 R/W 7:5 4:0 R/W R/W FlowCtrlEnable for MAC’s receive part of Port[4:0] are configured by internal 8051 0: not identify PAUSE frames by receive part of MAC 1: can identify PAUSE frames. That is, PauseTimer of MAC will be active. Reserved FlowCtrlEnable for MAC’s transmit part of Port[4:0] are configured by internal 8051 0: not send PAUSE frames or JAM 1: send PAUSE frames for full-duplex when the packet buffer is empty. send JAM frames for half-duplex when the packet buffer is empty. 4.4 Register 03 BIT 15:0 R/W R/W DESCRIPTION Reserved 4.5 Register 04 BIT 15:0 R/W R/W DESCRIPTION Reserved 4.6 Register 05 BIT 15:0 R/W R/W DESCRIPTION Reserved 4.7 Register 06 BIT 15:0 R/W R/W DESCRIPTION Reserved 4.8 Register 07 BIT 15:0 R/W R/W DESCRIPTION Reserved 4.9 Register 08 BIT 15:0 R/W R/W DESCRIPTION Reserved 4.10 Register 09 BIT 15:0 R/W R/W DESCRIPTION Reserved 4.11 Register 0A BIT 15 14:12 R/W R/W R/W DESCRIPTION All_Bit of PortPair #1 when QoS[0] is high Port_ID of PortPair #1 when QoS[0] is high 15 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 11 10:8 7 6:4 3 2:0 R/W R/W R/W R/W R/W R/W All_Bit of PortPair #1 when QoS[0] is high Port_ID of PortPair #1 when QoS[0] is high All_Bit of PortPair #0 when QoS[0] is high Port_ID of PortPair #0 when QoS[0] is high All_Bit of PortPair #0 when QoS[0] is high Port_ID of PortPair #0 when QoS[0] is high 4.12 Register 0B BIT 15 14:12 11 10:8 7 6:4 3 2:0 R/W R/W R/W R/W R/W R/W R/W R/W R/W DESCRIPTION All_Bit of PortPair #3 when QoS[0] is high Port_ID of PortPair #3 when QoS[0] is high All_Bit of PortPair #3 when QoS[0] is high Port_ID of PortPair #3 when QoS[0] is high All_Bit of PortPair #2 when QoS[0] is high Port_ID of PortPair #2 when QoS[0] is high All_Bit of PortPair #2 when QoS[0] is high Port_ID of PortPair #2 when QoS[0] is high 4.13 Register 0C BIT 15:12 11:10 9:0 R/W R/W R/W R/W DESCRIPTION WeightForLowQue: Weight for low priority queues when QoS is active (see Appendix C) Reserved LowWaterMark of low priority queues when drop packets 4.14 Register 0D BIT 15:12 11:10 R/W R/W R/W 9:0 R/W DESCRIPTION WeightForHighQue: Weight for high priority queues when QoS is active (see Appendix C) Maximum number of broadcast frames that can be accumulated in each input frame buffer. 00: disable broadcast storm control 01: 32 frames 10: 48 frames 11: 64 frames LowWaterMark of high priority queues when drop packets 4.15 Register 0E BIT 15 14 R/W R/W R/W 13 R/W 12:11 10 R/W R/W DESCRIPTION Reserved 802.3x Flow control frame recognition control 0: check for MAC control frame DA MAC address in addition to the MAC control type field 1: check only the MAC control type field Setting for maximum length of packet that received 0: 1518 byte 1: 1522 byte Reserved Software Reset (Only reset the switch kernel) 0: active 1: disable 16 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 9 R/W 8 R/W 7:5 4:3 R/W R/W 2 R/W 1 R/W 0 R/W Back-off algorithm selection 0: disable. Device will perform the IEEE standard exponential back off algorithm when a collision occurs. 1: enable. When collisions occur, the MACs will back off up to 7 slots. 0: stop generate JAM patterns after some collision that is defined by MaxJam[5:0] 1: Never stop back-pressure Reserved QoS selection 00: disable QoS function 01: Port-Pair Priority algorithm 10: 802.1p AgingEnable Switch Table Entry Aging Control. Only the dynamically learned addresses will be aged. All explicit entries will not age. The aging time is programmed in register 0F. 0: disable. The table aging process is disabled. 1: enable. The table aging process is enabled and a hardware process ages every dynamically learned table entry. Hash algorithm selection 0: XOR mapping 1: Linear mapping Reserved 4.16 Register 0F BIT 15:9 8:0 R/W R/W R/W DESCRIPTION Reserved MaxAge. This is a seven-bit register containing unsigned integer for determining the address-aging timer. The resolution of the normal address aging is (64 M* MaxAge[8:0]) / FreqencyOfSystemClock. Default value is 300 seconds. 4.17 Register 10 BIT 15:13 12:10 R/W R/W R/W 9:0 R/W DESCRIPTION Reserved Trunking selection for Port[3:0] 000: disable trunking 001: disable trunking 010: one 2-Port Trunking for Port[1:0] 011: one 2-Port Trunking for Port[1:0] 100: one 2-Port Trunking for Port[3:2] 101: one 4-Port Trunking 110: two 2-Port Trunkings for Port[3:2] and Port[1:0] 111: one 4-Port Trunking Reserved 17 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 4.18 Register 11 BIT 15:10 9:0 R/W R/W R/W DESCRIPTION Reserved LowWaterMarkForFlowCtrl. This is a ten-bit register containing unsigned integer for transmit queues whether generate PAUSE-ON or not. 4.19 Register 12 BIT 15:10 R/W R/W 9:0 R/W DESCRIPTION MaxJam. This is a six-bit register containing unsigned integer for determining the JAM counter whether generate JAM or not. HighWaterMarkForFlowCtrl. This is a ten-bit register containing unsigned integer for transmit queues whether generate PAUSE-OFF or not. 4.20 Register 13 BIT 15:10 9:0 R/W R/W R/W DESCRIPTION Reserved HighWaterMark of low priority queues when drop packets 4.21 Register 14 BIT 15:10 9:0 R/W R/W R/W DESCRIPTION Reserved HighWaterMark of high priority queues when drop packets 18 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 5.0 ELECTRICAL SPECIFICATION AND TIMING 5.1 Absolute Maximum Ratings Description SYM Min Max Units Operating Temperature Ta 0 +70 °C Storage Temperature Ts -55 +150 °C Supply Voltage Vcc -0.3 +4.0 V Input Voltage Vin -0.3 Vdd+0.5 V Output Voltage Vout -0.3 Vdd+0.5 V Lead Temperature (soldering 10 seconds maximum) Tl -55 +220 °C Note: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability 5.2 General Operation Conditions Description SYM Ta Vdd Operating Temperature Supply Voltage Min 0 +3.0 Max +70 +3.6 Units °C V 5.3 DC Characteristics (Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 70°C) Description Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Input Leakage Current 1 (Note 1) Input Leakage Current 2 (Note 2) Output Leakage Current Description Power Consumption SYM Vil Vih Vol Voh Iil1 Iil1 Iol SYM Min Pc Min Vss-0.3 2 Max 0.8 Vdd+0.5 0.4 2.4 10 500 10 Tpy TBD Units V V V V uA uA uA Max Units mA Note: 1. All the input pins without pull low or pull high. 2. Those pins had been pull low or pull high. 19 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 5.4 AC specifications 5.4.1 X_IN Signal Timing Thigh X_IN Tr Tlow Description Symbol Tcyc Thigh Tlow Tr/Tf Tf Tcyc Min CYCLE TIME CLK HIGH TIME CLK LOW TIME CLK SLEW RATE Max 8 8 1 Typ. 20 10 10 - 12 12 4 Units ns ns ns ns Min 10 Typ. - Max - Units SYSCLK 5.4.2 Reset Signal Timing SYSCLK /RST Description Symbol Trst Reset pulse width 20 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 5.4.3 GMII Transmit/Receive Signals Timing T0 T1 GTX_CLK T2 T3 TX_EN TXD[7:0] Symbol T0 T1 T2 T3 Description GTX_CLK Clock Cycle Time GTX_CLK Clock High Time TX_EN and TXD data setup to GTX_CLK rising edge TX_EN and TXD data hold from GTX_CLK rising edge T4 Min 7.998 Typ. 8 4 Max 8.002 Units ns ns ns ns Max 8.002 Units ns ns ns ns 2.5 0.5 T5 RX_CLK T6 T7 RX_DV RXD[7:0] Symbol T4 T5 T6 T7 Description RX_CLK Clock Cycle Time RX_CLK Clock High Time RX_DV and RXD data setup to RX_CLK rising edge RX_DV and RXD data hold from RX_CLK rising edge 21 Min 7.998 2.5 0.5 Typ. 8 4 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 5.4.4 100 Mbps MII Transmit/Receive Signals Timing T0 T1 TX_CLK T2 T2 TX_EN T3 T3 TXD[3:0] Symbol T0 T1 T2 T3 Description TX_CLK Cycle Time TX_CLK High Time TX_CLK rising edge to TX_EN Delay TX_CLK rising edge to TXD Delay T4 Min 39.996 14 7.440 3.410 Typ. 40 20 Max 40.004 26 21.760 13.320 Units ns ns ns ns T5 RX_CLK T6 T6 RX_CRS RX_DV T7 T7 Description RX_CLK Clock Cycle Time RX_CLK Clock High Time RX_CLK rising edge to RX_DV and RX_CRS Delay RX_CLK rising edge to RXD Delay Min 39.996 14 3.0 3.0 RXD[3:0] Symbol T4 T5 T6 T7 22 Typ. 40 20 Max 40.004 26 13.0 13.0 Units ns ns ns ns ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 5.4.5 10 Mbps MII Transmit/Receive Signals Timing T0 T1 TX_CLK T2 T2 TX_EN T3 T3 TXD[3:0] Symbol T0 T1 T2 T3 Description TX_CLK Cycle Time TX_CLK High Time TX_CLK rising edge to TX_EN Delay TX_CLK rising edge to TXD Delay T4 Min 399.96 14 7.440 3.410 Typ. 400 20 Max 400.04 26 21.760 13.320 Units ns ns ns ns T5 RX_CLK T6 T6 RX_CRS RX_DV T7 T7 Description RX_CLK Clock Cycle Time RX_CLK Clock High Time RX_CLK rising edge to RX_DV and RX_CRS Delay RX_CLK rising edge to RXD Delay Min 399. 96 140 3.0 3.0 RXD[3:0] Symbol T4 T5 T6 T7 23 Typ. 400 200 Max 400. 04 260 13.0 13.0 Units ns ns ns ns ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 24 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch 6.0 PACKAGE INFORMATION A2 A1 L L1 D Hd He E pin 1 e b θ SYMBOL MILIMETER MIN. A1 NOM 0.25 A2 3.4 b 0.16 D 28.00 E 28.00 e 0.4 Hd 30.6 He 30.6 L 0.45 0.75 L1 θ MAX 1.3 0 7 25 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch Appendix A: System Applications A.1 AX88655 as 5-Port SOHO high traffic power user switch I/O Port for Configuration From PC AX88655P Switch Controller SEEPROM for save Configuration Quad GMII PHY Or 4 GMII PHYs 1 GMII PHY A.2 AX88655 as 5-Port Smart switch (DIP switch configurable) DIP SW LEDs or General Serial Output via GPIO Configuration Serial In via GPIO AX88655P EEPROM Switch Controller 5 * 10/100/1000Mbps PHYs 26 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch A.3 AX88655 for 10/100Mbps Ethernet Backbone 5-port Gigabit switch AX88655P Switch Controller 16*10/100Mbps +2*1000Mbps Ethernet Switch 16*10/100Mbps +2*1000Mbps Ethernet Switch WAN Router Using 2 Gigabit Ports Up-link and Trunking form a 12.8G Non-blocking backbone A.4 AX88655 for Super Server Trunking Application 5-port Gigabit switch AX88655 P Switch Controller Super Server with 2 * Gigabit Ethernet Cards Trunking 27 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch Appendix B: Design Note B.1 Using MII I/F connects to MAC Using MII interface to connect to MAC type device application for AX88655 is illustrated bellow. 25MHz Clock COL0 COL TX_EN0 CRS RX_DV RX_CLK RXD[3:0] RX_ER TX_CLK0 TXD0[3:0] CRS0 RX_DV0 RX_CLK0 RXD0[3:0] TX_EN TX_CLK TXD[3:0] TX_ER 10K Gnd AX88655 / Switch AX88195 / MAC Note: 1. The MAC needs to run at full-duplex mode. 2. Care must be taken that the receive side has enough setup and/or hold time 3. Some kind of CPU with embedded MAC can also refer to this example 28 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch Appendix C: Weight Setting for QoS Service Ratio (High : Low) 1:1 2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 WeightForHighQue[3:0] WeightForLowQue[3:0] 4’b0100 4’b0100 4’b0110 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 4’b0100 4’b0010 4’b0010 4’b0001 4’b0001 4’b0001 4’b0001 4’b0001 4’b0001 4’b0001 4’b0001 4’b0001 4’b0001 4’b0001 4’b0001 29 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch Demonstration Circuit (A) : AX88658 Smart Switch TX_EN TXD[0..7] TX_CLK GTX_CLK RX_DV RX_CLK RXD[0..7] COL CRS VDD25 TX_EN4 TXD4[0..7] TX_CLK4 GTX_CLK4 RX_RV4 RX_CLK4 RXD4[0..7] COL4 CRS4 VDD18 PORT4 GPHY4 TX_EN4 TXD4[0..7] TX_CLK4 GTX_CLK4 RX_DV4 RX_CLK4 RXD4[0..7] COL4 CRS4 GND SDC VDD25_2 VDD25 VDD33 VDD33 VDD25_2 VDD18_1 SDIO SDC VDD18_2 VDD25 SDIO MDIO MDC MDC MDIO VDD25_2 VDD33 VDD33 VDD25_2 RST#_SW RESET# GCLK GCLK GSW_CKT SYSCLK GND VDD25 VDD18_2 GND RST_CTL# RST#_SW RST#_P0 RST#_P12 RST#_P34 GND GCLK RST_CTL# RST#_SW RST#_P0 RST#_P12 RST#_P34 GND SDC SDIO POWER_CKT POWER_CKT RST_CTL# VDD18_1 VDD33 SYSCLK VDD33 VDD33 ROM_CKT ROM_CKT SYSCLK OSC_CKT GND 25M_P0 25M_P1 25M_P2 25M_P3 25M_P4 GND VDD33 OSC_CKT 25M_P0 25M_P1 25M_P2 25M_P3 25M_P4 VDD18_2 AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch Application. MDIO MDC PHY_RST# 25MHZ MDIO MDC RST#_P34 25M_P4 TX_EN TXD[0..7] TX_CLK GTX_CLK RX_DV RX_CLK RXD[0..7] COL CRS VDD25 TX_EN3 TXD3[0..7] TX_CLK3 GTX_CLK3 RX_DV3 RX_CLK3 RXD3[0..7] COL3 CRS3 GND PORT3 GPHY3 TX_EN3 TXD3[0..7] TX_CLK3 GTX_CLK3 RX_RV3 RX_CLK3 RXD3[0..7] COL3 CRS3 VDD18 GND VDD18_2 VDD25 VDD25 VDD18 TX_EN TXD[0..7] TX_CLK GTX_CLK RX_DV RX_CLK RXD[0..7] COL CRS MDIO MDC PHY_RST# GND TX_EN2 TXD2[0..7] TX_CLK2 GTX_CLK2 RX_DV2 RX_CLK2 RXD2[0..7] COL2 CRS2 RST#_P34 25M_P3 25MHZ MDIO MDC RST#_P12 25M_P2 GND TX_EN1 TXD1[0..7] TX_CLK1 GTX_CLK1 RX_DV1 RX_CLK1 RXD1[0..7] COL1 CRS1 TX_EN TXD[0..7] TX_CLK GTX_CLK RX_DV RX_CLK RXD[0..7] COL CRS VDD25 VDD18_2 VDD25 PORT1 GPHY1 GSW_CKT VDD18 TX_EN2 TXD2[0..7] TX_CLK2 GTX_CLK2 RX_RV2 RX_CLK2 RXD2[0..7] COL2 CRS2 GND TXD1[0..7] TX_CLK1 TX_EN1 GTX_CLK1 RX_DV1 RX_CLK1 RXD1[0..7] GND COL1 CRS0 COL0 RXD0[0..7] RX_CLK0 RX_DV0 GTX_CLK0 TX_CLK0 TXD0[0..7] TX_EN0 CRS1 VDD25 CRS0 COL0 RXD0[0..7] RX_CLK0 RX_DV0 GTX_CLK0 TX_CLK0 TXD0[0..7] TX_EN0 GND 25MHZ PORT2 GPHY2 CRS COL RXD[0..7] RX_CLK RX_DV GTX_CLK TX_CLK TXD[0..7] TX_EN GND 25M_P0 PHY_RST# GND RST#_P0 MDIO MDC VDD18 PORT0 GPHY0 25MHZ MDIO MDC GND VDD18_2 VDD25 VDD18_1 VDD25 MDIO MDC MDIO MDC PHY_RST# MDIO MDC PHY_RST# 25MHZ MDIO MDC RST#_P12 25M_P1 GND ASIX ELECTRONICS CORPORATION Title AX88655 P 5-Port 10/100/1000BASE-T EtherNet Switch --- ROOT CKT. Size C Date: 30 Document Number Rev 1.0 GSW_ROOT.SCH Thursday, March 14, 2002 Sheet 1 of ASIX ELECTRONICS 10 AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch GTX_CLK TXD[0..7] TX_EN MDIO MDC PHY_RST# 25MHZ VDD25 VDD18 CRS COL RXD[0..7] RX_CLK RX_DV TX_CLK PHY ID : 00110 VDD25 VDD18 GND VDD_O GND CRS COL RXD[0..7] RX_CLK RX_DV TX_CLK GTX_CLK TXD[0..7] TX_EN MDIO MDC RESET# 25M_IN PHYADD0 PHYADD1 PHYADD2 PHYADD3 PHYADD4 AN_EN DUPLEX SPEED1 SPEED R1 R2 R3 R4 R5 R6 R7 R8 R9 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k PHYADD0 R11 1k D1 AN_EN R12 1k D2 LED DUPLEX R14 1k D3 LED SPEED1 R15 1k D4 LED Link Link SPEED R16 1k D5 LED Activity LED VDD_O R10 4.7K LED VDD_O RESET# R13 VDD_O 2K 4.7K VDD_O GND RX_DV R20 RXD7 RXD6 RXD5 RXD4 R21 10 RXD3 RXD2 RXD1 RXD0 R25 10 0 VDD_C GND VDD_O GND R28 TX_CLK GND R32 R33 10 VDD_O GND 10 4.7K TX_EN VDD_C GND GND VDD_O GND VDD_O GND VDD_C PHYADD3 PHYADD2 GND VDD_O PHYADD1 PHYADD0 GND VDD_C AN_EN DUPLEX SPEED1 SPEED GND GND VDD_C GND GND GND GND VDD_O COL CRS RX_ER IO_VDD VSS RX_DV RXD7 RXD6 RXD5 CORD_VDD VSS RXD4 RXD3 RXD2 IO_VDD VSS RXD1 RXD0 RX_CLK IO_VDD VSS TX_CLK TX_ER TX_EN CORD_VDD VSS U1 RX_VDD25 DP83865AVH VSS MDID_N MDID_P VSS VSS RX_VDD VSS MDIC_N MDIC_P VSS VSS RX_VDD VSS MDIB_N MDIB_P VSS VSS RX_VDD VSS MDIA_N MDIA_P VSS VSS RX_VDD VSS RX_VDD 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 GND MDID_N MDID_P GND GND VDD_C GND MDIC_N MDIC_P GND GND VDD_C GND MDIB_N MDIB_P GND GND VDD_C GND MDIA_N MDIA_P GND GND VDD_C GND VDD_C 0 R40 1.5K R37 4.7K R39 C17 C5 0.1uF 0.1uF C3 R18 49.9 0.1uF R22 49.9 C6 R23 49.9 0.1uF MDIC_N MDIC_P RX_VDD25 C7 C8 0.1uF 0.1uF R29 49.9 C9 R30 49.9 0.1uF MDIB_N MDIB_P TF1 1 2 3 4 5 6 7 8 9 10 11 12 TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4- MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4- 24 23 22 21 20 19 18 17 16 15 14 13 R24 MDI_DMDI_D+ R26 MDI_CMDI_C+ R27 MDI_BMDI_B+ R31 MDI_AMDI_A+ 75 12 8 7 6 5 4 3 2 1 11 MDI_DMDI_D+ MDI_BMDI_CMDI_C+ MDI_B+ MDI_AMDI_A+ 75 75 75 JACK1 RJ45_A 24HST1041 C10 0.01uF/2KV C11 C12 0.1uF 0.1uF R34 49.9 C14 0.1uF C15 1000pF C13 R35 49.9 0.1uF 9.76K GND 22 L1 MDIO C4 R17 49.9 RX_VDD25 TXD7 TXD6 TXD5 TXD4 VDD_O GND TXD3 TXD2 VDD_C GND TXD1 TXD0 VDD_O GND R38 0.1uF MDIA_N MDIA_P R36 VDD_O C2 0.1uF RX_VDD25 TXD[0..7] GTX_CLK C1 MDID_N MDID_P 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 GND 82 VDD_O 83 84 85 86 87 88 89 VDD_O 90 GND 91 VDD_C 92 GND 93 94 PHYADD4 95 RX_VDD25 96 GND 97 98 GND 99 VDD_C 100 RX_VDD25 101 102 RX_CLK 100 LED 10 LED SHIELD R19 RXD[0..7] 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TXD7 TXD6 TXD5 TXD4 IO_VDD VSS TXD3 TXD2 CORD_VDD VSS TXD1 TXD0 IO_VDD VSS GTX_CLK MDIO MDC VSS IO_VDD RESERVER CLK_TO_MAC CLK_IN CLK_OUT MAC_CLK_EN_STRAP MDIX_EN_STRAP IO_VDD VSS CORD_VDD VSS MULTI_EN_STRAP PHYADDR4_STRAP AFE_VDD VSS PGM_VDD VSS CORD_VDD BG_VDD BG_REF COL CRS GND 38 VSS 37 IO_VDD 36 VSS 35 CORE_VDD 34 VDD_SEL_STRAP 33 /RESET 32 /TRST 31 TDI 30 VSS 29 IO_VDD 28 TDO 27 TMS 26 VSS 25 CORE_VDD 24 TCK 23 RESERVED 22 VSS 21 IO_VDD 20 VSS 19 CORE_VDD 18 PHYADDR3_STRAP 17 PHYADDR2_STRAP 16 VSS 15 IO_VDD 14 PHYADDR1_STRAP 13 PHYADDR0_STRAP /DUPLEX_LED 12 VSS 11 CORE_VDD 10 AN_EN_STRAP /LINK1000_LED 9 LINK100_LED /DUPLEX_STRAP 8 LINK10_LED /SPEED1_STRAP 7 ACTIVITY_LED /SPEED_STRAP 6 TX_TCLK 5 VSS 4 IO_VDD 3 /INTERRUPT 2 RESERVED 1 NON_IEEE_STRAP GND VDD_O GND VDD_C GND OPTION DUPLEX LED Link 1000 LED VDD_C F.B. + C16 VDD_O VDD_O MDC R41 0.1uF 1.5K 22uF Option 25M_IN R42 4.7K RX_VDD25 VDD_O + C18 C19 100uF/16V 0.1uF C20 C21 C22 1000pF 0.1uF 0.1uF GND L2 VDD25 VDD_O + C23 C25 100uF/16V 0.1uF C26 F.B. 1000pF + C24 C27 100uF/16V 0.1uF C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GND L3 VDD18 VDD_C ASIX ELECTRONICS CORPORATION + C42 C44 100uF/16V 0.1uF C45 F.B. 1000pF + C43 C46 100uF/16V 0.1uF GND Title AX88655 P 5-Port 10/100/1000BASE-T EtherNet Switch --- Port 0 G'PHY CKT. Size C Date: 31 Document Number Rev 1.0 GPHY0.SCH Thursday, March 14, 2002 Sheet 2 of 10 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch GTX_CLK TXD[0..7] TX_EN MDIO MDC PHY_RST# 25MHZ VDD25 VDD18 CRS COL RXD[0..7] RX_CLK RX_DV TX_CLK PHY ID : 01000 VDD25 VDD18 GND VDD_O GND CRS COL RXD[0..7] RX_CLK RX_DV TX_CLK GTX_CLK TXD[0..7] TX_EN MDIO MDC RESET# 25M_IN PHYADD0 PHYADD1 PHYADD2 PHYADD3 PHYADD4 AN_EN DUPLEX SPEED1 SPEED R43 R44 R45 R46 R47 R48 R49 R50 R51 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k PHYADD0 R53 1k D6 AN_EN R54 1k D7 LED DUPLEX R56 1k D8 LED SPEED1 R57 1k D9 LED Link Link SPEED R58 1k D10 LED Activity LED VDD_O R52 4.7K LED DUPLEX LED VDD_O RESET# R55 VDD_O 2K 4.7K VDD_O GND RX_DV R62 RXD7 RXD6 RXD5 RXD4 R63 10 RXD3 RXD2 RXD1 RXD0 R67 10 0 VDD_C GND VDD_O GND R70 TX_CLK GND R74 R75 10 VDD_O GND 10 4.7K TX_EN VDD_C GND GND VDD_O GND VDD_O GND VDD_C PHYADD3 PHYADD2 GND VDD_O PHYADD1 PHYADD0 GND VDD_C AN_EN DUPLEX SPEED1 SPEED GND GND VDD_C GND GND GND GND VDD_O COL CRS RX_ER IO_VDD VSS RX_DV RXD7 RXD6 RXD5 CORD_VDD VSS RXD4 RXD3 RXD2 IO_VDD VSS RXD1 RXD0 RX_CLK IO_VDD VSS TX_CLK TX_ER TX_EN CORD_VDD VSS RX_VDD25 DP83865AVH VSS MDID_N MDID_P VSS VSS RX_VDD VSS MDIC_N MDIC_P VSS VSS RX_VDD VSS MDIB_N MDIB_P VSS VSS RX_VDD VSS MDIA_N MDIA_P VSS VSS RX_VDD VSS RX_VDD 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 GND MDID_N MDID_P GND GND VDD_C GND MDIC_N MDIC_P GND GND VDD_C GND MDIB_N MDIB_P GND GND VDD_C GND MDIA_N MDIA_P GND GND VDD_C GND VDD_C 0 R82 1.5K C65 C66 0.1uF 0.1uF R59 49.9 C64 R60 49.9 0.1uF RX_VDD25 R64 49.9 C67 R65 49.9 0.1uF MDIC_N MDIC_P RX_VDD25 C68 C69 0.1uF 0.1uF R71 49.9 C70 R72 49.9 0.1uF MDIB_N MDIB_P R78 9.76K GND R81 22 L4 C78 0.1uF TF2 1 2 3 4 5 6 7 8 9 10 11 12 TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4- MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4- 24 23 22 21 20 19 18 17 16 15 14 13 R66 MDI_DMDI_D+ R68 MDI_CMDI_C+ R69 MDI_BMDI_B+ R73 MDI_AMDI_A+ 75 12 8 7 6 5 4 3 2 1 11 MDI_DMDI_D+ MDI_BMDI_CMDI_C+ MDI_B+ MDI_AMDI_A+ 75 75 75 JACK2 RJ45_A 24HST1041 C71 0.01uF/2KV C72 C73 0.1uF 0.1uF R76 49.9 C75 0.1uF C76 1000pF C74 R77 49.9 0.1uF MDIA_N MDIA_P R79 4.7K MDIO C63 0.1uF MDID_N MDID_P TXD7 TXD6 TXD5 TXD4 VDD_O GND TXD3 TXD2 VDD_C GND TXD1 TXD0 VDD_O GND R80 VDD_O C62 RX_VDD25 TXD[0..7] GTX_CLK 100 LED 10 LED U2 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 GND 82 VDD_O 83 84 85 86 87 88 89 VDD_O 90 GND 91 VDD_C 92 GND 93 94 PHYADD4 95 RX_VDD25 96 GND 97 98 GND 99 VDD_C 100 RX_VDD25 101 102 RX_CLK Link 1000 LED SHIELD R61 RXD[0..7] 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TXD7 TXD6 TXD5 TXD4 IO_VDD VSS TXD3 TXD2 CORD_VDD VSS TXD1 TXD0 IO_VDD VSS GTX_CLK MDIO MDC VSS IO_VDD RESERVER CLK_TO_MAC CLK_IN CLK_OUT MAC_CLK_EN_STRAP MDIX_EN_STRAP IO_VDD VSS CORD_VDD VSS MULTI_EN_STRAP PHYADDR4_STRAP AFE_VDD VSS PGM_VDD VSS CORD_VDD BG_VDD BG_REF COL CRS GND 38 VSS 37 IO_VDD 36 VSS 35 CORE_VDD 34 VDD_SEL_STRAP 33 /RESET 32 /TRST 31 TDI 30 VSS 29 IO_VDD 28 TDO 27 TMS 26 VSS 25 CORE_VDD 24 TCK 23 RESERVED 22 VSS 21 IO_VDD 20 VSS 19 CORE_VDD 18 PHYADDR3_STRAP 17 PHYADDR2_STRAP 16 VSS 15 IO_VDD 14 PHYADDR1_STRAP 13 PHYADDR0_STRAP /DUPLEX_LED 12 VSS 11 CORE_VDD 10 AN_EN_STRAP /LINK1000_LED 9 LINK100_LED /DUPLEX_STRAP 8 LINK10_LED /SPEED1_STRAP 7 ACTIVITY_LED /SPEED_STRAP 6 TX_TCLK 5 VSS 4 IO_VDD 3 /INTERRUPT 2 RESERVED 1 NON_IEEE_STRAP GND VDD_O GND VDD_C GND OPTION VDD_C F.B. + C77 VDD_O VDD_O MDC R83 0.1uF 1.5K 22uF OPTION 25M_IN R84 4.7K RX_VDD25 VDD_O + C79 C80 100uF/16V 0.1uF C81 C82 C83 1000pF 0.1uF 0.1uF GND L5 VDD_O VDD25 + C84 C86 100uF/16V 0.1uF C87 F.B. 1000pF + C85 C88 100uF/16V 0.1uF C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GND L6 VDD_C VDD18 + C103 C105 100uF/16V 0.1uF C106 F.B. 1000pF + C104 C107 ASIX ELECTRONICS CORPORATION Title 100uF/16V 0.1uF AX88655 P 5-Port 10/100/1000BASE-T EtherNet Switch --- Port 1 G'PHY CKT. GND Size C Date: 32 Document Number Rev 1.0 GPHY1.SCH Thursday, March 14, 2002 Sheet 3 of 10 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch GTX_CLK TXD[0..7] TX_EN MDIO MDC PHY_RST# 25MHZ VDD25 VDD18 CRS COL RXD[0..7] RX_CLK RX_DV TX_CLK PHY ID : 01001 VDD25 VDD18 GND VDD_O GND CRS COL RXD[0..7] RX_CLK RX_DV TX_CLK GTX_CLK TXD[0..7] TX_EN MDIO MDC RESET# 25M_IN PHYADD0 PHYADD1 PHYADD2 PHYADD3 PHYADD4 AN_EN DUPLEX SPEED1 SPEED R85 R86 R87 R88 R89 R90 R91 R92 R93 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k VDD_O PHYADD0 R95 1k D11 LED AN_EN R96 1k D12 LED DUPLEX R98 1k D13 LED SPEED1 R99 1k D14 LED Link Link SPEED R100 1k D15 LED Activity LED R94 4.7K DUPLEX LED VDD_O RESET# R97 VDD_O 2K VDD_O GND R104 RX_DV RXD7 RXD6 RXD5 RXD4 R105 10 RXD3 RXD2 RXD1 RXD0 R109 10 0 VDD_C GND VDD_O GND RX_CLK R112 10 TX_CLK GND R116 R117 10 4.7K VDD_O GND GND VDD_O GND VDD_O GND VDD_C PHYADD3 PHYADD2 GND VDD_O PHYADD1 PHYADD0 GND VDD_C AN_EN DUPLEX SPEED1 SPEED GND GND VDD_C GND GND GND GND VDD_O COL CRS RX_ER IO_VDD VSS RX_DV RXD7 RXD6 RXD5 CORD_VDD VSS RXD4 RXD3 RXD2 IO_VDD VSS RXD1 RXD0 RX_CLK IO_VDD VSS TX_CLK TX_ER TX_EN CORD_VDD VSS RX_VDD25 DP83865AVH VSS MDID_N MDID_P VSS VSS RX_VDD VSS MDIC_N MDIC_P VSS VSS RX_VDD VSS MDIB_N MDIB_P VSS VSS RX_VDD VSS MDIA_N MDIA_P VSS VSS RX_VDD VSS RX_VDD 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 GND MDID_N MDID_P GND GND VDD_C GND MDIC_N MDIC_P GND GND VDD_C GND MDIB_N MDIB_P GND GND VDD_C GND MDIA_N MDIA_P GND GND VDD_C GND VDD_C 0 R124 1.5K C127 0.1uF 0.1uF C125 R102 49.9 0.1uF R106 49.9 C128 R107 49.9 0.1uF RX_VDD25 C129 C130 0.1uF 0.1uF R113 49.9 C131 R114 49.9 0.1uF MDIB_N MDIB_P TF3 1 2 3 4 5 6 7 8 9 10 11 12 TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4- MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4- 24 23 22 21 20 19 18 17 16 15 14 13 R108 MDI_DMDI_D+ R110 MDI_CMDI_C+ R111 MDI_BMDI_B+ R115 MDI_AMDI_A+ 75 12 8 7 6 5 4 3 2 1 11 MDI_DMDI_D+ MDI_BMDI_CMDI_C+ MDI_B+ MDI_AMDI_A+ 75 75 75 JACK3 RJ45_A 24HST1041 C132 0.01uF/2KV C133 C134 0.1uF 0.1uF R118 49.9 C136 0.1uF C137 1000pF C135 R119 49.9 0.1uF MDIA_N MDIA_P R121 4.7K 9.76K R123 22 L7 MDIO C126 R101 49.9 MDIC_N MDIC_P GND VDD_C RX_VDD25 PHYADD4 RX_VDD25 GND VDD_O GND VDD_C GND GND VDD_O TXD7 TXD6 TXD5 TXD4 VDD_O GND TXD3 TXD2 VDD_C GND TXD1 TXD0 VDD_O GND R122 0.1uF RX_VDD25 TXD[0..7] VDD_O C124 0.1uF RX_VDD25 R120 GTX_CLK C123 MDID_N MDID_P 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 TX_EN VDD_C GND 100 LED 10 LED SHIELD 4.7K VSS IO_VDD VSS CORE_VDD VDD_SEL_STRAP /RESET /TRST TDI VSS IO_VDD TDO TMS VSS CORE_VDD TCK RESERVED VSS IO_VDD VSS CORE_VDD PHYADDR3_STRAP PHYADDR2_STRAP VSS IO_VDD PHYADDR1_STRAP PHYADDR0_STRAP /DUPLEX_LED VSS CORE_VDD AN_EN_STRAP /LINK1000_LED LINK100_LED /DUPLEX_STRAP LINK10_LED /SPEED1_STRAP ACTIVITY_LED /SPEED_STRAP TX_TCLK VSS IO_VDD /INTERRUPT RESERVED NON_IEEE_STRAP R103 RXD[0..7] 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TXD7 TXD6 TXD5 TXD4 IO_VDD VSS TXD3 TXD2 CORD_VDD VSS TXD1 TXD0 IO_VDD VSS GTX_CLK MDIO MDC VSS IO_VDD RESERVER CLK_TO_MAC CLK_IN CLK_OUT MAC_CLK_EN_STRAP MDIX_EN_STRAP IO_VDD VSS CORD_VDD VSS MULTI_EN_STRAP PHYADDR4_STRAP AFE_VDD VSS PGM_VDD VSS CORD_VDD BG_VDD BG_REF COL CRS GND Link 1000 LED U3 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND VDD_O GND VDD_C GND OPTION C139 + C138 0.1uF 22uF GND VDD_C F.B. VDD_O VDD_O MDC R125 1.5K Option 25M_IN R126 4.7K RX_VDD25 VDD_O + C140 100uF/16V C141 C142 C143 C144 0.1uF 1000pF 0.1uF 0.1uF GND L8 VDD25 VDD_O + C145 100uF/16V C147 C148 0.1uF 1000pF F.B. + C146 100uF/16V C149 C150 C151 C152 C153 C154 C155 C156 C157 C158 C159 C160 C161 C162 C163 0.1uF 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GND L9 VDD18 VDD_C ASIX ELECTRONICS CORPORATION + C164 100uF/16V C166 C167 0.1uF 1000pF F.B. + C165 100uF/16V C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 C178 C179 C180 C181 C182 C183 0.1uF 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GND Title AX88655 P 5-Port 10/100/1000BASE-T EtherNet Switch --- Port 2 G'PHY CKT. Size C Date: 33 Document Number Rev 1.0 GPHY2.SCH Thursday, March 14, 2002 Sheet 4 of 10 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch GTX_CLK TXD[0..7] TX_EN MDIO MDC PHY_RST# 25MHZ VDD25 VDD18 CRS COL RXD[0..7] RX_CLK RX_DV TX_CLK PHY ID : 01010 VDD25 VDD18 GND VDD_O GND CRS COL RXD[0..7] RX_CLK RX_DV TX_CLK GTX_CLK TXD[0..7] TX_EN MDIO MDC RESET# 25M_IN PHYADD0 PHYADD1 PHYADD2 PHYADD3 PHYADD4 AN_EN DUPLEX SPEED1 SPEED R127 R128 R129 R130 R131 R132 R133 R134 R135 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k PHYADD0 R137 1k D16 AN_EN R138 1k D17 LED DUPLEX R140 1k D18 LED SPEED1 R141 1k D19 LED Link Link SPEED R142 1k D20 LED Activity LED VDD_O R136 4.7K LED DUPLEX LED VDD_O RESET# R139 2K VDD_O RXD[0..7] 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 4.7K VDD_O GND RX_DV R146 RXD7 RXD6 RXD5 RXD4 R147 10 RXD3 RXD2 RXD1 RXD0 R151 10 0 VDD_C GND VDD_O GND R154 TX_CLK GND R158 R159 10 VDD_O GND 10 4.7K TX_EN VDD_C GND GND VDD_O GND VDD_O GND VDD_C PHYADD3 PHYADD2 GND VDD_O PHYADD1 PHYADD0 GND VDD_C AN_EN DUPLEX SPEED1 SPEED GND GND VDD_C GND GND GND GND VDD_O COL CRS RX_ER IO_VDD VSS RX_DV RXD7 RXD6 RXD5 CORD_VDD VSS RXD4 RXD3 RXD2 IO_VDD VSS RXD1 RXD0 RX_CLK IO_VDD VSS TX_CLK TX_ER TX_EN CORD_VDD VSS RX_VDD25 DP83865AVH VSS MDID_N MDID_P VSS VSS RX_VDD VSS MDIC_N MDIC_P VSS VSS RX_VDD VSS MDIB_N MDIB_P VSS VSS RX_VDD VSS MDIA_N MDIA_P VSS VSS RX_VDD VSS RX_VDD 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 GND MDID_N MDID_P GND GND VDD_C GND MDIC_N MDIC_P GND GND VDD_C GND MDIB_N MDIB_P GND GND VDD_C GND MDIA_N MDIA_P GND GND VDD_C GND VDD_C 0 R166 1.5K 0.1uF C187 C188 0.1uF 0.1uF R143 49.9 C186 R144 49.9 0.1uF RX_VDD25 R148 49.9 C189 R149 49.9 0.1uF MDIC_N MDIC_P RX_VDD25 C190 C191 0.1uF 0.1uF R155 49.9 C192 R156 49.9 0.1uF MDIB_N MDIB_P TF4 1 2 3 4 5 6 7 8 9 10 11 12 TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4- MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4- 24 23 22 21 20 19 18 17 16 15 14 13 R150 MDI_DMDI_D+ R152 MDI_CMDI_C+ R153 MDI_BMDI_B+ R157 MDI_AMDI_A+ 75 12 8 7 6 5 4 3 2 1 11 MDI_DMDI_D+ MDI_BMDI_CMDI_C+ MDI_B+ MDI_AMDI_A+ 75 75 75 JACK4 RJ45_A 24HST1041 C193 0.01uF/2KV C194 C195 0.1uF 0.1uF R160 49.9 C197 0.1uF C198 1000pF C196 R161 49.9 0.1uF MDIA_N MDIA_P TXD7 TXD6 TXD5 TXD4 VDD_O GND TXD3 TXD2 VDD_C GND TXD1 TXD0 VDD_O GND R164 R163 4.7K 9.76K GND R165 22 L10 MDIO C185 0.1uF RX_VDD25 TXD[0..7] VDD_O C184 MDID_N MDID_P R162 GTX_CLK 100 LED 10 LED U4 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 GND 82 VDD_O 83 84 85 86 87 88 89 VDD_O 90 GND 91 VDD_C 92 GND 93 94 PHYADD4 95 RX_VDD25 96 GND 97 98 GND 99 VDD_C 100 RX_VDD25 101 102 RX_CLK Link 1000 LED SHIELD R145 TXD7 TXD6 TXD5 TXD4 IO_VDD VSS TXD3 TXD2 CORD_VDD VSS TXD1 TXD0 IO_VDD VSS GTX_CLK MDIO MDC VSS IO_VDD RESERVER CLK_TO_MAC CLK_IN CLK_OUT MAC_CLK_EN_STRAP MDIX_EN_STRAP IO_VDD VSS CORD_VDD VSS MULTI_EN_STRAP PHYADDR4_STRAP AFE_VDD VSS PGM_VDD VSS CORD_VDD BG_VDD BG_REF COL CRS GND 38 VSS 37 IO_VDD 36 VSS 35 CORE_VDD 34 VDD_SEL_STRAP 33 /RESET 32 /TRST 31 TDI 30 VSS 29 IO_VDD 28 TDO 27 TMS 26 VSS 25 CORE_VDD 24 TCK 23 RESERVED 22 VSS 21 IO_VDD 20 VSS 19 CORE_VDD 18 PHYADDR3_STRAP 17 PHYADDR2_STRAP 16 VSS 15 IO_VDD 14 PHYADDR1_STRAP 13 PHYADDR0_STRAP /DUPLEX_LED 12 VSS 11 CORE_VDD 10 AN_EN_STRAP /LINK1000_LED 9 LINK100_LED /DUPLEX_STRAP 8 LINK10_LED /SPEED1_STRAP 7 ACTIVITY_LED /SPEED_STRAP 6 TX_TCLK 5 VSS 4 IO_VDD 3 /INTERRUPT 2 RESERVED 1 NON_IEEE_STRAP GND VDD_O GND VDD_C GND OPTION C200 + C199 0.1uF 22uF VDD_C F.B. VDD_O VDD_O MDC R167 1.5K OPTION 25M_IN R168 4.7K RX_VDD25 VDD_O + C201 C202 100uF/16V 0.1uF C203 C204 C205 1000pF 0.1uF 0.1uF GND L11 VDD25 VDD_O + C206 C208 100uF/16V 0.1uF C209 F.B. 1000pF + C207 C210 100uF/16V 0.1uF C211 C212 C213 C214 C215 C216 C217 C218 C219 C220 C221 C222 C223 C224 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C230 C231 C232 C233 C234 C235 C236 C237 C238 C239 C240 C241 C242 C243 C244 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GND L12 VDD_C VDD18 ASIX ELECTRONICS CORPORATION + C225 C227 100uF/16V 0.1uF C228 F.B. 1000pF + C226 C229 100uF/16V 0.1uF GND Title AX88655 P 5-Port 10/100/1000BASE-T EtherNet Switch --- Port 3 G'PHY CKT. Size C Date: 34 Document Number Rev 1.0 GPHY3.SCH Thursday, March 14, 2002 Sheet 5 of 10 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch GTX_CLK TXD[0..7] TX_EN MDIO MDC PHY_RST# 25MHZ VDD25 VDD18 CRS COL RXD[0..7] RX_CLK RX_DV TX_CLK PHY ID : 01011 VDD25 VDD18 GND VDD_O GND CRS COL RXD[0..7] RX_CLK RX_DV TX_CLK GTX_CLK TXD[0..7] TX_EN MDIO MDC RESET# 25M_IN PHYADD0 PHYADD1 PHYADD2 PHYADD3 PHYADD4 AN_EN DUPLEX SPEED1 SPEED R169 R170 R171 R172 R173 R174 R175 R176 R177 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k VDD_O PHYADD0 R179 1k D21 LED AN_EN R180 1k D22 LED DUPLEX R182 1k D23 LED Link 100 LED SPEED1 R183 1k D24 LED Link 10 LED SPEED R184 1k D25 LED Activity LED R178 4.7K DUPLEX LED VDD_O RESET# R181 2K VDD_O 4.7K VDD_O GND RX_DV R188 RXD7 RXD6 RXD5 RXD4 R189 10 RXD3 RXD2 RXD1 RXD0 R193 10 0 VDD_C GND VDD_O GND RX_CLK R196 10 TX_CLK GND R200 R201 10 4.7K VDD_O GND GND VDD_O GND VDD_O GND VDD_C PHYADD3 PHYADD2 GND VDD_O PHYADD1 PHYADD0 GND VDD_C AN_EN DUPLEX SPEED1 SPEED GND GND VDD_C GND GND GND GND VDD_O COL CRS RX_ER IO_VDD VSS RX_DV RXD7 RXD6 RXD5 CORD_VDD VSS RXD4 RXD3 RXD2 IO_VDD VSS RXD1 RXD0 RX_CLK IO_VDD VSS TX_CLK TX_ER TX_EN CORD_VDD VSS U5 RX_VDD25 DP83865AVH VSS MDID_N MDID_P VSS VSS RX_VDD VSS MDIC_N MDIC_P VSS VSS RX_VDD VSS MDIB_N MDIB_P VSS VSS RX_VDD VSS MDIA_N MDIA_P VSS VSS RX_VDD VSS RX_VDD 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 GND MDID_N MDID_P GND GND VDD_C GND MDIC_N MDIC_P GND GND VDD_C GND MDIB_N MDIB_P GND GND VDD_C GND MDIA_N MDIA_P GND GND VDD_C GND VDD_C 0 R208 1.5K C248 C249 0.1uF 0.1uF R185 49.9 C247 R186 49.9 0.1uF R190 49.9 C250 R191 49.9 0.1uF MDIC_N MDIC_P RX_VDD25 C251 C252 0.1uF 0.1uF R197 49.9 C253 R198 49.9 0.1uF MDIB_N MDIB_P TF5 1 2 3 4 5 6 7 8 9 10 11 12 TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4- MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4- 24 23 22 21 20 19 18 17 16 15 14 13 R192 MDI_DMDI_D+ R194 MDI_CMDI_C+ R195 MDI_BMDI_B+ R199 MDI_AMDI_A+ 75 12 8 7 6 5 4 3 2 1 11 MDI_DMDI_D+ MDI_BMDI_CMDI_C+ MDI_B+ MDI_AMDI_A+ 75 75 75 JACK5 RJ45_A 24HST1041 C254 0.01uF/2KV C255 C256 0.1uF 0.1uF R202 49.9 C258 0.1uF C259 1000pF C257 R203 49.9 0.1uF MDIA_N MDIA_P R205 4.7K R204 9.76K GND R207 22 VDD_C L13 MDIO 0.1uF RX_VDD25 GND VDD_C RX_VDD25 PHYADD4 RX_VDD25 GND VDD_O GND VDD_C GND GND VDD_O TXD7 TXD6 TXD5 TXD4 VDD_O GND TXD3 TXD2 VDD_C GND TXD1 TXD0 VDD_O GND R206 VDD_O C246 0.1uF RX_VDD25 TXD[0..7] GTX_CLK C245 MDID_N MDID_P 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 TX_EN VDD_C GND Link 1000 LED SHIELD R187 RXD[0..7] 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TXD7 TXD6 TXD5 TXD4 IO_VDD VSS TXD3 TXD2 CORD_VDD VSS TXD1 TXD0 IO_VDD VSS GTX_CLK MDIO MDC VSS IO_VDD RESERVER CLK_TO_MAC CLK_IN CLK_OUT MAC_CLK_EN_STRAP MDIX_EN_STRAP IO_VDD VSS CORD_VDD VSS MULTI_EN_STRAP PHYADDR4_STRAP AFE_VDD VSS PGM_VDD VSS CORD_VDD BG_VDD BG_REF COL CRS GND 38 VSS 37 IO_VDD 36 VSS 35 CORE_VDD 34 VDD_SEL_STRAP 33 /RESET 32 /TRST 31 TDI 30 VSS 29 IO_VDD 28 TDO 27 TMS 26 VSS 25 CORE_VDD 24 TCK 23 RESERVED 22 VSS 21 IO_VDD 20 VSS 19 CORE_VDD 18 PHYADDR3_STRAP 17 PHYADDR2_STRAP 16 VSS 15 IO_VDD 14 PHYADDR1_STRAP 13 PHYADDR0_STRAP /DUPLEX_LED 12 VSS 11 CORE_VDD 10 AN_EN_STRAP /LINK1000_LED 9 LINK100_LED /DUPLEX_STRAP 8 LINK10_LED /SPEED1_STRAP 7 ACTIVITY_LED /SPEED_STRAP 6 TX_TCLK 5 VSS 4 IO_VDD 3 /INTERRUPT 2 RESERVED 1 NON_IEEE_STRAP GND VDD_O GND VDD_C GND OPTION C261 + C260 0.1uF 22uF F.B. VDD_O VDD_O MDC R209 1.5K OPTION 25M_IN R210 4.7K RX_VDD25 VDD_O + C262 C263 100uF/16V 0.1uF C264 C265 C266 1000pF 0.1uF 0.1uF GND L14 VDD25 VDD_O + C267 C269 100uF/16V 0.1uF C270 F.B. 1000pF + C268 C271 100uF/16V 0.1uF C272 C273 C274 C275 C276 C277 C278 C279 C280 C281 C282 C283 C284 C285 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C291 C292 C293 C294 C295 C296 C297 C298 C299 C300 C301 C302 C303 C304 C305 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF GND L15 VDD18 VDD_C ASIX ELECTRONICS CORPORATION + C286 C288 100uF/16V 0.1uF C289 F.B. 1000pF + C287 C290 100uF/16V 0.1uF GND Title AX88655 P 5-Port 10/100/1000BASE-T EtherNet Switch --- Port 4 G'PHY CKT. Size C Date: 35 Document Number Rev 1.0 GPHY4.SCH Thursday, March 14, 2002 Sheet 6 of 10 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch RXD0[0..7] CRS0 COL0 RXD0[0..7] RX_CLK0 RX_DV0 TX_CLK0 GND GND 2.5V GCLK SYSCLK GCLK SYSCLK RESET# RESET# MDC MDIO MDC MDIO GND 3.3V X_IN X_OUT GND 2.5VA GND FILTER GND 2.5VA SDC SDIO SDC SDIO VDD33 VDD25 GND VDD33 VDD25_2 GND CRS1 COL1 FILTER RXD1[0..7] R222 680 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15 RXD16 RXD17 RX_CLK1 RX_DV1 GND GTX_CLK1 R224 C306 39pF C307 680pF TXD1[0..7] TX_EN1 R228 0 2.5V TX_CLK1 R225 47 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15 TXD16 TXD17 R226 47 R227 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TXD0[4] TXD0[5] TXD0[6] TXD0[7] TX_EN0 VSS VDD25 NC NC VSS VSS VSS VSS NC NC NC NC VSS VSS VSS NC VDD25 NC NC NC NC NC NC NC NC NC NC VSS VDD33 X_IN X_OUT AVBB25 AVDD25A AVSS25A FILTER AVSS25D AVDD25D NC CRS1 COL1 RXD1[0] RXD1[1] RXD1[2] RXD1[3] RXD1[4] RXD1[5] RXD1[6] RXD1[7] RX_CLK1 RX_DV1 VSS GTX_CLK1 VDD25 TX_CLK1 TXD1[0] TXD1[1] TXD1[2] TXD1[3] TXD1[4] 0 1M Y1 X_IN X_OUT 27MHZ C308 20pF GND 2.5V 2.5V GND GND NC NC NC NC VSS VSS VSS VSS NC NC VDD25 VSS GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 NC NC NC NC VDD33 /RST VSS SYSCLK NC MDC MDIO SDC SDIO VDD25 GCLK VSS VSS /SYSCLK_EN /GCLK_EN SID4 SID3 SID2 SID1 SID0 VDD25 VSS TX_EN4 TXD4[7] TXD4[6] TXD4[5] TXD4[4] TXD4[3] TXD4[2] TXD4[1] TXD4[0] TX_CLK4 VDD25 G_TXCLK4 VSS RX_DV4 RX_CLK4 RXD4[7] RXD4[6] RXD4[5] RXD4[4] RXD4[3] RXD4[2] AX88655 P L16 C309 20pF F.B. L17 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 GND 2.5V GND 3.3V RESET# GND SYSCLK R215 R216 1.5K 1.5K MDC MDIO SDC SDIO 2.5V GCLK GND GND SYSCLK_EN# GCLK_EN# If SYSCLK_EN pull down, the SYSCLK input 90MHZ, else the X_IN & X_OUT input 27MHz. SYSCLK_EN# R217 10K GND GCLK_EN# 10K GND R218 2.5V GND R219 0 TX_EN4 TXD47 TXD46 TXD45 TXD44 TXD43 TXD42 TXD41 TXD40 R223 0 GTX_CLK4 R220 47 R221 47 TXD4[0..7] TX_CLK4 2.5V GND RX_DV4 RX_CLK4 RXD47 RXD46 RXD45 RXD44 RXD43 RXD42 RXD41 RXD40 R235 47 GND 2.5V RXD4[0..7] 0 GND 2.5V CRS4 COL4 R213 47 0 GTX_CLK4 TXD4[0..7] TX_EN4 2.5V R212 47 GTX_CLK3 TXD3[0..7] TX_EN3 GTX_CLK4 TXD4[0..7] TX_EN4 65 TXD1[5] 66 TXD1[6] 67 TXD1[7] 68 TX_EN1 69 VSS 70 VDD25 71 CRS2 72 COL2 73 RXD2[0] 74 RXD2[1] 75 RXD2[2] 76 RXD2[3] 77 RXD2[4] 78 RXD2[5] 79 RXD2[6] 80 RXD2[7] 81 RX_CLK2 82 RX_DV2 83 VSS 84 GTX_CLK2 85 VDD25 86 TX_CLK2 87 TXD2[0] 88 TXD2[1] 89 TXD2[2] 90 TXD2[3] 91 TXD2[4] 92 TXD2[5] 93 TXD2[6] 94 TXD2[7] 95 TX_EN2 96 VSS 97 VDD25 98 CRS3 99 COL3 100 RXD3[0] 101 RXD3[1] 102 RXD3[2] 103 RXD3[3] 104 RXD3[4] 105 RXD3[5] 106 RXD3[6] 107 RXD3[7] 108 RX_CLK3 109 RX_DV3 110 VSS 111 GTX_CLK3 112 VDD25 113 TX_CLK3 114 TXD3[0] 115 TXD3[1] 116 TXD3[2] 117 TXD3[3] 118 TXD3[4] 119 TXD3[5] 120 TXD3[6] 121 TXD3[7] 122 TX_EN3 123 VSS 124 VDD25 125 CRS4 126 COL4 127 RXD4[0] 128 RXD4[1] TXD0[0..7] TXD00 TXD01 TXD02 TXD03 TXD04 TXD05 TXD06 TXD07 TX_EN0 R214 GTX_CLK2 TXD2[0..7] TX_EN2 GTX_CLK3 TXD3[0..7] TX_EN3 2.5V U6 CRS4 COL4 RXD4[0..7] RX_CLK4 RX_DV4 TX_CLK4 CRS4 COL4 RXD4[0..7] RX_CLK4 RX_RV4 TX_CLK4 0 GTX_CLK1 TXD1[0..7] TX_EN1 GTX_CLK2 TXD2[0..7] TX_EN2 TXD32 TXD33 TXD34 TXD35 TXD36 TXD3[0..7]TXD37 R236 TX_EN3 GTX_CLK0 R211 GND 2.5V CRS2 COL2 RXD20 RXD21 RXD22 RXD23 RXD24 RXD25 RXD26 RXD2[0..7] RXD27 RX_CLK2 RX_DV2 GND R229 0 GTX_CLK2 2.5V TX_CLK2 R230 TXD20 47 TXD21 TXD22 TXD23 R231 TXD24 47 TXD25 TXD26 TXD2[0..7]TXD27 R232 0 TX_EN2 GND 2.5V CRS3 COL3 RXD30 RXD31 RXD32 RXD33 RXD34 RXD35 RXD36 RXD3[0..7] RXD37 RX_CLK3 RX_DV3 GND R233 0 GTX_CLK3 2.5V TX_CLK3 R234 TXD30 47 TXD31 CRS3 COL3 RXD3[0..7] RX_CLK3 RX_DV3 TX_CLK3 CRS3 COL3 RXD3[0..7] RX_CLK3 RX_RV3 TX_CLK3 GTX_CLK0 TXD0[0..7] TX_EN0 GTX_CLK1 TXD1[0..7] TX_EN1 256 TXD0[3] 255 TXD0[2] 254 TXD0[1] 253 TXD0[0] 252 TX_CLK0 251 VDD25 250 GTX_CLK0 249 VSS 248 RX_DV0 247 RX_CLK0 246 RXD0[7] 245 RXD0[6] 244 RXD0[5] 243 RXD0[4] 242 RXD0[3] 241 RXD0[2] 240 RXD0[1] 239 RXD0[0] 238 COL0 237 CRS0 236 VDD25 235 VSS 234 NC 233 NC 232 NC 231 NC 230 NC 229 NC 228 NC 227 NC 226 NC 225 NC 224 VDD25 223 NC 222 VSS 221 VSS 220 VSS 219 NC 218 NC 217 NC 216 NC 215 VSS 214 VSS 213 VSS 212 VSS 211 NC 210 NC 209 VDD25 208 VSS 207 NC 206 NC 205 NC 204 NC 203 NC 202 NC 201 NC 200 NC 199 NC 198 NC 197 VDD25 196 NC 195 VSS 194 VSS 193 VSS TX_CLK0 2.5V CRS2 COL2 RXD2[0..7] RX_CLK2 RX_DV2 TX_CLK2 CRS2 COL2 RXD2[0..7] RX_CLK2 RX_RV2 TX_CLK2 GTX_CLK0 TXD0[0..7] TX_EN0 GND RX_DV0 RX_CLK0 RXD07 RXD06 RXD05 RXD04 RXD03 RXD02 RXD01 RXD00 COL0 CRS0 2.5V GND CRS1 COL1 RXD1[0..7] RX_CLK1 RX_DV1 TX_CLK1 CRS1 COL1 RXD1[0..7] RX_CLK1 RX_DV1 TX_CLK1 2.5V CRS0 COL0 RXD0[0..7] RX_CLK0 RX_DV0 TX_CLK0 F.B. L18 VDD25 2.5V + C310 C312 220uF/16V0.1uF C313 F.B. 1000pF + C311 C314 220uF/16V0.1uF C315 C316 C317 C318 C319 C320 C321 C322 C323 C324 C325 C326 C327 C328 C329 C330 C331 C332 1000pF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C345 C346 C347 C348 1000pF 0.1uF 0.1uF GND L19 L20 + C333 C337 100uF/16V0.1uF GND VDD33 2.5VA VDD25 C338 F.B. 1000pF + C334 C339 100uF/16V0.1uF C340 C341 C342 1000pF 0.1uF 0.1uF 3.3V + C335 C343 100uF/16V0.1uF C344 F.B. 1000pF + C336 ASIX ELECTRONICS CORPORATION Title 100uF/16V0.1uF AX88655 P 5-Port 10/100/1000BASE-T EtherNet Switch --- AX88655 P CKT. GND Size C Date: 36 Document Number Rev 1.0 GSW_CKT.SCH Thursday, March 14, 2002 Sheet 7 of 10 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch VDD33 GND VDD33 GND 25M_P0 25M_P1 25M_P2 25M_P3 25M_P4 25M_P0 25M_P1 25M_P2 25M_P3 25M_P4 GCLK SYSCLK U7 L21 VDD33 C349 F.B. 0.1uF U8 OUT 8 C350 0.1uF VCC GCLK SYSCLK GND 5 R237 10 25MHz 25M_P0 25M_P1 GCLK 4 R238 R240 R242 10 10 10 GND 1 2 3 4 REF CLK2 CLK1 GND CLKOUT CLK4 VDD CLK3 8 7 6 5 R239 R241 CLK_VDD1 R243 10 10 25M_P4 25M_P3 10 25M_P2 PLL102_05 125MHz U9 OUT L23 VDD33 8 C351 F.B. 0.1uF C352 0.1uF VCC GND 5 R244 10 L22 SYSCLK VDD33 CLK_VDD1 4 C353 F.B. C354 0.1uF 90MHz GND 0.1uF U10 L24 VDD33 OUT 8 C355 F.B. 0.1uF C356 0.1uF VCC GND 5 R245 10 25MHz 4 25MHZ ASIX ELECTRONICS CORPORATION Title AX88655 P 5-Port 10/100/1000BASE-T EtherNet Switch --- OSC CKT. Size B Date: 37 Document Number Rev 1.0 OSC_CKT.SCH Thursday, March 14, 2002 Sheet 8 of 10 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch VDD33 VDD25 VDD25_2 VDD18_2 VDD18_1 GND RST_CTL# VDD33 VDD25 VDD25_2 VDD18_2 VDD18_1 GND RST_CTL# RST#_P34 RST#_P12 RST#_P0 RST#_SW RST#_P34 RST#_P12 RST#_P0 RST#_SW 5VSB 3.3V 3 VIN TP2 C370 S1 SW SPST 5V 5V 11 12 13 14 15 16 17 18 19 20 3.3V 3.3V -12V 3.3V GND GND PS-ON 5V GND GND GND 5V GND GND -5V PW_OK 5V 5VSB 5V 12V 3.3V 3.3V GND 5V GND 5V GND 1 2 3 4 5 6 7 8 9 10 1N5402 C366 C367 C368 C369 1000pF 0.1uF 1000pF 0.1uF + C365 + C357 5V INPUT TEST POINT C359 C360 0.1uF GND TAB/OUT VOUT ADJ/GND 4 2 1 1000pF 680 R248 301 220uF/16V 220uF/16V TP1 VDD18_1 R246 + C358 LT1085 C361 C362 0.1uF 1000pF C363 1 C364 1 GND TEST POINT 220uF/16V TP4 GND 1 1.8V Output TEST POINT TP3 1000pF 0.1uF GND TEST POINT 5V Power LED 5VSB 12V D27 LED C372 C373 C374 C375 1000pF 0.1uF 1000pF 0.1uF 3.3V + 3 R250 1K 220uF/16V VDD18_2 U13 C371 ATX POWER + C376 GND GND C378 C379 0.1uF 1000pF VIN TAB/OUT VOUT ADJ/GND 4 2 1 TP5 VDD18_2 R251 680 + C377 R252 LT1085 301 220uF/16V C380 C381 C382 C383 0.1uF 1000pF 0.1uF 1000pF 1 1.8V Output TEST POINT TP6 1 GND TEST POINT 220uF/16V R253 100/2W U14 5V J1 3 TP8 3.3V 1 2 D28 C393 C394 C395 C396 + C392 C397 CON2 1N5402 0.1uF 1000pF 0.1uF 1000pF 0.1uF C399 C400 C401 C402 1000pF 0.1uF 1000pF 0.1uF + C384 3.3V 1 INPUT TEST POINT GND C386 C387 0.1uF 1000pF VIN TAB/OUT VOUT ADJ/GND 4 2 1 TP7 VDD25_2 R254 1K R255 1K + C385 LT1085 220uF/16V 220uF/16V GND C388 C389 C390 C391 0.1uF 1000pF 0.1uF 1000pF 220uF/16V 1 2.5V Output TEST POINT TP9 1 GND TEST POINT TP10 GND 1 TEST POINT VDD25 3.3V Power LED U15 D29 LED 5V C398 + 3 R257 1K 220uF/16V GND + C403 GND C405 C406 C407 0.1uF 1000pF 1000pF TAB/OUT VOUT ADJ/GND VIN 4 2 1 TP11 VDD25 LT1085 R256 1K R258 1K + C404 220uF/16V C408 C409 C410 C411 0.1uF 1000pF 0.1uF 1000pF 220uF/16V 1 2.5V TEST POINT TP12 Output 1 GND TEST POINT VDD33 TP13 TEST POINT VDD25 1 + C412 C414 + C413 C415 220uF/16V0.1uF 220uF/16V0.1uF R259 VDD33 VDD33 C416 TP14 1000pF 1 GND TEST POINT VDD33 GND PS_ON GND GND GND 100 0.1uF 3.3V 1 D26 U16A C417 0.1uF 14 1N4148 15 CEXT R261 4.7K R260 U17A VDD33 1 2 10K VDD33 VDD33 RST#_SW 100K D30 GND VDD33 VDD33 R264 1 2 3 10K 14 REXT/CEXT A B CLR Q Q RST_CTL# R263 13 0 U18A U17B 3 4 R265 0 C418 0.1uF 74HC04 1 3 4 RST#_P0 2 74HC04 74HC123 7 VDD33 U17C 74HC00 5 6 RST#_P12 S2 Option C419 0.1uF VDD33 SW PUSHBUTTON 74HC04 C420 0.1uF U17D C421 0.1uF 9 8 RST#_P34 74HC04 U17E VDD33 R249 5V U12 VDD18_1 U11 5V R247 4.7K VDD33 11 10 74HC04 R268 10K U19 3 2 VIN VOUT VSS R269 0 1 XC61F C422 0.1uF + C423 4.7uF/16V VDD33 Option for external RC reset IC C424 0.1uF ASIX ELECTRONICS CORPORATION Title AX88655 P 5-Port 10/100/1000BASE-T EtherNet Switch --- Power Input CKT. Size C Date: 38 Document Number POWER_CKT.SCH Thursday, March 14, 2002 Rev 1.0 Sheet 9 of 10 ASIX ELECTRONICS CORPORATION AX88655 P 5-Port 10/100/1000BASE-T Ethernet Switch RST_CTL# VDD33 SDIO SDC U20 VDD33 VDD33 VDD33 R270 4.7K R271 4.7K R272 4.7K 14 U18B 14 U18C STROB# 4 9 6 INIT# 8 2 5 9 12 RST_CTL# SDIO RST_CTL# 1 4 10 13 VDD33 14 5 7 1A 2A 3A 4A 1Y 2Y 3Y 4Y 3 6 8 11 SDIO BUSY SDC 1OE 2OE 3OE 4OE VCC 74HC00 74HC00 C425 0.1uF GND 7 PD0 GND PD2 GND RST_CTL# 10 GND SDIO SDC RST_CTL# VDD33 GND VDD33 VDD33 GND 74HC125 VDD33 VDD33 C426 0.1uF U21 R279 R281 R282 0 0 0 GND 1 2 3 4 A0 VCC A1 WP A2 SCL GND SDA R274 4.7K 8 7 6 5 R275 4.7K R276 4.7K VDD33 RST_CTL# SDC SDIO J2 STROB#(I) PD0(I) STROB# PD0 R273 R277 100 100 PD2(I) PD2 R280 100 BUSY(O) BUSY R283 100 AT24C16B (SEEPROM) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 R278 100 INIT# INIT#(I) PRINT_PORT ASIX ELECTRONICS CORPORATION Title AX88655 P 5-Port 10/100/1000BASE-T EtherNet Switch ---Serial EEPROM CKT. Size B Date: 39 Document Number Rev 1.0 ROM_CKT.SCH Thursday, March 14, 2002 Sheet 10 of 10 ASIX ELECTRONICS CORPORATION ASIX Electronic Revision history Revision V. 1.0 Date 3/14/02 Comment Initial release. 4F, NO.8, HSIN ANN RD., SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C. TEL: 886-3-5799500 FAX: 886-3-5799558 Email: [email protected] Web: http://www.asix.com.tw 40 http://www.asix.com.tw