Datasheet 1A Variable Output LDO Regulator BD00HC0WEFJ ●General Description BD00HC0WEFJ is a LDO regulator with output current 1.0A. The output accuracy is ±1% of the output voltage. The output voltage of the variable output voltage device can be varied from 0.8 to 7.0V using external resistors. It has a package type: HTSOP-J8 (4.90mm x 6.00mm x 1.00mm), and can be used in a wide variety of digital appliances. The device has built in over current protection to protect the device when output is shorted, 0µA shutdown mode and thermal shutdown circuit to protect the device during over load conditions. The LDO regulator is usable with ceramic capacitors that enable a smaller layout and longer life. ●Features ■ +/-1% output voltage accuracy ■ Built-in Over Current Protection circuit (OCP) ■ Built-in Thermal Shut Down circuit (TSD) ■ Zero µA Shutdown mode ●Key Specifications Input Power Supply Voltage range: Output voltage range: Output current: Shutdown current: Operating temperature range: ●Package HTSOP-J8 (Typ.) (Typ.) (Max.) 4.90mm x 6.00mm x 1.00mm 4.5V to 8.0V 0.8V to 7.0V 1.0A (Max.) 0μA(Typ.) -25℃ to +85℃ HTSOP-J8 ●Typical Application Circuit VCC VO CIN COUT R1 FB EN GND R2 FIN CIN,COUT : Ceramic Capacitor ●Ordering Information B Part Number D 0 0 H C 0 W E F J - Output voltage Input voltage range Output current Shutdown mode 00 : Variable H:10V C0:1.0A “W”:Included EFJ:HTSOP-J8 ○Product structure:Silicon monolithic integrated circuit www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・14・001 Package E2 Packaging and forming specification E2:Emboss tape reel ○This product is not designed protection against radioactive rays. 1/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ ●Block Diagram BD00HC0WEFJ GND VCC SOFT START VO FB EN Fig.1 Block Diagram ●Pin Configuration TOP VIEW VO VCC FB N.C. GND N.C. N.C. EN ●Pin Description Pin No. 1 2 3 4 5 6 7 8 Reverse Pin name VO FB GND N.C. EN N.C. N.C. VCC FIN Pin Function Output pin Feedback pin GND pin No Connect (Connect to GND or leave OPEN) Enable pin No Connect (Connect to GND or leave OPEN) No Connect (Connect to GND or leave OPEN) Input pin Substrate (Connect to GND) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 2/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ ●Absolute Maximum Ratings (Ta=25℃) Parameter Symbol Power supply voltage VCC EN voltage VEN Power dissipation HTSOP-J8 Pd *2 Operating Temperature Range Topr Storage Temperature Range Tstg Junction Temperature Tjmax Ratings 10.0 *1 10.0 2110 *2 -25 to +85 -55 to +150 +150 Unit V V mW ℃ ℃ ℃ *1 Not to exceed Power dissipation(Pd) *2 Reduced by 16.9mW/℃ for each increase in Ta of 1℃ over 25℃. (when mounted on a board 70mm×70mm×1.6mm glass-epoxy board, two layer) ●Recommended Operating Ratings (Ta=25℃) Parameter Input power supply voltage EN voltage Output voltage setting range Output current Symbol VCC VEN VO IO Ratings Min. 4.5 0.0 0.8 0.0 Max. 8.0 8.0 7.0 1.0 Unit V V V A ●Electrical Characteristics (Unless otherwise noted, Ta=25℃, EN=3V, VCC=6V, R1=43kΩ, R2=8.2kΩ) Limits Parameter Symbol Unit Conditions Min. Typ. Max. Circuit current at shutdown mode ISD 0 5 μA VEN=0V, OFF mode Bias current ICC 600 900 μA Line regulation Reg.I -1 1 % VCC=( VO+0.92V )→8.0V Load regulation Reg IO -1.5 1.5 % IO=0→1.0A Minimum dropout voltage1 VCO1 0.15 0.23 V VCC=5V, IO =250mA Minimum dropout voltage2 VCO2 0.30 0.46 V VCC=5V, IO =500mA Minimum dropout voltage3 VCO3 0.45 0.69 V VCC=5V, IO =750mA Minimum dropout voltage4 VCO4 0.60 0.92 V VCC=5V, IO =1.0A Output reference voltage VFB 0.792 0.800 0.808 V IO=0mA EN Low voltage VEN (Low) 0 0.8 V EN High voltage VEN (High) 2.4 8.0 V EN Bias current IEN 1 3 9 μA www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 3/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ ●Typical Performance Curves (Unless otherwise noted, Ta=25℃, EN=3V, VCC=6V, R1=43kΩ, R2=8.2kΩ) VO VO IO IO Fig.2 Transient Response (0→1A) Co=1µF Fig.3 Transient Response (1→0A) Co=1µF VEN VEN VCC VCC VO VO Fig.5 OFF sequence 1 Co=1µF Fig.4 Input sequence 1 Co=1µF www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 4/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ VEN VEN VCC VCC VO VO Fig.7 OFF sequence 2 Co=1µF VO[V] ICC[µA] Fig.6 Input sequence 2 Co=1µF Ta[℃] Ta[℃] Fig.8 Ta-VO (IO=0mA) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 Fig.9 Ta-ICC 5/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet ISD[µA] IEN[µA] BD00HC0WEFJ Ta[℃] Ta[℃] Fig.11 Ta-IEN VO[V] ISD [µA] Fig.10 Ta-ISD (VEN=0V) IO[A] VCC[V] Fig.12 IO-VO Fig.13 VCC-IISD (VEN=0V) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 6/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet VO[V] VO[V] BD00HC0WEFJ Ta[℃] VCC[V] Fig.15 TSD (IO=0mA) VO[V] Fig.14 VCC-VO (IO=0mA) IO[A] Ta[℃] Fig.16 OCP www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 Fig.17 Minimum dropout Voltage (VCC=5V、IO=-1A) 7/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet ICC[mA] BD00HC0WEFJ IO[A] IO[A] Fig.19 IO-ICC Vdrop [V] Fig.18 ESR condencer IO[A] IO [A] Fig.20 PSRR(IO=0mA) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 Fig.21 Minimum dropout Voltage 2 (VCC=4.5V、Ta=25℃) 8/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet Vdrop [V] Vdrop Vdrop[V] [V] BD00HC0WEFJ [A] IOIO[A] IO[A] Io[A] Fig.23 Minimum dropout Voltage 4 (VCC=8V、Ta=25℃) Fig.22 Minimum dropout Voltage 3 (VCC=6V、Ta=25℃) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 9/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ ●Power Dissipation ◎HTSOP-J8 4.0 Power Dissipation :Pd [W] ⑤3.76W Measurement condition: mounted on a ROHM board, Substrate size: 70mm×70mm×1.6mm (Substrate with thermal via) ・Solder the thermal pad to Ground 3.0 ① IC only θj-a=249.5℃/W ② 1-layer(copper foil are :0mm×0mm) θj-a=153.2℃/W ③ 2-layer(copper foil are :15mm×15mm) θj-a=113.6℃/W ④ 2-layer(copper foil are :70mm×70mm) θj-a=59.2℃/W ⑤ 4-layer(copper foil are :70mm×70mm) θj-a=33.3℃/W ④2.11W 2.0 ③1.10W 1.0 ②0.82W ①0.50W 0 0 25 50 75 100 125 150 Ambient 周囲温度:Ta Temperature [℃] :Ta [℃] Thermal design should ensure operation within the following conditions. Note that the temperatures listed are the allowed temperature limits and thermal design should allow sufficient margin beyond these limits. 1. Ambient temperature Ta can be no higher than 85℃. 2. Chip junction temperature (Tj) can be no higher than 150℃. Chip junction temperature can be determined as follows: Calculation based on ambient temperature (Ta) Tj=Ta+θj-a×W <Reference values> θj-a: HTSOP-J8 153.2℃/W 1-layer substrate (copper foil density 0mm×0mm) 113.6℃/W 2-layer substrate (copper foil density 15mm×15mm) 59.2℃/W 2-layer substrate (copper foil density 70mm×70mm) 4-layer substrate (copper foil density 70mm×70mm) 33.3℃/W Substrate size: 70mm×70mm×1.6mm (substrate with thermal via) Most of the heat loss that occurs in the BD00HC0WEFJ is generated from the output Pch FET. Power loss is determined by the total VCC-VO voltage and output current. Be sure to confirm the system input and output voltage as well as the output current conditions in relation to the heat dissipation characteristics of the VCC and VO in the design. Bearing in mind that heat dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the BD00HC0WEFJ make certain to factor conditions such as substrate size into the thermal design. Power consumption [W] = Input voltage (VCC) - Output voltage (VO) ×IO (Ave) Example) Where VCC=5.0V, VO=3.3V, IO(Ave) = 0.5A, Power consumption [W] = 5.0V - 3.3V ×0.5A =0.85[W] www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 10/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ ●Input-to-Output Capacitor It is recommended that a capacitor (over 1uF) is placed near pins between the input pin and GND as well as the output pin and GND. A capacitor, between input pin and GND, is valid when the power supply impedance is high or trace is long. Also, as for the capacitor between the output pin and GND, the greater the capacitance, the more sustainable the line regulation will be and the capacitor will make improvements of characteristics depending on the load. However, please check the actual functionality of this part by mounting it on a board for the actual application. Ceramic capacitors usually have different, thermal and equivalent series resistance characteristics, and moreover capacitance decreases gradually in use. For additional details, please check with the manufacturer, and select the best ceramic capacitor for your application. 10 Rated Voltage:10V B1 characteristics Rated Voltage:10V B characteristics 0 Capacitance Change [%] -10 Rated Voltage:6.3V B characteristics -20 -30 -40 -50 Rated Voltage:10V F characteristics -60 Rated Voltage:4V X6S characteristics -70 -80 -90 -100 0 1 2 3 4 DC Bias Voltage [V] Ceramic capacitor capacity – DC bias characteristics (Characteristics example) 10.00 1.00 Safety Area ESR [Ω] ●Equivalent Series Resistance ESR (Output capacitor) To prevent oscillations, please attach a capacitor between VO and GND. Capacitors usually have ESR (Equivalent Series Resistance). Operation will be stable in the ESR-IO range shown to the right. Ceramic, tantalum and electrolytic Capacitors have different ESR values, so please ensure that you are using a capacitor that operates in the stable operating region shown on the right. Finally, please evaluate in the actual application. 0.10 CO=1μF 0.01 0 0.2 0.4 0.6 0.8 1 Io [A] ESR – IO characteristics www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 11/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ ●Evaluation Board Circuit U1 C3 C7 1 VCC VO 8 C2 C6 R1 C5 2 FB N.C 7 GND N.C 6 C1 R2 Vcc GND 3 SW1 VO 4 N.C. EN EN 5 FIN ●Evaluation Board Parts List Designation R1 R2 R3 R4 R5 R6 C1 C2 C3 Value 43kΩ 8.2kΩ ‐ ‐ ‐ ‐ 1μF ‐ ‐ Part No. MCR01PZPZF4302 MCR01PZPZF8201 ‐ ‐ ‐ ‐ CM105B105K16A ‐ ‐ Company Designation ROHM C4 ROHM C5 ‐ C6 ‐ C7 ‐ C8 ‐ C9 KYOCERA C10 U1 U2 Value ‐ 1μF Part No. ‐ CM105B105K16A Company ‐ KYOCERA ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ ‐ BD00HC0WEFJ ‐ ‐ ‐ ‐ ‐ ROHM ‐ ●Board Layout EN GND CIN VCC ( VIN ) R1 R2 COUT VO PCB layout considerations: ・Input capacitor CIN connected to VCC (Vin) should be placed as close to VCC(VIN) pin as possible. Output capacitor COUT also should be placed as close to IC pin as possible. In case the part is connected to inner layer GND plane, please use several through holes. ・FB pin has comparatively high impedance and can be affected by noise, so stray capacitance should be as small as possible. Please take care of this during layout. ・Please make GND pattern wide enough to handle thermal dissipation. ・For output voltage setting Output voltage can be set by FB pin voltage(0.800V typ.)and external resistance R1, R2. VO = VFB× R1+R2 R2 (The use of resistors with R1+R2=1k to 90k is recommended) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 12/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ ●I/O Equivalent Circuits 8pin(VCC) / 1pin(VO) 8pin(VCC) 2pin(FB) 5pin(EN) VCC 4pin(FB) VCC 5pin(EN) 1pin(VO) www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 13/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ ●Operational Notes (1) Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the device, thus making it impossible to identify the damage mode, such as a short circuit or an open circuit. If there is any possibility of exposure over the rated values, please consider adding circuit protection devices such as fuses. (2) Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage the IC. Take precautions when connecting the power supply lines. An external direction diode can be added. (3) Power supply lines Design the PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and GND terminal. When using electrolytic capacitors in a circuit, note that capacitance values are reduced at low temperatures and over time. (4) GND voltage The potential of the GND pin must be minimum potential under all operating conditions. (5) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. (6). Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. (7). Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. (8). ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. (9). Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. BD00HC0WEFJ TSD ON Temperature[℃] (typ.) 175 Hysteresis Temperature [℃] 15 (typ.) (10). Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC’s power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 14/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ (11). Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used. Resistor Transistor (NPN) Pin B Pin A C B Pin B E Pin A N N N P+ P+ P N Parasitic element P+ P substrate Parasitic element GND B N P+ P N C E P substrate Parasitic element GND GND GND Parasitic element Other adjacent elements (12). Ground Wiring Pattern. When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 15/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ ●Physical Dimension Tape and Reel Information HTSOP-J8 <Tape and Reel information> 4° (2.4) 3.9±0.1 6.0±0.2 8 7 6 5 +6° −4° 1 1.05±0.2 (3.2) 0.65±0.15 4.9±0.1 (MAX 5.25 include BURR) Tape Embossed carrier tape Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) 2 3 4 1PIN MARK +0.05 0.17 -0.03 1.0MAX 0.545 S 0.08±0.08 0.85±0.05 1.27 +0.05 0.42 -0.04 0.08 M 0.08 S 1pin (Unit : mm) Reel Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. ●Marking Diagram HTSOP-J8(TOP VIEW) Part Number Marking 0 0 H C 0 W LOT Number 1PIN MARK www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 16/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet BD00HC0WEFJ ●Revision History Date Revision 28.May.2012 17.Jan.2013 001 002 Changes New Release The description was modified. www.rohm.com © 2013 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 17/17 TSZ02201-0R6R0A600060-1-2 17.Jan.2013 Rev.002 Datasheet Notice ●General Precaution 1) Before you use our Products, you are requested to carefully read this document and fully understand its contents. ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any ROHM’s Products against warning, caution or note contained in this document. 2) All information contained in this document is current as of the issuing date and subject to change without any prior notice. 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The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3) Our Products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any special or extraordinary environments or conditions. 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Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7) De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual ambient temperature. 8) Confirm that operation temperature is within the specified range described in the product specification. 9) ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Notice - Rev.004 © 2013 ROHM Co., Ltd. All rights reserved. Datasheet ●Precaution for Mounting / Circuit board design 1) When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2) In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification ●Precautions Regarding Application Examples and External Circuits 1) If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2) You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use. Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. 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It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3) Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4) Use Products within the specified time after opening a humidity barrier bag. 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ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or concerning such information. 2) This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 3) The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 4) In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 5) The proper names of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties. Notice - Rev.004 © 2013 ROHM Co., Ltd. All rights reserved.