ROHM BD6721FS_1

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STRUCTURE
Silicon Monolithic Integrated Circuit
PRODUCT SERIES
Single-Phase Full-Wave Motor Driver for Fan Motor
TYPE
BD6721FS
FEATURES
Speed controllable by DC / PWM input
Current limit circuit
PWM soft switching drive
〇ABSOLUTE MAXIMUM RATINGS
Symbol
Limit
Parameter
Supply voltage
20
Vcc
812.5*
Power dissipation
Pd
-40~+100
Operating temperature
Topr
-55~+150
Storage temperature
Tstg
1.0**
Output current
Iomax
IFG
10
FG signal output current
VFG
20
FG signal output voltage
IAL
10
AL signal output current
VAL
20
AL signal output voltage
IVREF
8
VREF current ability
Tjmax
150
Junction temperature
*
Reduce by 6.5mW/℃ over Ta=25℃.
(On 70.0mm×70.0mm×1.6mm glass epoxy board)
** This value is not to exceed Pd.
Unit
V
mW
℃
℃
A
mA
V
mA
V
mA
℃
〇OPERATING CONDITIONS
Parameter
Operating supply voltage range
Hall input voltage range
VTH input voltage range
VMIN input voltage range
Symbol
Vcc
VH
VVTH
VVMIN
*This product is not designed for production against radioactive rays.
*This document may be strategic data subject to COCOM regulations.
REV. D
Limit
4.5~17.0
0~Vcc-2.0
0~Vcc-2.0
0~Vcc-2.0
Unit
V
V
V
V
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〇ELECTRICAL CHARACTERISTICS (Unless otherwise specified Ta=25℃,Vcc=12V)
Limit
Typ.
7.0
±10
Max.
10.0
±15
Unit
Icc
VHYS
Min.
4.0
±5
VO
-
0.6
0.9
V
Lock detection ON time
Lock detection OFF time
TON
TOFF
0.3
3.0
0.5
5.0
0.7
7.0
s
s
FG output low voltage
VFGL
-
0.15
0.3
V
IFG=5mA
FG output leak current
IFGL
-
-
50
μA
VFG=17V
AL output low voltage
VALL
-
0.15
0.3
V
IAL=5mA
AL output leak current
IALL
-
-
50
μA
VAL=17V
OSC low voltage
OSC high voltage
OSC charge current
OSC discharge current
Level amp gain
Level amp output low voltage
VOSCL
VOSCH
ICOSC
IDOSC
GLA
VLAOL
0.8
2.3
-50
26
50
-
1.0
2.5
-32
32
0.2
1.2
2.7
-26
50
0.3
V
V
μA
μA
dB
V
Level amp output high voltage
VLAOH
-
1.6
2.0
V
Output ON duty 1
DUTY1
85
90
95
%
Output ON duty 2
DUTY2
45
50
55
%
Output ON duty 3
DUTY3
5
10
15
%
VREF voltage
VREF
2.8
3.0
3.2
V
Current limit voltage
VTH bias current
VMIN bias current
VCL
IVTH
IVMIN
290
-
310
-
330
0.2
0.2
mV
μA
μA
Parameter
Circuit current
Hall input hysteresis
Output voltage
Symbol
REV. D
Conditions
mA
mV
Io=300mA
Upper and Lower total
Voltage between
LAOUT and Vcc
VTH=VREF*0.383
OUT=Pull down 1kΩ
COSC=470pF
VTH=VREF*0.583
OUT=Pull down 1kΩ
COSC=470pF
VTH=VREF*0.783
OUT=Pull down 1kΩ
COSC=470pF
IVREF=-2mA
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〇PACKAGE OUTLINES
6.6±0.2
9
0.3Min.
6.2±0.3
1.5±0.1
4.4±0.2
0.11
16
BD6721
1
8
0.15±0.1
Lot No.
0.1
0.8
0.36±0.1
SSOP-A16 (UNIT:mm)
〇BLOCK DIAGRAM
〇TERMINAL NAME
GND
AL
COSC
1
VREF
2
+
LAOUT
-
3
+
4
LEVEL AMP
5
VMIN
TSD
VREF
VMIN
PWM COMP
14
LOCK
PROTECTION
H13
CONTROL
LOGIC
-
+
H+
HALL COMP
PRE
DRIVER
+
-
7
12
Vcc
Vcc
6
OUT1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FG
15
VTH
PWMCOMP
-
LAIN
VTH
SIGNAL
OUTPUT
SOFT
SWITCH
COSC
PIN No.
16
11
CURRENT LIMIT
COMP
+
-
CS
10
RNF
OUT2
8
9
REV. D
Terminal
name
GND
COSC
LAOUT
LAIN
VTH
VMIN
OUT1
RNF
OUT2
CS
VCC
H+
HVREF
FG
AL
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〇CAUTIONS ON USE
1) Absolute maximum ratings
An excess in the absolute maximum rations, such as supply voltage, temperature range of operating conditions, etc., can break
down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated
values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.
2) Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An
external direction diode can be added.
3) Power supply line
Back electromotive force causes regenerated current to power supply line, therefore take a measure such as placing a capacitor
between power supply and GND for routing regenerated current. And fully ensure that the capacitor characteristics have no problem
before determine a capacitor value. (when applying electrolytic capacitors, capacitance characteristic values are reduced at low
temperatures)
4) GND potential
The potential of GND pin must be minimum potential in all operating conditions. Also ensure that all terminals except GND terminal
do not fall below GND voltage including transient characteristics. However, it is possible that the motor output terminal may deflect
below GND because of influence by back electromotive force of motor. Malfunction may possibly occur depending on use condition,
environment, and property of individual motor. Please make fully confirmation that no problem is found on operation of IC.
5) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation(Pd) in actual operating conditions.
6) Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error
or if pins are shorted together.
7) Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
8) ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum rations or ASO.
9) Thermal shut down circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). Operation temperature is 175℃(typ.) and has a hysteresis width
of 25℃(typ.). When IC chip temperature rises and TSD circuit works, the output terminal becomes an open state. TSD circuit is
designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not
continue to use the IC after operation this circuit or use the IC in an environment where the operation of this circuit is assumed.
10) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always
discharge capacitors after each process or step. Always turn the IC’s power supply off before connecting it to or removing it from a
jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution
when transporting or storing the IC.
11) GND wiring pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single
ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large
currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external
components, either.
12) Capacitor between output and GND
When a large capacitor is connected between output and GND, if Vcc is shorted with 0V or GND for some cause, it is possible that
the current charged in the capacitor may flow into the output resulting in destruction. Keep the capacitor between output and GND
below 100uF.
13) IC terminal input
When Vcc voltage is not applied to IC, do not apply voltage to each input terminal. When voltage above Vcc or below GND is
applied to the input terminal, parasitic element is actuated due to the structure of IC. Operation of parasitic element causes mutual
interference between circuits, resulting in malfunction as well as destruction in the last. Do not use in a manner where parasitic
element is actuated.
REV. D
Appendix
Notes
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upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
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Appendix-Rev4.0