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STRUCTURE
Silicon monolithic integrated circuit
PRODUCT SERIES
Motor driver for ink jet printer
(H-bridge driver 2ch, switching regulator 1ch, reset output)
TYPE
BD64560EUV
FUNCTION
・External reset input terminal function
・Built-in thermal shut down circuit
・Built-in UVLO circuit
○Absolute maximum ratings (Ta=25℃)
Parameter
Supply voltage
Logic input voltage
RNF voltage (DC)
Symbol
VM
VL
VRNF(DC)
Limit
Unit
-0.4～40.0
V
-0.4～5.5
V
0.5
V
1
1.70※
W
Power dissipation
Pd
4.32※2
Operating temperature range
Topt
-25～+85
℃
Storage temperature range
Tstg
-55～+150
℃
Junction temperature
Tjmax
150
℃
Motor driver maximum output current (peak500ns)
Iout(peak)
8.0
A
Motor driver maximum output current (DC)
Iout(DC)
2.5※3
A
Switching Reg maximum output current (DC)
Iout
1.5
A
※1
70mm×70mm×1.6mm glass epoxy board. Derating in done at 13.6mW/℃ for operating above Ta=25℃.
※2
4-layer recommended board. Derating in done at 34.6mW/℃ for operating above Ta=25℃.
※3
Do not, however exceed Pd, ASO and Tjmax=150℃.
○Recommended operating conditions (Ta= -25～+85℃)
Parameter
Symbol
Supply voltage
VM
CLK input frequency
fCLK
Switching Reg output voltage range
VOUT
Limit
7～36
1～25
1～VM×0.5
This product isn't designed for protection against radioactive rays.
Status of this document
The Japanese version of this document is the formal specification.
A customer may use this translation version only for a reference to help reading the formal version.
If there are any differences in translation version of this document, formal version takes priority.
REV. A
Unit
V
MHz
V
2/4
○Electrical characteristics (Unless otherwise specified, Ta=25℃, VＭ=32V)
Parameter
Symbol
Min.
Limit
Typ.
Max.
Unit
Conditions
Overall
SLEEP=L
SWREG=OFF
SLEEP=H
VM current 2
IM2
15
mA
SWREG=Max Duty
Control logic (C_SELECT, IRT, SLEEP, STROBE/ENABLE_A, CLK/PHASE_A, DATA/PHASE_B, ENABLE_B)
High input voltage
VLINH
2.0
5.5
V
VM current 1
Low input voltage
Input current
C_SELECT Low input voltage
C_SELECT Middle input voltage
C_SELECT High input voltage
C_SELECT input current
IRT High input voltage
IRT Low input voltage
IRT input current
H bridge
Output on resistance (High side)
IM1
-
-
2
mA
VLINL
ILIN
VCSELL
VCSELM
VCSELH
ICSEL
VIRTH
VIRTL
IIRT
0
15
0
1.20
2.5
-45
2.0
0
-50
33
1.65
3.3
-33
-33
0.8
50
0.8
2.10
-21
5.5
0.8
-15
V
uA
V
V
V
uA
V
V
uA
Input voltage=3.3V
C_SELECT=0V
IRT=0V
RONH
-
0.70
0.84
Ω
IOUT=1A
Output on resistance (Low side)
RONL
-
0.50
0.60
Ω
IOUT=1A
Output leak current (High side)
ILEAKH
-1
-
1
uA
VM=40V、OUTxx=0V
Output leak current (Low side)
ILEAKL
-1
-
1
uA
VM=OUTxx=40V
IRNF
10
20
30
uA
RNF pin outflow current
VREF-RNF offset voltage
VREF=2V
GAIN=1/10 or 1/20
※VOFST={(VREF×GAIN－RNF threshold voltage) / (VREF×GAIN)}×100%
VVREF
0.8
3.0
V
IVREF
-1
0
1
uA VREF=2V
VUVLOH
13.5
15.0
16.5
V
VUVLOL
12.5
14.0
15.5
V
VOFST
-5
0
5
%
FB threshold voltage
VFB
0.873
0.900
0.927
V
FB pin outflow current
IFB
-1
0
1
uA
RONSW
ILEAKSW
VFBOVP
VFBUVP
-1
1.10
0.55
0.70
0
1.20
0.60
0.84
1
1.30
0.65
Ω
uA
V
V
IOUT=0.5A
VM=40V、SWOUT=0V
Disabled at turn on
Disabled at turn on
VORT
-
-
0.4
V
IDRAIN=5mA
VREF voltage range
VREF pin outflow current
High motor UVLO voltage
Low motor UVLO voltage
Switching regulator
Output on resistance
Leak current
FB over voltage protection
FB under voltage protection
ORT pin
Output voltage
Leak current
VM threshold voltage
L_OUT pin
Output voltage
Leak current
ILEAKORT
-1
0
1
uA
VPOR
5.9
6.3
6.7
V
No hysteresis
VLOUT
-
-
0.5
V
IDRAIN=5mA
ILEAKLOUT
-1
0
1
uA
REV. A
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○Package outline
Product
No.
BD64560EUV
Lot No.
HTSSOP-C48 (Unit:mm)
○Block diagram
C_SELECT
3.3V(internal regulator)
VREF
Logic input
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SWREG
5
Control logic
POR
Ach
Bch
H-Bridge
H-Bridge
VREF
OSC
VREF
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
○Pin No. / Pin name
Pin
Pin name
No.
1
LGND
2
Pin
No.
48
TEST2
C_SELECT
47
NC
3
CC
46
TEST1
4
IRT
45
NC
5
ORT
44
VMSW
6
VREFA
43
VMSW
7
VREFB
42
NC
8
SLEEP
41
SWOUT
9
STROBE
/ENABLE_A
40
NC
10
CLK
/PHASE_A
39
FB
11
DATA
/PHASE_B
38
AGND
12
ENABLE_B
37
NC
13
L_OUT
36
NC
14
TJMON
35
VM
15
NC
34
NC
16
OUTAM
33
OUTBM
17
NC
32
NC
18
VMA
31
VMB
19
VMA
30
VMB
20
NC
29
NC
21
RNFA
28
RNFB
22
RNFA
27
RNFB
23
NC
26
NC
24
OUTAP
25
OUTBP
NC：Non Connection
REV. A
Pin name
4/4
○Operation Notes
(1)
Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating
conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a
short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings,
consider adding circuit protection devices, such as fuses.
(2) Power supply lines
As return of current regenerated by back EMF of motor happens, take steps such as putting capacitor
between power supply and GND as an electric pathway for the regenerated current. Be sure that there is no
problem with each property such as emptied capacity at lower temperature regarding electrolytic capacitor
to decide capacity value. If the connected power supply does not have sufficient current absorption capacity,
regenerative current will cause the voltage on the power supply line to rise, which combined with the
product and its peripheral circuitry may exceed the absolute maximum ratings. It is recommended to
implement a physical safety measure such as the insertion of a voltage clamp diode between the power
supply and GND pins.
(3) GND potential
The potential of GND pin must be minimum potential in all operating conditions.
(4) Metal on the backside (Define the side where product markings are printed as front)
The metal on the backside is shorted with the backside of IC chip therefore it should be connected to GND.
Be aware that there is a possibility of malfunction or destruction if it is shorted with any potential other than
GND.
(5) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual
operating conditions. This IC exposes its frame of the backside of package. Note that this part is assumed
to use after providing heat dissipation treatment to improve heat dissipation efficiency . Try to occupy as
wide as possible with heat dissipation pattern not only on the board surface but also the backside.
(6) Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the
IC to malfunction.
(7) ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
(8) Thermal shutdown circuit
The IC has a built-in thermal shutdown circuit (TSD circuit). If the chip temperature becomes Tjmax=150℃,
and higher, coil output to the motor and regulator output will be OFF, and reset output will be L. The TSD
circuit is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect
or indemnify peripheral equipment. Do not use the TSD function to protect peripheral equipment.
(9) Ground Wiring Pattern
When using both large current and small signal GND patterns, it is recommended to isolate the two ground
patterns, placing a single ground point at the ground potential of application so that the pattern wiring
resistance and voltage variations caused by large currents do not cause variations in the small signal
ground voltage. Be careful not to change the GND wiring pattern of any external components, either.
(10) TEST pin
Be sure to leave TEST1 pin open and connect TEST2 pin to GND.
REV. A
Appendix
Notes
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upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account
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Appendix-Rev4.0