FAIRCHILD FSD1000

www.fairchildsemi.com
FSD1000
Combo Fairchild Power Switch (FPSTM)
Features
Description
FSD1000 is a Fairchild Power Switch (FPS) that is specially
designed for SMPS of personal computer. This device is a
high voltage power SenseFET combined with two PWM
controllers in a single monolithic device; One is for main power
and the other is for auxiliary power. The PWM controllers
feature integrated oscillator, under voltage lockout,
optimized gate driver and temperature compensated precise
current sources for the loop compensation. This device also
includes various fault protection circuits such as line under/
over voltage lock out, over voltage protection, over load
protection and over temperature protection. Compared with
discrete MOSFET and PWM controller solution, FSD1000
can reduce total cost, component count, size and weight
simultaneously increasing efficiency, productivity and
system reliability
• Current Mode Control for Main Power
• Voltage Mode Control for Auxiliary Power
• Synchronized switching of Main and Auxiliary Power
(70kHz)
• Internal Start-up Circuit
• Internal Soft Start for Auxiliary Power
• User Defined Soft Start for Main Power
• Pulse by Pulse Current Limiting
• Over Load Protection (Main : Latch Mode, Aux : Auto
Restart Mode)
• Internal Over Temperature Protection
• Vcc Under Voltage Lockout
• Line Under voltage/ Over Voltage Lockout
• Burst Mode Operation for auxiliary power to reduce the
Power Consumption in the Standby Mode
• Internal High Voltage SenseFET for auxiliary power
Application
Typical Circuit
• SMPS for PC power
• LCD TV Power Supply
Main Output
V STR
AC
IN
Output
LS2
Main
PWM
Isense
Main Off
LS1
Aux Output
S/S
Drain
Aux
PWM
GND
V FB.aux
ILIM
V FB.main
Vcc
Figure 1. Typical Application circuit
Rev.1.0.2
©2004 Fairchild Semiconductor Corporation
FSD1000
Internal Block Diagram
Drain
11
LS2
8
Vcc
5
Vstr
12
Ich
Vcc OVP
Line OVP
4.4 V
H : Dmain < 0.67
L : Dmain < 0.50
2.4 V
2.0 V
Vref
Vcc good
21V
9.5/13.5V
Gate
drive
Q
S
Q
R
Internal
Bias
OSC
S
Q
R
Q
Gate drive
GND
ILIM 9
Vref
Idelay
Q
R
Q
S
OTP
IFB
Auto
restart
OSC
PWM
Comparator
Latch
Vcc OVP
0.3V
1:110
Vref
S
Line OVP
Main OLP
R
6
Q
Q
3R
Power off Reset
(Vcc <6V)
Vcc
Vcc
IFB
Idelay
Isense
2 VFB.MAIN
R
VFB,AUX 1
R
Soft Start
(10ms)
Aux OFF
Counter
/4
Vcc good
Main
OLP
Vcc good
7V
Aux OLP
Main OFF
Burst
0.5 V
0.7 V
4.5V
Vth
Vcc
ISS
3 S/S
0.8 V
1.0 V
1.4 V
1.68 V
Vcc
good
time delay
(30ms)
7
LS1
Figure 2. Functional Block Diagram of FSD1000
2
4 Output
Burst
FSD1000
Pin Definitions
Pin Number
Pin Name
Pin Function Description
VFB,AUX
This pin is for the feedback control of the auxiliary power. This pin is internally
connected to the inverting input of the PWM comparator. The collector of an
opto-coupler is typically tied to this pin. For stable operation, a capacitor should
be placed between this pin and GND. Voltage mode control is employed for the
auxiliary power and the duty cycle ratio of Internal MOSFET for the auxiliary
power is proportional to the voltage of this pin. If the voltage of this pin exceeds
4.5V, the over load protection is triggered terminating the switching operation of
the main and auxiliary power (Auto-restart mode protection).
2
VFB,MAIN
This pin is for the feedback control of the main power. This pin is internally
connected to the inverting input of the PWM comparator. The collector of an
opto-coupler is typically tied to this pin. For stable operation, a capacitor should
be placed between this pin and GND. Current mode control is employed for the
main power and the peak drain current of the external MOSFET for the main
power is proportional to the voltage of this pin. If the voltage of this pin exceeds
7V, the over load protection is triggered disabling the gating output for the main
power (Latch mode protection).
3
S/S
This pin is for the soft start of the main power. Soft start time is programmed by
a capacitor on this pin.
4
Output
1
This pin is for the gate drive of the external MOSFET of the main power.
5
Vcc
This pin is the positive supply voltage input. During startup, the power is supplied
by an internal high voltage current source that is connected to the Vstr pin. When
Vcc reaches 13.5V, the internal high voltage current source is disabled and the
power is supplied from auxiliary transformer winding.
6
ISENSE
This pin is for the current sense of the external MOSFET for the main power. It is
internally connected to the PWM comparator for the main.
7
LS1
This pin is for line under voltage detection. When the voltage of this in drops
below 1.4V the main power is shutdown. When the voltage drops below 0.8V,
the auxiliary power is shutdown.
8
LS2
This pin is for line over voltage detection and maximum duty cycle ratio change.
The maximum duty cycle ratio is set to be 50% when the voltage of LS2 pin is
higher than 2.4V. The maximum duty cycle ratio is increased to 67% when LS2
voltage goes below 2.0V. When the voltage of LS2 goes above 4.4V, the
switching operations for the main and auxiliary powers are disabled to protect
the switching devices.
9
ILIM
This pin is for the current limit of the auxiliary power. The pulse-by-pulse current
limit level of the internal SenseFET is programmed by a resistor on this pin.
10
NC
11
Drain
This pin is the high voltage power SenseFET drain. It is designed to drive the
auxiliary transformer directly.
VSTR
This pin is connected directly to the high voltage DC link. At startup, the internal
high voltage current source supplies internal bias and charges the external
capacitor that is connected to the Vcc pin. Once Vcc reaches 13V, the internal
current source is disabled.
12
3
FSD1000
Pin Configuration
12DIPH
VFB,AUX
1
12
Vstr
VFB,MAIN
2
11
Drain
S/S
3
10
NC
GND
GND
FSD1000
Output
4
9
ILIM
Vcc
5
8
LS2
Isense
6
7
LS1
Figure 3. Pin Configuration (Top View)
4
FSD1000
Absolute Maximum Ratings
(Ta=25°C, unless otherwise specified)
Parameter
Maximum Vstr Pin Voltage
Continuous SenseFET Drain Current (TC=25°C)
Maximum Supply Voltage
Input Voltage Range
Operating Ambient Temperature
Storage Temperature Range
Symbol
Value
Unit
VSTR,MAX
700
V
ID
2
ADC
VCC,MAX
20
V
VFB,MAIN / VFB,AUX
-0.3 to VSD
V
TA
-25 to +85
°C
TSTG
-55 to +150
°C
5
FSD1000
Electrical Characteristics
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
700
-
-
V
-
-
100
µA
SENSEFET SECTION
Drain-Source Breakdown Voltage
Off-State Current
On-State Resistance
BVdss
Idss
RDS(ON)
VCC = 0V, ID = 100µA
VDS = 560V
Tj = 25°C ID = 100mA
-
7.8
9.0
Ω
Tj = 100°C ID = 100mA
-
12.9
15.0
Ω
Rising Time 2
(1)
TR2
VDS = 350V, ID = 500mA
-
100
-
ns
Falling Time 2
(1)
TF2
VDS = 350V, lD = 500mA
-
50
-
ns
Leading Edge
Blanking(1)
-
250
-
ns
Pulse-by-pulse current limit
TLEB
-
ILIM
With 33Ω resistor between
ILIM pin and ground pin
0.8
1.0
1.2
A
Fosc
Tj = 25°C
61
67
73
kHz
CONTROL SECTION
Switching Frequency
Main Feedback Source Current
IFB,MAIN
Ta = 25°C, VFB,MAIN = 0V
0.6
0.7
0.8
mA
Shutdown Main Delay Current
IDELAY,MAIN
Ta = 25°C
5V < VFB,MAIN < VSD,MAIN
3.5
5.0
6.5
uA
Aux. Feedback Source Current
IFB,MAIN
Ta = 25°C, VFB,AUX = 0V
0.3
0.4
0.5
mA
Shutdown Aux. Delay Current
IDELAY,MAIN
Ta = 25°C
3V < VFB,AUX < VSD,AUX
3.5
5.0
6.5
uA
Maximum Duty Cycle
Dmax
VFB,AUX = 3.5V
1.4V < LS2 < 2V
62
67
72
%
Maximum Duty Cycle
Dmax
VFB,AUX = 3.5V
2V < LS2 < 4.4V
45
50
55
%
Minimum Duty Cycle
Dmin
VFB,AUX = 0V
-
0
0
%
12.5
13.5
14.5
V
8.5
9.5
10.5
V
UVLO Threshold Voltage
Vstart
Vstop
After turn on
SOFT START SECTION
Soft Start Current
Internal Soft Start Time
Internal Time Delay
ISOFT
-
35
45
55
uA
TSS
-
-
10
-
ms
Td
-
-
30
-
ms
140
160
-
°C
6.0
7.0
8.0
V
4.0
4.5
5.0
V
PROTECTION SECTION
Thermal Shutdown Temperature (Tj) (1)
TSD
Shutdown Main Feedback Voltage
VSD,MAIN
Shutdown Aux. Feedback Voltage
VSD,AUX
(Note 1)
Vfb = 4V
OUTPUT SECTION
Rising Time 1 (1)
TR1
Ta = 25°C, CL = 100pF
-
45
150
ns
Falling Time 1 (1)
TF1
Ta = 25°C, CL = 100pF
-
35
150
ns
Note:
1. These parameters, although guaranteed, are not 100% tested in production
6
FSD1000
Electrical Characteristics (Continued)
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Line Over Voltage
BUS OVP
-
4.0
4.4
5.0
V
PWM Max Duty Control Voltage
Max Duty
-
2.0
2.4
2.8
V
-
-
400
-
mV
-
1.17
1.4
1.63
V
-
-
280
-
mV
-
0.67
0.8
0.93
V
-
-
200
-
mV
-
-
0.7
-
V
-
-
200
-
mV
LINE SENSE SECTION
Hysteresis
Main Off Voltage
Main OFF
Hysteresis
Aux. Off Voltage
Aux OFF
Hysteresis
BURST MODE SECTION
Burst Mode Voltage
BURST
Hysteresis
TOTAL DEVICE SECTION
Start up Chragng Current
Ich
VCC = 0V, VSTR = min. 30V
-
1.5
2.3
mA
Operating Supply Current
Iop
Ta = 25°C, VCC = 18V
-
4
5
mA
7
FSD1000
Typical Performance Characteristics
(Some characteristic Graphs are Normalized at Ta= 25°C)
1.3
1.3
1.2
1.2
1.1
1.1
1.0
1.0
0.9
0.9
0.8
0.8
0.7
-40
-20
0
20
40
60
80
100
120
140
0.7
-40
-20
0
20
Iop
1.3
1.2
1.2
1.1
1.1
1.0
1.0
0.9
0.9
0.8
0.8
0
20
40
80
100
120
140
Figure 2. Normalized Aux feedback current vs. Temp
1.3
-20
60
Ifb_aux
Figure 1. Normalized Operating Current vs. Temp
0.7
-40
40
60
80
100
120
140
0.7
-40
-20
0
20
Ifb
40
60
80
100
120
140
Fosc
Figure 3. Normalized Main feedback current vs. Temp
Figure 4. Normalized Operating Freqency vs. Temp
700
550
650
500
600
450
550
400
500
350
450
300
400
250
200
-40
350
-20
0
20
40
60
80
100
120
Isouce
Figure 5. Output source current (mA) vs. Temp
8
140
300
-40
-20
0
20
40
60
80
100
120
140
Isink
Figure 6. Output sink Current (mA) vs. Temp
FSD1000
Functional Description
1. Startup : At startup, an internal high voltage current
source supplies the internal bias and charges the external
capacitor that is connected to the Vcc pin as illustrated in
figure 4. When Vcc reaches 13.5 V, the FPS begins switching
operation and the internal high voltage current source is
disabled. Then, the FPS continues its normal switching
operation unless Vcc goes below the stop voltage of 9.5 V
and the power is supplied from the auxiliary transformer
winding. Once the auxiliary power starts up, the main power
starts up with a time delay of 30ms.
ILIM pin. Since the sense ratio is 1/110 and the reference
voltage of the comparator is 0.3V, the pulse-by-pulse current
limit level (ICL) is given by
× 0.3I CL = 110
----------------------R LIM
(A)
LS2
5
Max duty
control
DC link
voltage
2.0 V
2.4 V
Vcc
3
6
OSC
S
Q
R
Q
Gate
drive
4 Output
Vstr
6 Isense
PWM
Comparator
Istart
3R
Vcc
Vcc
IFB
Idelay
VFB.MAIN
2
Vref
D2
R
Vcc good
D1
CFB
9.5V/13.5V
Internal
Bias
Figure 5. PWM control block for the main power
Figure 4. Internal startup circuit
Drain
11
2. Feedback Control : FSD1000 has two PWM controllers
in a single package; one is for the main power and the other
is for the auxiliary power. The PWM block for the main
controls the external MOSFET, while the PWM block for the
auxiliary power controls the internal SenseFET.
2.1 Feedback Control for the main power : Figure 5
illustrates the simplified PWM block for the main power.
The current mode control is employed for the main power.
The voltage of the feedback pin is compared with the current
sense voltage for pulse width modulation (PWM). As shown
in figure 5, the feedback voltage determines the peak value
of the drain current of the external power MOSFET for main
power. Usually opto-coupler is used to implement feedback
network. The collector of the opto-coupler transistor is
connected to feedback pin and the emitter is connected to the
ground pin. For stable operation, a capacitor should be
placed between this pin and GND.
2.2 Feedback Control for the auxiliary power : Figure 6
shows the internal high voltage SenseFET together with
PWM block for auxiliary power. Auxiliary power employs
voltage mode control and the feedback pin voltage is
compared with internal ramp signal for pulse width
modulation (PWM). The pulse-by-pulse current limit level of
the SenseFET is programmed by an external resistor on the
9
Gate
drive
GND
Q
S
Q
R
OSC
Burst
1/110
ILIM
9
0.3V
R LIM
Vref
Vref
OSC
I delay
V FB,AUX
I FB
4
D1
C FB
D2
R
Soft start
Figure 6. PWM control block for the auxiliary power
3. Protection Circuit : Besides pulse-by-pulse current limit,
FSD1000 has various self protection functions; over load
protections (OLP) for main and auxiliary powers, over
voltage protection (OVP), line over/under voltage lockout
and over temperature protection (OTP). Because these
protection circuits are fully integrated into the IC without
external components, the reliability can be improved. In the
event of fault conditions such as OLP of auxiliary power and
FSD1000
line under voltage lockout, FSD1000 enters into auto restart
operation. Once the fault condition occurs, switching is
terminated and the SenseFET remains off. This causes Vcc
to fall. When Vcc reaches the stop voltage (9.5V), the
internal startup circuit charges Vcc capacitor up to start
voltage (13.5V). When Vcc reaches 13.5V, the internal
startup circuit is disabled and Vcc is discharged down to
9.5V. In this manner, FSD1000 repeats charging and
discharging Vcc capacitor 4 times. After then, the protection
is reset and the FSD1000 resumes its normal operation. In
this manner, the auto-restart can alternately enable and
disable the switching of the power SenseFET until the fault
condition is eliminated as shown Figure 7. Meanwhile,
FSD1000 enters into latch mode in the case of Vcc OVP,
Line OVP and Main OLP and OTP. The fault latch is reset
only when Vcc is fully discharged below 6V by un-plugging
the AC line as shown in Figure 8.
Over Load of Aux
Over Load removed
13.5V
9.5V
Vcc
Aux Vds
Restart
3.1 Over Load Protection : Over load means that the load
current exceeds a pre-set level due to an abnormal situation.
In this situation, protection circuit should be triggered in
order to protect the SMPS. Because of the pulse-by-pulse
current limit capability, the maximum peak current through
the SMPS is limited, and therefore the maximum input
power is restricted with a given input voltage. If the output
consumes beyond this maximum power, the output voltage
(Vo) decreases below the set voltage. This reduces optocoupler transistor current increasing feedback voltage (Vfb).
If the inverting input of PWM comparator reaches its
maximum value, D1 is blocked and the current source Idelay
starts to charge CFB slowly compared to when the current
source IFB charges CFB. In this condition, the feedback
voltage continues increasing until it reaches OLP threshold,
and the switching operation is terminated at that time. The
OLP for the auxiliary power is auto restart mode while OLP
for the main is latch mode.
3.2 Line Under voltage lockout : The switching operation
for the main power is terminated when the voltage of LS1
drops below 1.4V and the switching operation for auxiliary
power is terminated when this voltage goes below 0.8V.
3.3 Over voltage protection : In an abnormal situation such
as feedback loop open, the supply voltage for FSD1000
(Vcc) may rise above the breakdown voltage of the FPS. In
order to protects the FPS from the over voltage damage,
FSD1000 employs over voltage protection for Vcc. If Vcc
exceeds 21V, OVP circuit is triggered resulting in a
termination of switching operation of both main and
auxiliary powers. In order to avoid undesired triggering of
OVP during normal operation, Vcc should be properly
designed to be below 21V.
Figure 7. Auto restart mode protection
3.4 Line Over voltage protection : When the voltage of
LS2 rises above below 4.4V, the switching operations for the
main and auxiliary powers are disabled to protect the
switching devices.
Latch Reset
OTP, Vcc OVP, Line
OVP, Main OLP
AC power Off
AC power On
13.5V
3.5 Over Temperature Protection : The thermal shutdown
circuitry senses the junction temperature. The threshold is set
at 160°C. When the junction temperature rises above this
threshold, the switching operations of main and auxiliary
powers are disabled.
9.5V
6V
Vcc
Aux Vds
Figure 8. Latch mode protection
4. Burst Mode Operation : In order to minimize the power
dissipation in the standby mode, FDS1000 has burst
operation for the auxiliary power. The FPS enters into the
burst mode when the feedback voltage decreases as the load
decreases. The operation principle of the burst mode is
illustrated in Figure 9. When the feedback voltage drops
below 0.5V, the FPS stops the switching operation. Then, the
output voltage decreases below the set voltage, which
increases the feedback voltage. When the feedback voltage
rises above 0.7V, the FPS resumes the switching operation
and the feedback voltage decreases. When the feedback
voltage drops below 0.5V again, the FPS ceases the
10
FSD1000
switching operation. In this manner, the burst operation
alternately enables and disables the switching of the power
MOSFET to reduce the switching loss in the standby mode.
M ain O utput
Vo
Vo set
VFB
0.70V
0.50V
M ain O ff
Ids
A ux O u tp ut
Vds
time
Figure 9. Waveforms of burst operation
5. Sequence of start-up and shutdown : FSD1000 has a
sequence of the startup and shutdown operation between
main and auxiliary powers. As can be seen in Figure 11,
main power starts up with 30 ms time delay after auxiliary
power starts up. When the AC line is powered off, the main
power shuts down first as the voltage of LS1 pin drops below
1.4V. The auxiliary power shuts down when the voltage of
LS1 drops below 0.8V. Figure 12 shows the shutdown and
restart sequence in the case of auto restart mode protection.
When the protection is triggered, main and auxiliary powers
shut down together. When FSD1000 restarts, the auxiliary
power starts up first and the main power starts up after 30ms.
Figure 13 shows the shutdown and restart sequence in the
case of latch mode protection. When the protection is
triggered, main and auxiliary powers shut down together and
Vcc continues being charged and discharged until Vcc is
fully discharged. The protection is reset when Vcc is
discharged below 6V by unplugging the AC line. Figure 14
shows the remote ON/OFF of the main power. The remote
ON/OFF of the main power is easily implemented using a
transistor connected to the cathode of KA431 in the main
power feedback network as shown in Figure 10. When the
transistor is turned on, the current through the opto-coupler
increases pulling down the feedback voltage to almost zero.
The main starts up with soft-start when the transistor is
turned off.
Figure 10. Remote ON/OFF of Main power
11
FSD1000
AC power on
AC power on
AC power off
AC Line
voltage
LS1<1.4V
LS1<0.8V
DC link
voltage
13.5V
9.5V
Vcc
Aux drain
current
Tss=10ms
Tss=10ms
Main drain
current
Td=30ms
Td=30ms
Figure 11. Typical Waveforms (1)
OLP of Aux
Auto Restart
13.5V
9.5V
Vcc
Aux drain
current
Tss=10ms
Tss=10ms
Main drain
current
Td=30ms
Td=30ms
Figure 12. Typical Waveforms (2)
12
FSD1000
Vcc OVP, Line OVP,
Main OLP or OTP
AC Power off
Latch
reset
AC Power ON
13.5V
9.5V
6V
Vcc
Aux drain
current
Tss=10ms
Tss=10ms
Main drain
current
Td=30ms
Td=30ms
Figure 13. Typical Waveforms (3)
Main Off by
pulling down VFB
Main ON
Main VFB
13.5V
Vcc
Aux drain
current
Tss=10ms
Main drain
current
Td=30ms
Figure 14. Typical Waveforms (4)
13
FSD1000
Typical application circuit
Low standby mode power consumption (<1W at 240Vac input and 0.5W load)
Low component count
Enhanced system reliability through various protection functions
Internal soft-start (10ms)
•
•
•
•
JP2
LS
R112
33
2
F1
FUSE
0
7
8
9
U1
1
LS1
LS2
RT1
10D9
2 1
1
GND
Output
Vcc
Isense
C101
473/275VAC
I_LIM
GND
VFB.aux
VFB.main
S/S
Drain
NC
t
Vstart
Line f ilter
LF1
1
2
2
VFB1
GND_P
R109
30k
GND_P
Is
1N4745
D103
2
C102
473/275VAC
6
5
4
3
13
2
1 VFB2
C103
222/3kV
4 -
0
C105
222/3kV
1
2
UF4003
2
1
D104
GND_P
47uF,50V
C110
C104
222/3kV
2
1
R110
30
C113
1uF
R111
10k
VDC
BD1
GSIB660
C107
470uF,200V
+ 2
GND_P
2
C106
470uF,200V
1
D102
GND_P
1
1
2
2
R101
500K
R102
500K
LS
R103
10K
1
R104
33K/3W
Gate
Is
D101
UF4007
2
Q1
FQA10N80
1 G
R105
1K
T2
EE1625
C109
102
1
2
3
4
5
6
C114
222,1kV
UF4007
D106
R107
10/0.5W
Drain
VDC
R108
50K/3W
UF4004
Gate
1N4745
D105
1
VFB2
D
S
1
T1
EI3329
14
4
3
9
10
11
12
13
5
8
2
R212
1k
C207
470uF,16V
L202
2uH
6
1
7
C108
2
222,1kV
R106
0.1/2W
10
9
GP30G
D203
18
7
R213
1k
1
C209
47nF
2
2
1
1
10
R201
1
472
C201
2
472
C203
2
2
2
1
21
2 1
D201
1
2 1
MBRF3060PT
10
R203
D202
MBRF3060PT
R214
10k
C208
470uF,16V
1
GND_S
R211
33k
C202
472
R202
10
GND_S
R204
10
C204
472
GND_S
5V_aux
VFB1
P1
817A
GND_P
SW SPDT
S1
4.7k
R210
1
L201
EER2834
12
9
11
8
10
4
2
5
1
C210
100nF
7
R205
1k
2
6
2
R206
1k
3
1
IC1
TL431
R207
33k
GND_S
C205
2200uF,10V
GND_S
C206
2200uF,10V
GND_S
1
R209
5k
5V
3.3V
2
R208
3.2k
1
1
3
1
2
1
2
3
3
2
1
21
2
2
C112
473
2
Q2
2N2222
2
1
1
2
3
1
14
11
GND_P 10
12
C111
103
P2
817A
2
2
1
HEADER 3
C115
473
Drain
VDC
FSD1000
GND_P
3
2
1
2
1
2
3
1
2
1
2
1
2
1
2
1
2
1
2
2
GND_P
1
IC2
TL431
GND_S
2
1
2
1
1
2
3
1
2
1
2
1
2
1
2
1
2
1
2
GND_P
1
R215
10k
1
4
2
2
1
1
2
GND_S
R216
10k
14
11
1
2
3
3
2
1
2
1
2
2
1
2
1
2
2
1
2
1
1
2
1
2
4
3
3
2
2
1
2
1
Main power : 5V (12A), 3.3V (12A)
with voltage doubler
Aux. power : 5V (2A)
110W
Universal input
PC power supply
Output voltage (Max current)
Output power
Input voltage
Application
Features
1. Schematic
FSD1000
2.1 Main Transformer Schematic Diagram
1
14
3㎜
NP/2 2
3㎜
13 +5V
3
12
NP/2 4
5
BOTTOM
11
6
10
7
9
TOP
NP/2
N5V
N3.3V
NP/2
+3.3V
8
Bobbin
* THE '
' MARKS ARE START POINT.
CORE : EI3329
BOBBIN : EI3329
2.2 Main Transformer Winding Specification
No
NP/2
Pin (s→f)
Wire
Turns
Winding Method
1→3
φ
24
Solenoid Winding
2
Center Winding
3
Center Winding
24
Solenoid Winding
0.5 × 1
Insulation: Polyester Tape t = 0.050mm, 2Layers
N3.3V
10 → 8
0.4φ × 6
Insulation: Polyester Tape t = 0.050mm, 2Layers
N5V
14→ 12
0.4φ × 6
Insulation: Polyester Tape t = 0.050mm, 2Layers
NP/2
3→5
0.5φ × 1
Outer Insulation: Polyester Tape t = 0.050mm, 2Layers
2.3 Main Transformer Electrical Characteristics
Pin
Specification
Remarks
Inductance
1-5
9mH ± 10%
100kHz, 1V
Leakage Inductance
1-5
10uH Max
2nd all short
15
FSD1000
3.1 Main inductor Schematic Diagram
3㎜
6
5
4
3
N3.3V
2
3㎜
1
N5V
N5V
TOP
N3.3V
7
8
9
10 11 12
Bobbin
* THE '
' MARKS ARE START POINT.
CORE : EER2834
BOBBIN : EER2834
3.2 Main inductor Winding Specification
No
N5V
Pin (s→f)
Wire
Turns
Winding Method
1 → 12
φ
9
Center Winding
6
Solenoid Winding
0.4 × 8
Insulation: Polyester Tape t = 0.050mm, 2Layers
N3.3V
6→7
0.4φ × 8
Insulation: Polyester Tape t = 0.050mm, 2Layers
3.3 Main inductor Electrical Characteristics
Inductance
16
Pin
Specification
Remarks
1 - 12
15 uH ± 10%
100kHz, 1V
FSD1000
4.1 Auxiliary Transformer Schematic Diagram
10
1
3㎜
NVcc
3㎜
2
3
9
BOTTOM
4
5
NVcc
N5V
NP/2
8
NP/2
6
TOP
NP/2
NP/2
+5V
7
Bobbin
* THE '
' MARKS ARE START POINT.
CORE : EE1625
BOBBIN : EE1625
4.2 Auxiliary Transformer Winding Specification
No
NP/2
N5V
NVcc
NP/2
Pin (s→f)
Wire
φ
4→5
0.15
8→7
0.5φ
2→1
φ
0.2
5→6
0.15
φ
Turns
Winding Method
75
Solenoid Winding
9
Solenoid Winding
25
Solenoid Winding
75
Solenoid Winding
4.3 Auxiliary Transformer Electrical Characteristics
Pin
Specification
Remarks
Inductance
4-6
1.35mH ± 10%
100kHz, 1V
Leakage Inductance
4-6
60uH Max
2nd all short
17
FSD1000
5. Layout Auxiliary Transformer Electrical Characteristics
18
FSD1000
Package Dimensions
12DIPH-300
19
FSD1000
Ordering Information
Product Number
Package
Package Marking
Rdson max
FSD1000
12-DIPH
FSD1000
9Ω
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
7/9/04 0.0m 001
 2004 Fairchild Semiconductor Corporation