TI TMS44409P

TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
D
D
D
D
D
D
D
Organization . . . 1 048 576 × 4
Single 5-V Power Supply (±10% Tolerance)
Performance Ranges:
ACCESS
TIME
(tRAC)
(MAX)
’44409 / P-60 60 ns
’44409 / P-70 70 ns
’44409 / P-80 80 ns
ACCESS
TIME
(tCAC)
(MAX)
15 ns
18 ns
20 ns
ACCESS
TIME
(tAA)
(MAX)
30 ns
35 ns
40 ns
EDO
CYCLE
(tHPC)
(MIN)
25 ns
30 ns
35 ns
Extended Data Out ( EDO) Operation
CAS-Before-RAS ( CBR) Refresh
3-State Unlatched Output
Low Power Dissipation
All Inputs / Outputs and Clocks are
TTL-Compatible
Long Refresh Period
– 1 024 Cycle Refresh in 16 ns (max)
– 128 ms on Low Power, Self-Refresh
Version (TMS44409P Only)
Operating Free-Air Temperature Range
0°C to 70°C
description
DJ PACKAGE
( TOP VIEW )
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
VCC
DGA PACKAGE
( TOP VIEW )
1
2
3
4
5
26
25
24
23
22
VSS
DQ4
DQ3
CAS
OE
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
VCC
1
2
3
4
5
26
25
24
23
22
VSS
DQ4
DQ3
CAS
OE
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
PIN NOMENCLATURE
A0 – A9
CAS
DQ1 – DQ4
OE
RAS
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data In / Data Out
Output Enable
Row-Address Strobe
5-V Supply
Ground
Write Enable
The TMS44409 is a high-speed 4 194 304-bit
dynamic random-access memory (DRAM) organized as 1 048 576 words of four bits each. This
device features maximum RAS access times of
60 ns, 70 ns and 80 ns. Maximum power
consumption is as low as 385 mW operating and
6 mW standby. All inputs and outputs, including
clocks, are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system
design. Data out is unlatched to allow greater system flexibility.
The TMS44409P is a high-speed, low-power, self-refresh version of the TMS44409 DRAM.
All versions of the TMS44409 / P are offered in a 300-mil 20 / 26 J-lead plastic surface-mount SOJ package ( DJ
suffix) and a 20 / 26-lead plastic small outline package ( DGA suffix). These devices are characterized for
operation from 0°C to 70°C.
Copyright  1995, Texas Instruments Incorporated
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
ADVANCE INFORMATION
D
D
D
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
logic symbol†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
ADVANCE INFORMATION
CAS
W
OE
DQ1
DQ2
DQ3
DQ4
9
10
11
12
14
15
16
17
18
5
4
23
3
22
1
2
24
25
RAM 1024K × 4
20D10/21D0
A
0
1 048 575
20D19/21D9
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21[COLUMN]
G24
&
23,21D
G25
23C22
24,25EN
A,22D
26
A,Z26
† This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
functional block diagram
RAS
CAS
W
OE
Timing and Control
8
ColumnAddress
Buffers
Column Decode
Sense Amplifiers
2
128K Array
128K Array
A9
16
RowAddress
Buffers
16
128K Array
R
o
w
128K Array
16
16
D
e
c
o
d
e
10
128K Array
I/O
Buffers
4 of 16
Selection
2
DataIn
Reg.
DataOut
Reg.
4
4
DQ1 – DQ4
128K Array
10
operation
extended data out
Extended data out allows for data output rates of up to 40 MHz for 60-ns devices. When keeping the same row
address while selecting random column addresses, the time for row-address setup and hold and address
multiplex is eliminated. The maximum number of columns that can be accessed is determined by tRASP , the
maximum RAS low time.
Extended data out does not place the DQs into the high-impedance state with the rising edge of CAS. The output
remains valid for the system to latch the data. After CAS goes high, the DRAM decodes the next address. OE
and W can be used to control the output impedance. Descriptions of OE and W further explain EDO operation
benefit.
address ( A0– A9)
Twenty address bits are required to decode one of 1 048 576 storage cell locations. Ten row-address bits are
set up on A0 through A9 and latched onto the chip by the row-address strobe ( RAS). The ten column-address
bits are set up on pins A0 through A9 and latched onto the chip by the column-address strobe (CAS). All
addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip-enable in
that it activates the sense amplifiers as well as the row decoder.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 7). There are two
methods for placing the DQs into the high-impedance state and keeping them that way during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for tCHO past the CAS
transition. This disables the DQs and they remain disabled, regardless of OE, until CAS falls again. The second
method is to have OE low as CAS transitions high. Then OE can pulse high for a minimum of tOEP anytime during
CAS high time, thus, disabling the DQs regardless of further transitions on OE until CAS falls again (see
Figure 7).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3
ADVANCE INFORMATION
A0
A1
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
write enable ( W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The data input is disabled when the read mode is selected.
When W goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle,
permitting a write operation independent of the state of OE. This permits early-write operation to be completed
with OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is
high (see Figure 8).
data in / data out ( DQ1– DQ4)
Data is written during a write or a read-modify-write cycle. Depending on the mode of operation, data is strobed
in by the later falling edge of CAS or W with setup and hold times referenced to the latter edge. The DQs drive
valid data after all access times are met and remain valid except in the cases described in the W and OE
descriptions (above).
refresh
ADVANCE INFORMATION
A refresh operation must be performed at least once every 16 ms to retain data. This is achieved by strobing
each of the 1 024 rows (A0 – A9). A normal read or write cycle refreshes all bits in each row that is selected. A
RAS-only operation can be used by holding CAS at the high ( inactive) level, thus conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished
by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle. The external address is ignored during the hidden-refresh cycle.
CAS-before-RAS ( CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS
falls (see parameter tCHR). For successive CBR-refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
self-refresh (TMS44409P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100 µs. The chip is then refreshed by an on-board oscillator. No external address is required
because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS
are brought high to satisfy tCHS. Upon exiting the self-refresh mode, a burst refresh (refresh of a full set of row
addresses) must be executed before continuing with normal operation. This ensures the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full VCC level is achieved. These eight initialization cycles need to include at
least one refresh (RAS only or CBR) cycle.
test mode
A design for test (DFT) mode is incorporated in the TMS44409. A CBR with W low (WCBR) cycle is used to enter
the test mode. In the test mode, data is written into and read from eight sections of the array in parallel. All data
is written into the array through DQ1. Data is compared upon reading and if all bits are equal, all DQ pins go
high. If any one bit is different, a DQ pin goes low. Any combination of read, write, read-write, or page-mode
can be used in the test mode. The test-mode function reduces test times by enabling the 1-megabit × 4 DRAM
to be tested as if it were a 512K DRAM where column address 0 is not used. A RAS-only or CBR-refresh cycle
is used to exit the DFT mode.
4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
NOM
MAX
Supply voltage
4.5
5
5.5
UNIT
V
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
–1
0.8
V
TA
Operating free-air temperature
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
ADVANCE INFORMATION
MIN
VCC
VIH
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output
voltage
IOH = – 5 mA
VOL
Low-level output
voltage
IOL = 4.2 mA
II
Input current
(leakage)
IO
’44409-60
’44409P-60
’44409-70
’44409P-70
’44409-80
’44409P-80
MIN
MIN
MIN
MAX
2.4
MAX
2.4
UNIT
MAX
2.4
V
ADVANCE INFORMATION
0.4
0.4
0.4
V
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All other pins = 0 V to VCC
± 10
± 10
± 10
mA
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to 6.5 V,
± 10
± 10
± 10
µA
ICC1 †
Read- or write-cycle
current (see Note 3)
VCC = 5.5 V,
tRWC = MIN
105
90
80
mA
2
2
mA
Standby current
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V
2
ICC2
1
1
1
mA
500
500
500
µA
105
90
80
mA
90
80
70
mA
500
500
500
µA
5
5
5
mA
500
500
500
µA
TTL
CMOS
’44409
’44409P
ICC3
Average refresh
current
(RAS only or CBR)
(see Note 3)
VCC = 5.5 V,
tRWC = MIN,
CAS high (RAS only);
RAS cycling,
RAS low after CAS low (CBR)
ICC4 †
Average EDO page
current (see Note 4)
VCC = 5.5 V,
RAS low,
ICC6‡
Self-refresh current
CAS, RAS < 0.2 V,
Measured after tRASS min
ICC7 †
Standby current
RAS = VIH,
CAS = VIL ,
Data out = enabled
ICC10‡
Battery-backup
current
tRC = 125 µs, tRAS ≤ 1 µs,
VCC – 0.2 V ≤ VIH ≤ 6.5 V,
0 V ≤ VIL ≤ 0.2 V, W and OE = VIH ,
Addresses and data stable
tHPC = MIN,
CAS cycling
† Measured with outputs open
‡ TMS44409P only
NOTES: 3. Measured with a maximum of one address change while RAS = VIL
4. Measured with a maximum of one address change while CAS = VIH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5) §
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A9
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, CAS and RAS
7
pF
Ci(W)
Input capacitance, W
7
pF
7
pF
Co
Output capacitance
§ Capacitance measurements are made on a sample basis only.
NOTE 5: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
’44409-60
’44409P-60
’44409-70
’44409P-70
’44409-80
’44409P-80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tAA
tCAC
Access time from column address
30
35
40
ns
Access time from CAS low
15
18
20
ns
tCPA
tRAC
Access time from column precharge
35
40
45
ns
Access time from RAS low
60
70
80
ns
tOEA
tCLZ
Access time from OE low
20
ns
CAS to output in low-impedance state
0
tREZ
tCEZ
Output disable time, start of RAS high (see Note 6)
3
15
3
18
3
20
ns
Output disable time, start of CAS high (see Note 6)
3
15
3
18
3
20
ns
tOEZ
tWEZ
Output disable time after OE high (see Note 6)
3
15
3
18
3
20
ns
Output disable time after W high (see Note 6)
3
15
3
18
3
20
ns
15
18
0
0
ns
NOTE 6: Maximum tREZ, tCEZ, tWEZ and tOEZ are specified when the output is no longer driven.
EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’44409-60
’44409P-60
’44409-70
’44409P-70
’44409-80
’44409P-80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tHPC
tCSH
Cycle time, EDO page-mode read or write
25
30
35
ns
Hold time, CAS from RAS
50
55
60
ns
tCHO
tDOH
Hold time, OE from CAS
10
10
10
ns
3
3
3
ns
tCAS
tWPE
Pulse duration, CAS
tOCH
tCP
Setup time, OE before CAS
Precharge time, CAS
tOEP
Precharge time, OE
Hold time, output from CAS
10
Pulse duration, W (output disable only)
POST OFFICE BOX 1443
10 000
12
10 000
15
10 000
ns
5
5
5
ns
10
10
10
ns
5
5
5
ns
5
5
5
ns
• HOUSTON, TEXAS 77251–1443
7
ADVANCE INFORMATION
PARAMETER
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’44409-60
’44409P-60
MIN
MAX
’44409-70
’44409P-70
MIN
MAX
’44409-80
’44409P-80
MIN
UNIT
MAX
ADVANCE INFORMATION
tRC
tRWC
Cycle time, random read or write (see Note 7)
110
130
150
ns
Cycle time, read-write (see Note 7)
150
175
200
ns
tPRWC
tRASP
Cycle time, EDO page-mode read-write
80
90
100
ns
Pulse duration, page mode, RAS low, (see Note 8)
60 100 000
70
100 000
tRAS
tRP
Pulse duration, nonpage mode, RAS low, (see Note 8)
60
70
10 000
Pulse duration, RAS high (precharge)
40
50
60
ns
tWP
tASC
Pulse duration, W
10
10
10
ns
Setup time, column address before CAS low
0
0
0
ns
tASR
tDS
Setup time, row address before RAS low
0
0
0
ns
Setup time, data before W low (see Note 9)
0
0
0
ns
tRCS
tCWL
Setup time, read before CAS low
0
0
0
ns
Setup time, W low before CAS high
10
12
15
ns
tRWL
tWCS
Setup time, W low before RAS high
10
12
15
ns
0
0
0
ns
tWSR
tCAH
Setup time, W high ( CBR refresh only )
10
10
10
ns
Hold time, column address after CAS low
10
15
15
ns
tDH
tRAH
Hold time, data after CAS low (see Note 9)
10
15
15
ns
Hold time, row address after RAS low
10
10
10
ns
tRCH
tRRH
Hold time, read after CAS high (see Note 10)
0
0
0
ns
0
0
0
ns
tWCH
tWHR
Hold time, write after CAS low ( early-write operation only )
10
15
15
ns
Hold time, W high ( CBR refresh only)
10
10
10
ns
tROH
tAWD
Hold time, RAS referenced to OE
10
10
10
ns
Delay time, column address to W low ( read-write operation only )
55
63
70
ns
tCHR
tCRP
Delay time, RAS low to CAS high ( CBR refresh only )
15
15
20
ns
Delay time, CAS high to RAS low
0
0
0
ns
tCSR
tCWD
Delay time, CAS low to RAS low ( CBR refresh only )
5
5
5
ns
Delay time, CAS low to W low ( read-write operation only )
40
46
50
ns
tOEH
tOED
Hold time, OE command
15
18
20
ns
Delay time, valid data in after OE high
15
18
20
ns
tRAD
tRAL
Delay time, RAS low to column address
15
Delay time, column address to RAS high
30
tCAL
tRCD
Delay time, column address to CAS high
20
Delay time, RAS low to CAS low ( see Note 11)
20
tRPC
Delay time, RAS high to CAS low ( CBR refresh only )
Setup time, W low before CAS low ( early-write operation only )
Hold time, read after RAS high (see Note 10)
NOTES: 7.
8.
9.
10.
11.
8
10 000
30
35
35
0
• HOUSTON, TEXAS 77251–1443
20
0
ns
80
ns
15
10 000
40
40
25
45
All timing requirements assume tT = 5 ns.
In a read-write cycle, tRWD and tRWL must be observed.
Referenced to the later of CAS or W in write operations
The minimum value is measured when tRCD is set to tRCD min as a reference.
The minimum value is specified only to assure access time.
POST OFFICE BOX 1443
15
80 100 000
ns
30
52
20
0
ns
ns
60
ns
ns
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
Delay time, CAS low to RAS high
’44409-70
’44409P-70
’44409-80
’44409P-80
MIN
MIN
MIN
MAX
10
Delay time, RAS low to W low
12
85
’44409
tREF
Refresh time interval
tT
tWTH
Transition time
tCHS
tWTS
Hold time, CAS low after RAS high ( self refresh ) (TMS44409P only)
tCPS
tRPS
CAS precharge before self refresh
tRASS
’44409P
2
Hold time, write low (test mode)
MAX
15
98
UNIT
MAX
ns
110
ns
16
16
16
ms
128
128
128
ms
50
ms
50
2
50
2
10
10
10
ns
– 50
– 50
– 50
ns
10
10
10
ns
0
0
0
ns
RAS precharge after self refresh
110
130
150
ns
Self-refresh entry from RAS low (TMS44409P only)
100
100
100
µs
Setup time, write low (test mode)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ADVANCE INFORMATION
tRSH
tRWD
’44409-60
’44409P-60
9
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
1.31 V
RL
VCC = 5 V
+ 218 W
Output Under Test
R1
+ 828 W
R2
+ 295 W
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
ADVANCE INFORMATION
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
tCAS
tASR
CAS
tRAD
tCP
tASC
tRAH
A0 – A9
Row
tCAL
tRAL
Don’t Care
Column
tRCS
tRRH
tRCH
tCAH
W
Don’t Care
Don’t Care
tCAC
tCEZ
tREZ
tAA
DQ1 – DQ4
Hi-Z
Valid Data Out
See Note A
tCLZ
tRAC
tWEZ
tOEA
tWPE
tOEZ
tROH
OE
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCSH
tCAS
tASR
CAS
tCP
tASC
tRAL
tRAH
Row
Don’t Care
Column
tCWL
tRAD
W
ADVANCE INFORMATION
A0 – A9
tCAH
tRWL
tWCH
Don’t Care
tWCS
Don’t Care
tWP
tDH
tDS
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
OE
Figure 3. Early-Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCAS
tCSH
tASR
tASC
CAS
tCP
tRAL
ADVANCE INFORMATION
tRAH
tCAH
A0 – A9
Row
Don’t Care
Column
tCWL
tRAD
tRWL
W
Don’t Care
Don’t Care
tWP
tDS
tDH
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
tOED
tOEH
OE
Don’t Care
Don’t Care
Figure 4. Write-Cycle Timing
12
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
tCP
tRAH
tCAH
tRAD
A0 – A9
tT
tASC
Row
Don’t Care
Column
tCWL
tRCS
tRWL
tRWD
tWP
Don’t Care
tAWD
tCWD
W
tCAC
tDS
tAA
tDH
tCLZ
DQ1 – DQ4
Hi-Z
Data
Out
See Note A
tRAC
Data
In
Don’t Care
tOEZ
tOEA
tOED
OE
ADVANCE INFORMATION
CAS
tOEH
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRASP
RAS
tRP
tT
tRCD
tRSH
tCSH
tHPC
tCRP
tCAS
CAS
tCP
tRAH
tASC
tCAL
tASR
tRAL
ADVANCE INFORMATION
tCAH
A0 – A9
Row
Column #1
Column #2
Column #3
tRAD
tRCH
tOEA
OE
tRCS
tCAC
tRRH
tDOH
W
tCAC
tAA
tAA
tCEZ
tCPA
tRAC
tREZ
tCLZ
DQ
DATA #1
DATA #2
DATA #3
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. Access time is tCPA- or tAA- dependent.
Figure 6. Extended-Data-Out Read Cycle
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCHS
tHPC
tCAS
tCP
tRSH
CAS
tASR
tRAH
Row
A0 – A9
tASC
tCAL
tCAH
tRAL
Column #1
Column #2
Column #3
tOCH
ADVANCE INFORMATION
tRAD
tCHO
tOEP
tOEP
OE
tOEA
tRRH
tRCS
tRCH
tOEA
tCAC
W
tDOH
tCLZ
tOEZ
tCAC
tREZ
tOEZ
tRAC
DQ
tCEZ
tCPA
tAA
tAA
DATA #1
DATA #1
DATA #2
DATA #3
Figure 7. Extended-Data-Out Read-Cycle With OE Control
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRASP
RAS
tRP
tCSH
tHPC
tRSH
tCP
tCRP
tCAS
CAS
tASR
tRAH
tCAH
tASC
tCAL
tRAL
A0 – A9
Row
Column #1
Column #2
Column #3
tRAD
ADVANCE INFORMATION
OE
tOEA
tCAC
tRCS
tCAC
tWPE
tRCH
tRRH
W
tDOH
tCAC
tWEZ
tAA
tCPA
tCLZ
tAA
tCPA
tCEZ
tAA
tREZ
tRAC
DQ
DATA #1
DATA #2
Figure 8. Extended-Data-Out Read-Cycle With W Control
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
DATA #3
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tHPC
tRCD
tCAS
tASC
tRAH
tCP
tCAH
tRAL
tASR
tCAL
Row
Column
Don’t Care
Column
tCWL
tCWL
tRAD
tRWL
tWP
W
Don’t Care
Don’t Care
See Note A
tDH
tDH
tDS
tDS
DQ1 – DQ4
ADVANCE INFORMATION
CAS
A0 – A9
tCRP
tRSH
Don’t Care
tOEH
See Note A
Valid
In
Valid Data In
tOEH
tOED
Don’t Care
OE
Don’t Care
Don’t Care
NOTES: A. Referenced to CAS or W, whichever occurs last.
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are
not violated.
Figure 9. EDO-Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRSH
tPRWC
tRCD
tCAS
tASR
tASC
CAS
tCAL
tCAH
tRAL
tRAD
Row
A0 – A9
tCRP
tCP
Column 1
Column 2
Don’t Care
tRAH
tCWL
tCWD
ADVANCE INFORMATION
tAWD
tRWL
tWP
tRWD
W
tRCS
tCPA
tAA
tDH
tRAC
Valid Out 2
See Note A
tDS
tCAC
Valid
In 1
DQ1 – DQ4
tCLZ
tOEA
tOEH
Valid
In 2
Valid
Out 1
tOEZ
tOED
tOEH
OE
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated.
Figure 10. EDO Read-Write-Cycle Timing
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tRP
tT
CAS
Don’t Care
tRPC
tRAH
tASR
Don’t Care
Row
W
Don’t Care
DQ1 – DQ4
Don’t Care
OE
Don’t Care
Don’t Care
Row
ADVANCE INFORMATION
A0 – A9
Figure 11. RAS-Only Refresh-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWSR
tWHR
W
ADVANCE INFORMATION
A0 – A9
Don’t Care
OE
Don’t Care
Hi-Z
DQ1 – DQ4
Figure 12. Automatic-CBR-Refresh-Cycle Timing
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
CAS
tCAH
ADVANCE INFORMATION
tASC
tRAH
tASR
A0 – A9
Row
Col
Don’t Care
tRRH
tWHR
tWHR
tRCS
tWSR
tWHR
tWSR
tWSR
W
tCAC
tAA
tREZ
tRAC
tCEZ
Valid Data Out
DQ1 – DQ4
tCLZ
OE
tOEZ
tOEA
Figure 13. Hidden-Refresh Cycle (Read)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
Memory Cycle
Refresh Cycle
tRAS
Refresh Cycle
tRP
tRAS
tRP
RAS
tCHR
tCAS
CAS
tCAH
tASC
ADVANCE INFORMATION
tRAH
tASR
Row
A0 – A9
Don’t Care
Col
tRRH
tWHR
tWCS
tWSR
tWP
W
tDS
tWCH
tDH
DQ1 – DQ4
Valid Data
Don’t Care
Don’t Care
OE
Figure 14. Hidden-Refresh Cycle (Write)
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
PARAMETER MEASUREMENT INFORMATION
tRASS
RAS
tRPS
tRPC
tCSR
tCHS
A0 – A9
Don’t Care
W
Don’t Care
OE
Don’t Care
ADVANCE INFORMATION
CAS
tREZ
DQ1 – DQ4
Hi-Z
Figure 15. Self Refresh Timing
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWTS
tWTH
Don’t Care
W
A0 – A9
Don’t Care
OE
Don’t Care
Hi-Z
DQ1 – DQ4
Figure 16. Test-Mode Entry Cycle
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
MECHANICAL DATA
DJ (R-PDSO-J20/26)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.680 (17,27)
0.670 (17,02)
26
22
18
14
0.340 (8,64)
0.330 (8,38)
0.305 (7,75)
0.295 (7,49)
1
5
9
13
ADVANCE INFORMATION
0.032 (0,81)
0.026 (0,66)
0.008 (0,20) NOM
0.106 (2,69) MAX
0.148 (3,76)
0.128 (3,25)
Seating Plane
0.020 (0,51)
0.016 (0,41)
0.004 (0,10)
0.007 (0,18) M
0.275 (6,99)
0.260 (6,60)
0.050 (1,27)
4040094-2 / B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS44409, TMS44409P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS563 – JULY1995
MECHANICAL DATA
DGA (R-PDSO-G20/26)
PLASTIC SMALL-OUTLINE PACKAGE
0.020 (0,50)
0.012 (0,30)
0.050 (1,27)
26
0.008 (0,21) M
14
0.371 (9,42)
0.355 (9,02)
0.304 (7,72)
0.296 (7,52)
0.006 (0,15) NOM
13
0.679 (17,24)
0.671 (17,04)
ADVANCE INFORMATION
1
Gage Plane
0.010 (0,25)
0°– 5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.047 (1,20) MAX
0.004 (0,10)
0.000 (0,00) MIN
4040265-2 / C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
device symbolization (TMS44409 illustrated)
-SS
TI
Speed ( - 60, - 70, - 80)
TMS44409 DGA
Package Code
W
B
Y
M LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
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