TI TMS45160P

TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
D
D
D
D
D
D
D
D
D
D
D
D
D
This data sheet is applicable to all TMS45160/Ps
symbolized with Revision “D” and subsequent
revisions as described on page 21.
Organization . . . 262144 × 16
5-V Supply (±10% Tolerance)
Performance Ranges:
’45160/P-60
’45160/P-70
’45160/P-80
DGE PACKAGE
( TOP VIEW )
DZ PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
NC
NC
W
RAS
NC
A0
A1
A2
A3
VCC
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
tRAC
tCAC
tAA
CYCLE
MAX
MAX
MAX
MIN
60 ns
15 ns
30 ns
110 ns
70 ns
20 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
Enhanced-Page-Mode Operation With
xCAS-Before-RAS (xCBR) Refresh
Long Refresh Period
512-Cycle Refresh in 8 ms (Max)
64 ms Max for Low Power With
Self-Refresh Version ( TMS45160P)
3-State Unlatched Output
Low Power Dissipation
Texas Instruments EPIC CMOS Process
All Inputs, Outputs, and Clocks Are TTL
Compatible
High-Reliability, 40-Lead, 400-Mil-Wide
Plastic Surface-Mount (SOJ) Package and
40/44-Lead Thin Small-Outline Package
( TSOP)
Operating Free-Air Temperature Range
0°C to 70°C
Low Power With Self-Refresh Version
Upper and Lower Byte Control During Read
and Write Operations
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
NC
NC
W
RAS
NC
A0
A1
A2
A3
VCC
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
A0 – A8
DQ0 – DQ15
LCAS
NC
OE
RAS
UCAS
VCC
VSS
W
Address Inputs
Data In / Data Out
Lower Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
Upper Column-Address Strobe
5-V Supply
Ground
Write Enable
description
The TMS45160 series are high-speed, 4 194 304-bit dynamic random-access memories organized as 262 144
words of 16 bits each. The TMS45160P series are high-speed, low-power, self-refresh 4 194 304-bit dynamic
random-access memories organized as 262 144 words of 16 bits each. They employ state-of-the-art EPIC
( Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low power at low
cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power dissipation
is as low as 770 mW operating and 11 mW standby on 80-ns devices. All inputs and outputs, including clocks,
are compatible with Series 74 TTL. All addresses and data-in lines are latched on chip to simplify system design.
Data out is unlatched to allow greater system flexibility.
The TMS45160 and TMS45160P are each offered in a 40-lead plastic surface-mount SOJ package ( DZ suffix)
and a 40/44-lead plastic surface-mount small-outline ( TSOP) package ( DGE suffix). These packages are
characterized for operation from 0°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
operation
dual CAS
Two CAS pins ( LCAS– UCAS) are provided to give independent control of the 16 data I/O pins ( DQ0– DQ15)
with LCAS corresponding to DQ0 – DQ7 and UCAS corresponding to DQ8 – DQ15. For read or write cycles, the
column address is latched on the first xCAS falling edge. Each xCAS going low enables its corresponding DQx
pins with data associated with the column address latched on the first falling xCAS edge. All address setup and
hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS low to valid data out
( see parameter tCAC ) is measured from each individual xCAS to its corresponding DQx pins.
In order to latch in a new column address, both xCAS pins must be brought high. The column precharge time
( see parameter tCP ) is measured from the last xCAS rising edge to the first falling xCAS edge of the new cycle.
Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH. During tCLCH, at
least one xCAS must be brought low before the other xCAS is taken high.
For early-write cycles, the data is latched on the first falling edge of xCAS. Only the DQs that have the
corresponding xCAS low are written into. Each xCAS must meet tCAS minimum in order to ensure writing into
the storage cell. In order to latch a new address and new data, both xCAS pins must go high and meet tCP .
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. With minimum xCAS page cycle time, all 512 columns specified by column
addresses A0 through A8 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The first falling edge
of xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after tRAH ( row-address hold time ) has been satisfied, usually
well in advance of the falling edge of xCAS. In this case, data is obtained after tCAC max ( access time from xCAS
low) if tAA max ( access time from column address) has been satisfied. In the event that column addresses for
the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined
by tCPA ( access time from rising edge of the last xCAS).
address ( A0– A8)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row-address bits are set
up on A0 through A8 and latched onto the chip by RAS. Then, nine column-address bits are set up on A0 through
A8 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling edge of
RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder.
xCAS is used as a chip select, activating its corresponding output buffer and latching the address bits into the
column-address buffers.
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. W can be driven from the standard TTL circuits without a pullup resistor. The data input lines
are disabled when the read mode is selected. When W goes low prior to xCAS ( early write ) , data out remains
in the high-impedance state for the entire cycle, permitting a write operation with OE grounded.
2
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•
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
data in (DQ0 – DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first occurring xCAS with setup and hold times referenced to data in. In a
delayed-write or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and
hold times referenced to data in. In a delayed-write or read-modify-write cycle, OE must be high to bring the
output buffers to the high-impedance state prior to impressing data on the I/O lines.
data out (DQ0 – DQ15)
The 3-state output buffer provides direct TTL compatibility ( no pullup resistor required ) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance ( floating)
state until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access-time interval
tCAC ( which begins with the negative transition of xCAS ) as long as tRAC and tAA are satisfied.
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the
low-impedance state. They remain in the low-impedance state until either OE or xCAS is brought high.
RAS-only refresh
A refresh operation must be performed at least once every 8 ms ( 64 ms for TMS45160P ) to retain data. This
can be achieved by strobing each of the 512 rows ( A0– A8). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding all xCAS at the high ( inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS ( see parameter tCSR ) and holding
it low after RAS falls ( see parameter tCHR ) . For successive xCBR refresh cycles, xCAS can remain low while
cycling RAS. The external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 500-µA refresh current is available on the
TMS45160P. Data integrity is maintained using xCBR refresh with a period of 125 µs holding
RAS low for less than 1 µs. To minimize current consumption, all input levels must be at CMOS levels
( VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V ).
self refresh ( TMS45160P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100 µs. The chip is refreshed internally by an on-board oscillator. No external address
is required since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and xCAS are brought high to satisfy tCHS. Upon exiting the self-refresh mode, a burst refresh (refresh a full set
of row addresses) must be executed before continuing with normal operation. This ensures that the DRAM is
fully refreshed.
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•
3
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight RAS cycles is
required after power up to the full VCC level.These eight initialization cycles must include at least one refresh
(RAS-only or xCBR) cycle.
4
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•
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
logic symbol†
RAM 256K × 16
A0
A1
A2
A3
A4
A5
A6
A7
A8
RAS
LCAS
16
17
18
19
22
23
24
25
26
14
29
20D9/21D0
A
0
262 143
20D17/21D8
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21
G24
&
23C22
31
UCAS
28
C21
G34
&
23C32
31
Z31
24,25EN27
W 13
27
OE
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
3
4
5
7
8
9
10
31
32
33
34
36
37
38
39
23,21D
34,25EN37
G25
A,22D
∇ 26,27
A, Z26
A,32D
∇ 36,37
A, Z36
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown are for the DZ package.
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•
5
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
functional block diagram
RAS UCAS LCAS
W
OE
Timing and Control
A0
A1
9
Column Decode
Sense Amplifiers
ColumnAddress
Buffers
128K Array
128K Array
A8
RowAddress
Buffers
128K Array
R
o
w
128K Array
16
D
e
c
o
d
e
16
9
16
128K Array
16
16 I/O
Buffers
DataIn
Reg.
DataIn
Reg.
16
16
DQ0 – DQ15
128K Array
9
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
2.4
6.5
V
Low-level input voltage (see Note 2)
–1
0.8
V
Supply voltage
0
V
V
TA
Operating free-air temperature
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
6
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•
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output
voltage
IOH = – 5 mA
VOL
Low-level output
voltage
IOL = 4.2 mA
II
Input current
(leakage)
IO
ICC1†§
’45160 - 60
’45160P - 60
’45160 - 70
’45160P - 70
’45160 - 80
’45160P - 80
MIN
MIN
MIN
MAX
2.4
2.4
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Read- or write-cycle
current
VCC = 5.5 V,
Minimum cycle
180
160
140
mA
2
2
2
mA
1
1
1
mA
350
350
350
µA
VIH = 2.4 V (TTL),
After 1 memory cycle,
RAS and xCAS high
ICC2
MAX
Standby current
VIH = VCC – 0.2 V (CMOS),
After 1 memory cycle,
cycle
RAS and xCAS high
’45160
’45160P
ICC3‡
Average refresh
current (RAS-only
refresh or CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
(RAS only),
xCAS high (CBR only),
RAS low after xCAS low
180
160
140
mA
ICC4†§
Average page current
VCC = 5.5 V,
RAS low,
160
140
120
mA
ICC5¶
Battery-backup
operating current
(equivalent refresh
time is 64 ms);
CBR only
tRC = 125 µs,
tRAS ≤ 1 µs,
VCC – 0.2 V ≤ VIH ≤ 6.5 V,
0 V ≤ VIL ≤ 0.2 V, W and OE = VIH,
Address and data stable
500
500
500
µA
ICC6†¶
Self-refresh current
xCAS < 0.2 V,
RAS < 0.2 V,
tRAS and tCAS > 1000 ms
400
400
400
µA
tPC = MIN,
xCAS cycling
† Measured with outputs open
‡ Measured with a maximum of one address change while RAS = VIL
§ Measured with a maximum of one address change while xCAS = VIH
¶ For TMS45160P only
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz# (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A8
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, xCAS and RAS
7
pF
Ci(W)
Input capacitance, W
7
pF
7
pF
Co
Output capacitance
# Capacitance measurements are made on a sample basis only.
NOTE 3: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V.
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7
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
’45160 - 60
’45160P - 60
’45160 - 70
’45160P - 70
’45160 - 80
’45160P - 80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tCAC
tAA
Access time from xCAS low
15
20
20
ns
Access time from column address
30
35
40
ns
tRAC
tOEA
Access time from RAS low
60
70
80
ns
Access time from OE low
15
20
20
ns
tCPA
tCLZ
Access time from column precharge
45
ns
Delay time, xCAS low to output in low impedance
0
tOFF
tOEZ
Output disable time after xCAS high (see Note 4)
0
15
0
20
0
20
ns
Output disable time after OE high (see Note 4)
0
15
0
20
0
20
ns
35
40
0
0
ns
NOTE 4: tOFF and tOEZ are specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
’45160 - 60
’45160P - 60
’45160 - 70
’45160P - 70
’45160 - 80
’45160P - 80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tRC
tWC
Cycle time, read (see Note 6)
110
130
150
ns
Cycle time, write
110
130
150
ns
tRWC
tPC
Cycle time, read-write/read-modify-write
155
185
205
ns
Cycle time, page-mode read or write (see Note 7)
40
45
50
ns
tPRWC
tRASP
Cycle time, page-mode read-modify-write
85
90
105
ns
Pulse duration, RAS low, page mode (see Note 8)
60 100 000
70 100 000
80 100 000
ns
tRAS
tCAS
Pulse duration, RAS low, nonpage mode (see Note 8)
60
10 000
70
10 000
80
10 000
ns
Pulse duration, xCAS low (see Note 9)
15
10 000
20
10 000
20
10 000
ns
tCP
tRP
Pulse duration, xCAS high
10
10
10
ns
Pulse duration, RAS high (precharge)
40
50
60
ns
tWP
tASC
Pulse duration, write
15
15
15
ns
Setup time, column address before xCAS low
0
0
0
ns
tASR
tDS
Setup time, row address before RAS low
0
0
0
ns
Setup time, data before W low (see Note 10)
0
0
0
ns
tRCS
tCWL
Setup time, read before xCAS low
0
0
0
ns
Setup time, W low before xCAS high
15
20
20
ns
tRWL
tWCS
Setup time, W low before RAS high
15
20
20
ns
0
0
0
ns
Setup time, W low before xCAS low (see Note 11)
NOTES: 5.
6.
7.
8.
9.
10.
11.
8
Timing measurements are referenced to VIL max and VIH min.
All cycle times assume tT = 5 ns.
To assure tPC min, tASC should be ≥ tCP .
In a read-modify-write cycle, tRWD and tRWL must be observed.
In a read-modify-write cycle, tCWD and tCWL must be observed.
Referenced to the later of xCAS or W in write operations
Early-write operation only
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•
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Note 5)
’45160 - 60
’45160P - 60
’45160 - 70
’45160P - 70
’45160 - 80
’45160P - 80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tCAH
tDHR
Hold time, column address after xCAS low (see Note 10)
10
15
15
ns
Hold time, data after RAS low (see Note 12)
30
35
35
ns
tDH
tAR
Hold time, data after xCAS low (see Note 10)
10
15
15
ns
Hold time, column address after RAS low (see Note 12)
30
35
35
ns
tRAH
tRCH
Hold time, row address after RAS low
10
10
10
ns
Hold time, read after xCAS high (see Note 13)
0
0
0
ns
tRRH
tWCH
Hold time, read after RAS high (see Note 13)
0
0
0
ns
Hold time, write after xCAS low (see Note 13)
10
15
15
ns
tWCR
tCLCH
Hold time, write after RAS low (see Note 14)
30
35
35
ns
5
5
5
ns
tAWD
tCHR
Delay time, column address to W low (see Note 15)
55
65
70
ns
Delay time, RAS low to xCAS high (see Note 11)
15
15
20
ns
tCRP
tCSH
Delay time, xCAS high to RAS low
0
0
0
ns
Delay time, RAS low to xCAS high
60
70
80
ns
tCSR
tCWD
Delay time, xCAS low to RAS low (see Note 11)
10
10
10
ns
Delay time, xCAS low to W low (see Note 15)
40
50
50
ns
tOEH
tOED
Hold time, OE command
15
20
20
ns
Delay time, OE high before data at DQ
15
20
20
ns
tROH
tRAD
Delay time, OE low to RAS high
10
10
10
ns
Delay time, RAS low to column address (see Note 16)
15
tRAL
tCAL
Delay time, column address to RAS high
30
35
40
ns
Delay time, column address to xCAS high
30
35
40
ns
tRCD
tRPC
Delay time, RAS low to xCAS low (see Note 16)
20
Delay time, RAS high to xCAS low (see Note 11)
0
0
0
ns
tRSH
tRWD
Delay time, xCAS low to RAS high
15
20
20
ns
Delay time, RAS low to W low (see Note 15)
85
100
110
ns
tCPR
tRPS
Pulse duration, xCAS precharge before self refresh
0
0
0
ns
Pulse duration, RAS precharge after self refresh
110
130
150
ns
tRASS
tCHS
Pulse duration, self refresh entry from RAS low
100
100
100
µs
Hold time, xCAS low after RAS high (for self refresh)
– 50
– 50
– 50
ns
tREF
Refresh time interval
Hold time, xCAS low to xCAS high
’45160
’45160P
30
45
•
•
20
35
50
15
20
40
60
8
8
8
64
64
64
tT
Transition time
2
50
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
10. Referenced in the later of xCAS or W in write operations.
11. Early-write operation only
12. The minimum value is measured when tRCD is set to tRCD min as a reference.
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. xCBR refresh only
15. Read-modify-write operation only
16. Maximum value specified only to assure access time
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15
2
50
2
50
ns
ns
ms
ns
9
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC = 5 V
RL = 218 Ω
R1 = 828 Ω
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(b) ALTERNATE LOAD CIRCUIT
(a) LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
10
R2 = 295 Ω
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TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tT
tRP
tRCD
tCAS
UCAS
tCLCH
(see Note A)
tCP
tCRP
LCAS
tCSH
tRSH
tRAD
tRAH
tASC
tCAL
tASR
A0 – A8
tRAL
Row
Column
Don’t Care
tAR
tRRH
tCAH
tRCS
W
tRCH
Don’t Care
Don’t Care
tCAC
tAA
tOFF
See Note B
tCLZ
Valid Data Out
DQ0 – DQ15
tRAC
tOEZ
tOEA
tROH
OE
NOTES: A.
B.
C.
D.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
tCAC is measured from xCAS to its corresponding DQx.
xCAS order is arbitrary.
Figure 2. Read-Cycle Timing
•
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•
11
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
RAS
tT
tRP
tRCD
tCAS
UCAS
tCLCH
(see Note A)
tCP
LCAS
tASR
tCRP
tCSH
tRSH
tRAH
tASC
tCAL
A0 – A8
Row
tRAL
Column
Don’t Care
tAR
tCAH
tCWL
tRAD
tRWL
W
Don’t Care
Don’t Care
tWCR
tWP
tDH (see Note B)
tDHR
Valid Data In
DQ0 – DQ15
tDS
tOED
tOEH
OE
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. Later of xCAS or W in write operations
C. xCAS order is arbitrary.
Figure 3. Write-Cycle Timing
12
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TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
RAS
tT
tRP
tRCD
tCSH
tCRP
tCAS
UCAS
tRSH
tCLCH
(see Note A)
LCAS
tRAD
tCP
tASR
tRAH
tASC
tCAL
tRAL
A0 – A8
Column
Address
Row Address
Don’t Care
tCAH
tAR
tWCS
W
tWCH
Don’t Care
Don’t Care
tCWL
tWCR
DQ0 – DQ15
Don’t Care
tRWL
tWP
Don’t Care
Valid Data In
tDH
tDHR
tDS
OE
Don’t Care
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
Figure 4. Early-Write-Cycle Timing
•
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•
13
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tRCD
tCAS
UCAS
tCSH
tCRP
tCLCH
tAR
tCP
(see Note A)
tRSH
tRAD
LCAS
tRAH
tASC
tASR
A0 – A8
Column
Row
Don’t Care
tCAH
tAWD
tRWL
tCWD
tRCS
W
tCWL
tWP
Don’t Care
Don’t Care
tRWD
See Note B
DQ8 – DQ15
Valid Out
Don’t Care
Don’t Care
tAA
tDH
tCAC
tDS
tRAC
tOEZ
tOEA
OE
tOED
See Note B
DQ0 – DQ7
Valid Out
Don’t Care
Valid In
Don’t Care
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
C. xCAS order is arbitrary.
Figure 5. Read-Modify-Write-Cycle Timing
14
•
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TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRCD
tCRP
UCAS
tRSH
tPC
tCSH
tCAS
tASR
LCAS
tCP
tAR
tRAH
tCAL
tASC
tCAH
A0 – A8
Row
Column
tRAL
Don’t Care
Column
Don’t Care
tRAD
W
tRCH
Don’t
Care
Don’t
Care
tCAC
(see Note A)
tAA
tRCS
tRRH
tRAC
tCLZ
Valid
Out
DQ8 – DQ15
tOFF
See Note B
tCPA
tAA
Valid
Out
DQ0 – DQ7
tOEZ
Valid
Out
tOEA
OE
NOTES: A. tCAC is measured from xCAS to its corresponding DQx.
B. Access time is tCPA or tAA dependent.
C. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
D. xCAS order is arbitrary.
E. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
•
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15
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRSH
UCAS
tCLCH
(see Note A)
tRCD
tCP
tCSH
LCAS
tCRP
tPC
tCAS
tASR
tCAH
tAR
tCAL
tASC
tRAH
A0 – A8
tRAL
Column
Row
tRAD
Don’t Care
tCWL
tCWL
tWP
tWCR
tDS
(see Note B)
W
Don’t Care
Column
tRWL
tWCH
Don’t Care
Don’t Care
Don’t Care
tDHR
DQ8 – DQ15
Valid In
tDH
DQ0 – DQ7
Valid In
See Note B
Valid In
Valid In
tOED
OE
NOTES: A.
B.
C.
D.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
Referenced to xCAS or W, whichever occurs last
xCAS order is arbitrary.
A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
Figure 7. Enhanced-Page-Mode Write-Cycle Timing
16
•
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TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRCD
tRSH
tCRP
tPRWC
tCAS
UCAS
tCP
tCLCH
(see Note A)
LCAS
tASR
tASC
tCAH
tRAD
A0 – A8
Row
Column
Column
tCWD
tAWD
tRAH
tWP
tCWL
tRWL
tRWD
W
tCAC
(see Note B)
tRCS
tCPA
tDS
tAA
tRAC
See Note C
tCLZ
Valid In
DQ0 – DQ15
tOEH
Valid Out
Valid In
Valid Out
tOEA
tOEH
tOEZ
tOED
OE
NOTES: A.
B.
C.
D.
E.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
Output can go from the high-impedance state to an invalid data state prior to the specified access time.
xCAS order is arbitrary.
A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications are
not violated.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
•
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•
17
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tT
xCAS
See Note A
Don’t Care
tASR
A0 – A8
Don’t Care
tRP
tRPC
tRAH
Row
Don’t Care
Don’t Care
W
Hi-Z
DQ0 – DQ15
Don’t Care
OE
NOTE A: All xCAS must be high.
Figure 9. RAS-Only Refresh Timing
18
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Row
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRAS
RAS
tRP
tCHR
tCAS
xCAS
tASR
tRAH
tASC
tCAH
A0 – A8
Row
Don’t Care
Col
tRRH
tRCS
W
Don’t Care
tRAC
tCAC
tAA
tOFF
DQ0 – DQ15
Valid Data
tOEZ
tOEA
OE
Figure 10. Hidden-Refresh-Cycle Timing
•
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•
19
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tRPC
xCAS
tCSR
tCHR
tT
W
Don’t Care
A0 – A8
Don’t Care
OE
Don’t Care
Hi-Z
DQ0 – DQ15
NOTE A: Any xCAS can be used.
Figure 11. Automatic-CBR- Refresh-Cycle Timing
20
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TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tRASS
RAS
tRPS
tCSR
tRPC
tCHS
xCAS
tCPR
A0 – A8
Don’t Care
W
Don’t Care
OE
Don’t Care
Hi-Z
DQ0 – DQ15
NOTE A: Any xCAS can be used.
Figure 12. Self-Refresh-Cycle Timing
device symbolization (TMS45160 illustrated)
-SS
TI
Speed ( - 60, - 70, - 80)
Low-Power / Self-Refresh Designator (Blank or P)
TMS45160 DZ
Package Code
W
B
Y
M LLL
P
Asembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
•
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•
21
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160D – AUGUST 1992 – REVISED JUNE 1995
22
•
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•
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