TI TMS416800

TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
D
D
D
D
D
D
D
D
Organization . . . 2 097 152 × 8
Single 5 V Power Supply (±10% Tolerance)
Performance Ranges:
’41x800-60
’41x800-70
’41x800-80
DZ PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
DQ2
DQ3
W
RAS
A11†
A10
A0
A1
A2
A3
VCC
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
tRAC
tCAC
tAA
CYCLE
MAX
MAX
MAX
MIN
60 ns
15 ns
30 ns
110 ns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
Enhanced Page-Mode Operation With
CAS-Before-RAS ( CBR) Refresh
High-Impedance State Unlatched Output
High-Reliability Plastic 28-Lead
400-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package
Operating Free-Air Temperature Range
0°C to 70°C
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC ) Technology by
Texas Instruments (TI)
description
The TMS41x800 series is a set of high-speed,
16 777 216-bit dynamic random-access memories (DRAMs) organized as 2 097 152 words of
eight bits each. It employs TI’s state-of-the-art
EPIC technology for high performance, reliability,
and low power.
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VSS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
A0 – A11†
CAS
DQ0 – DQ7
OE
RAS
VCC
VSS
W
Address Inputs
Column-Address Strobe
Data In / Data Out
Output Enable
Row-Address Strobe
5V
Ground
Write Enable
† A11 is NC (no internal connection) for TMS417800.
These devices feature maximum RAS access
times of 60 ns, 70 ns, and 80 ns. All addresses and
data-in lines are latched on-chip to simplify
system design. Data out is unlatched to allow
greater system flexibility.
The TMS416800 and TMS417800 are offered in
a 28-lead plastic surface-mount SOJ package
(DZ suffix). This package is characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and TI are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
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1
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The
maximum number of columns that can be accessed is determined by tRASP , the maximum row-address strobe
(RAS) low time.
Unlike conventional page-mode DRAMs, the column-address buffers in these devices are activated on the
falling edge of RAS. The buffers act as transparent or flow-through latches while column-address strobe (CAS)
is high. The falling edge of CAS latches the column addresses and enables the output. This feature allows the
devices to operate at a higher data bandwidth than conventional page-mode parts because data retrieval begins
as soon as the column address is valid rather than when CAS goes low. This performance improvement is
referred to as enhanced page mode. A valid column address can be presented immediately after row-address
hold time has been satisfied, usually well in advance of the falling edge of CAS. In this case, data is obtained
after tCAC max (access time from CAS low) if tAA max (access time from column address) and tRAC (access time
from RAS) have been satisfied. In the event that column address for the next cycle is valid at the time CAS goes
high, access time for the next cycle is determined by the later occurrence of tCPA (access time from CAS
precharge) or tCAC.
address: A0 – A11 ( TMS416800) and A0 – A10 (TMS417800)
Twenty-one address bits are required to decode one of 2 097 152 storage cell locations. For the TMS416800,
12 row-address bits are set up on A0 through A11 and latched on the chip by the RAS. Nine column-address
bits are set up on A0 through A8. For the TMS417800, 11 row-address bits are set up on inputs A0 through A10
and latched on the chip by RAS. Ten column-address bits are set up on A0 through A9. All addresses must be
stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable because it activates the
sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffers and
latching the address bits into the column-address buffers.
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
data in (DQ0 – DQ7)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS, and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold time referenced
to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the
high-impedance state prior to impressing data on the I/O lines.
data out (DQ0 – DQ7)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with
the negative transition of CAS) as long as tRAC and tAA are satisfied.
2
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TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
RAS-only refresh
TMS416800
A refresh operation must be performed at least once every 64 ms to retain data. The refresh operation can be
achieved by strobing each of the 4 096 rows (A0 – A11). A normal read or write cycle refreshes all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving
power as the output buffers remain in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh.
TMS417800
A refresh operation must be performed at least once every 32 ms to retain data. The refresh operation can be
achieved by strobing each of the 2 048 rows (A0 – A10). A normal read or write cycle refreshes all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving
power as the output buffers remain in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. The hidden refresh operation
is accomplished by holding CAS at VIL after a read or write operation and cycling RAS after a specified
precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address
is generated internally.
CAS-before-RAS ( CBR) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR) and then holding it low
after RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling
RAS. The external address is ignored, and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full VCC level. The eight initialization cycles must include at least one refresh
( RAS-only or CBR ) cycle.
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3
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
logic symbol for TMS416800†
RAM 2M x 8
A0 10
A1 11
20D9/21D0
A2 12
A3 13
A4
16
A5 17
A6 18
A7 19
A8 20
A
0
2 097 151
20D17/21D8
A9 21
A10 9
20D18
A11 8
20D20
20D19
C20[ROW]
G23/[REFRESH ROW]
RAS
7
24[PWR DWN]
C21[COL]
G24
CAS 23
&
23C22
6
W
22
OE
DQ0
2
23,21D
24,25EN
G25
A,22D
∇ 26
A,Z26
DQ1 3
DQ2 4
DQ3 5
DQ4 24
DQ5 25
DQ6 26
DQ7 27
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
4
POST OFFICE BOX 1443
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TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
logic symbol for TMS417800†
RAM 2M x 8
A0 10
A1 11
20D10/21D0
A2 12
A3 13
A4
16
A5 17
A6 18
A
0
2 097 151
A7 19
A8 20
A9 21
A10 9
20D19/21D9
20D20
C20[ROW]
RAS
7
CAS 23
G23/[REFRESH ROW]
24[PWR DWN]
C21[COL]
G24
&
23C22
W
OE
6
22
DQ0 2
23,21D
24,25EN
G25
A,22D
∇ 26
A,Z26
DQ1 3
DQ2 4
DQ3 5
DQ4 24
DQ5 25
DQ6 26
DQ7 27
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
POST OFFICE BOX 1443
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5
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
functional block diagram
TMS416800
RAS
CAS
W
OE
Timing and Control
A0
A1
9
Column Decode
Sense Amplifiers
ColumnAddress
Buffers
R
o
w
A8
RowAddress
Buffers
8
256K Array
8
D
e
c
o
d
e
12
A9, A10, A11
DataIn
Reg.
256K Array
I/O
Buffers
64
8
8
DataOut
Reg.
256K Array
DQ0 – DQ7
12
TMS417800
RAS
CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
ColumnAddress
Buffers
256K Array
256K Array
A9
32
RowAddress
Buffers
A10
11
8
256K Array
R
o
w
D
e
c
o
d
256K Array e 256K Array
11
6
POST OFFICE BOX 1443
DataIn
Reg.
256K Array
• HOUSTON, TEXAS 77251–1443
8
32
I/O
Buffers
8
8
DataOut
Reg.
DQ0 – DQ7
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS41x800
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
2.4
6.5
V
Low-level input voltage (see Note 2)
–1
0.8
V
Supply voltage
0
V
V
TA
Operating free-air temperature
0
70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
POST OFFICE BOX 1443
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7
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TMS416800
PARAMETER
TEST CONDITIONS†
VOH
High-level output
voltage
VOL
Low-level output voltage
II
Input current (leakage)
IO
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
ICC1‡§
Read- or write-cycle
current
VCC = 5.5 V,
Minimum cycle
ICC2
Standby current
IOH = – 5 mA
’416800 - 60
MIN
’416800 - 70
MAX
2.4
IOL = 4.2 mA
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
MIN
’416800 - 80
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
± 10
± 10
± 10
µA
± 10
± 10
± 10
µA
80
70
60
mA
VIH = 2.4 V ( TTL),
After one memory cycle,
RAS and CAS high
2
2
2
mA
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and CAS high
1
1
1
mA
ICC3‡§
Average refresh current
(RAS-only refresh or
CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
80
70
60
mA
ICC4‡¶
Average page current
VCC = 5.5 V,
RAS low,
70
60
50
mA
tPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change while CAS = VIH
8
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TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS417800
PARAMETER
TEST CONDITIONS†
VOH
High-level output
voltage
VOL
Low-level output voltage
II
Input current (leakage)
IO
Output current
(leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
ICC1‡§
Read- or write-cycle
current
VCC = 5.5 V,
Minimum cycle
ICC2
Standby current
IOH = – 5 mA
’417800 - 60
MIN
’417800 - 70
MAX
2.4
IOL = 4.2 mA
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
MIN
’417800 - 80
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
± 10
± 10
± 10
µA
± 10
± 10
± 10
µA
110
100
90
mA
VIH = 2.4 V ( TTL),
After one memory cycle,
RAS and CAS high
2
2
2
mA
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
RAS and CAS high
1
1
1
mA
110
100
90
mA
70
60
50
mA
ICC3‡§
Average refresh current
(RAS-only refresh or
CBR)
VCC = 5.5 V,
Minimum cycle,
RAS cycling,
CAS high (RAS
only),
RAS low after CAS low (CBR)
ICC4‡¶
Average page current
VCC = 5.5 V,
RAS low,
tPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change while CAS = VIH
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9
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A11†
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, CAS and RAS
7
pF
Ci(W)
Input capacitance, W
7
pF
7
pF
Co
Output capacitance
† A11 is NC (no internal connection) for TMS417800.
NOTE 3: VCC = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x800 - 60
PARAMETER
MIN
MAX
’41x800 - 70
MIN
MAX
’41x800 - 80
MIN
MAX
UNIT
tAA
tCAC
Access time from column address
30
35
40
ns
Access time from CAS
15
18
20
ns
tCPA
tRAC
Access time from CAS precharge
35
40
45
ns
Access time from RAS
60
70
80
ns
tOEA
tCLZ
Access time from OE
20
ns
Delay time, CAS to output in the low-impedance state
0
0
0
ns
tOH
tOHO
Output data hold time from CAS
3
3
3
ns
Output data hold time from OE
3
3
3
tOFF
tOEZ
Output buffer turn-off delay from CAS (see Note 5)
0
15
0
18
0
20
ns
Output buffer turn-off delay from OE (see Note 5)
0
15
0
18
0
20
ns
15
NOTES: 4. With ac parameters, it is assumed that tT = 5 ns.
5. tOFF and tOEZ are specified when the output is no longer driven.
10
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18
ns
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x800 - 60
’41x800 - 70
’41x800 - 80
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tRC
tWC
Cycle time, read
110
130
150
ns
Cycle time, write
110
130
150
ns
tRWC
tPC
Cycle time, read-write
155
181
205
ns
Cycle time, page-mode read or write (see Note 6)
40
45
50
ns
tPRWC
tRASP
Cycle time, page-mode read-write
85
96
105
ns
Pulse duration, RAS active, page mode (see Note 7)
60 100 000
70 100 000
80 100 000
ns
tRAS
tCAS
Pulse duration, RAS active, nonpage mode (see Note 7)
60
10 000
70
10 000
80
10 000
ns
Pulse duration, CAS active (see Note 8)
15
10 000
18
10 000
20
10 000
ns
tCP
tRP
Pulse duration, CAS precharge
10
10
10
ns
Pulse duration, RAS precharge
40
50
60
ns
tWP
tASC
Pulse duration, write command
10
10
10
ns
Setup time, column address
0
0
0
ns
tASR
tDS
Setup time, row address
0
0
0
ns
Setup time, data-in (see Note 9)
0
0
0
ns
tRCS
tCWL
Setup time, read command
0
0
0
ns
Setup time, write command before CAS precharge
15
18
20
ns
tRWL
Setup time, write command before RAS precharge
15
18
20
ns
tWCS
Setup time, write command before CAS active (early-write
only)
0
0
0
ns
tCSR
tCAH
Setup time, CAS referenced to RAS (CBR refresh only)
5
5
5
ns
Hold time, column address
10
15
15
ns
tDH
tRAH
Hold time, data-in (see Note 9)
10
15
15
ns
Hold time, row address
10
10
10
ns
tRCH
tRRH
Hold time, read command referenced to CAS (see Note 10)
0
0
0
ns
Hold time, read command referenced to RAS (see Note 10)
0
0
0
ns
tWCH
tRHCP
Hold time, write command during CAS active (early-write only)
10
15
15
ns
Hold time, RAS active from CAS precharge
35
40
45
ns
tOEH
tROH
Hold time, OE command
15
18
20
ns
Hold time, RAS referenced to OE
10
10
10
ns
NOTES: 4.
6.
7.
8.
9.
10.
With ac parameters, it is assumed that tT = 5 ns.
To ensure tPC min, tASC should be ≥ to tCP .
In a read-write cycle, tRWD and tRWL must be observed.
In a read-write cycle, tCWD and tCWL must be observed.
Referenced to the later of CAS or W in write operations
Either tRRH or tRCH must be satisfied for a read cycle.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
11
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’41x800 - 60
MIN
MAX
’41x800 - 70
MIN
MAX
’41x800 - 80
MIN
MAX
UNIT
Delay time, column address to write command
(read-write operation only)
55
63
70
ns
tCHR
tCRP
Delay time, CAS referenced to RAS (CBR refresh only)
10
10
10
ns
5
5
5
ns
tCSH
tCWD
Delay time, RAS active to CAS precharge
60
70
80
ns
Delay time, CAS to write command (read-write operation only)
40
46
50
ns
tOED
tRAD
Delay time, OE to data in
15
18
20
Delay time, RAS to column address (see Note 11)
15
tRAL
tCAL
Delay time, column address to RAS precharge
30
35
40
ns
Delay time, column address to CAS precharge
30
35
40
ns
tRCD
tRPC
Delay time, RAS to CAS (see Note 11)
20
tRSH
tRWD
tCPW
tAWD
tREF
Delay time, CAS precharge to RAS
Delay time, RAS precharge to CAS
30
45
15
20
35
52
15
20
60
ns
ns
0
0
0
ns
Delay time, CAS active to RAS precharge
15
18
20
ns
Delay time, RAS to write command (read-write operation only)
85
98
110
ns
Delay time, CAS precharge to write command (read-write only)
60
68
75
Refresh time interval
64
64
64
’417800
32
32
32
3
30
3
30
3
PARAMETER MEASUREMENT INFORMATION
1.31 V
5V
828 Ω
218 Ω
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
Figure 1. Load Circuits for Timing Parameters
POST OFFICE BOX 1443
ns
’416800
tT
Transition time
NOTE 11: The maximum value is specified only to ensure access time.
12
ns
40
• HOUSTON, TEXAS 77251–1443
295 Ω
30
ms
ns
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
tCAS
tASR
CAS
tCP
tRAD
tASC
tRAH
tCAL
tRAL
Address
Row
Don’t Care
Column
tRCS
W
tRRH
tRCH
tCAH
Don’t Care
Don’t Care
tCAC
tOFF
tOH
tAA
DQ0 – DQ7
Hi-Z
Valid Data Out
See Note A
tCLZ
tRAC
tOHO
tOEA
tOEZ
tROH
OE
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
13
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
tCAL
RAS
tRP
tT
tRSH
tRCD
tCAS
tCRP
tCSH
tASR
tASC
CAS
tCP
tRAL
tRAH
Address
tCAH
Row
tCWL
tRWL
tWCH
tRAD
W
Don’t Care
Column
Don’t Care
Don’t Care
tWCS
tWP
tDH
tDS
DQ0 – DQ7
Don’t Care
Valid Data
Don’t Care
OE
Figure 3. Early-Write-Cycle Timing
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tWC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCSH
tCAS
tASR
CAS
tCP
tASC
tRAL
tCAL
tRAH
tCAH
Address
Row
Column
tCWL
tRAD
W
Don’t Care
tRWL
Don’t Care
Don’t Care
tWP
tDS
tDH
DQ0 – DQ7
Don’t Care
Valid Data
tOED
OE
Don’t Care
tOEH
Don’t Care
Don’t Care
Figure 4. Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
15
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
CAS
tCP
tRAH
tCAH
tRAD
Address
tT
tASC
Row
Don’t Care
Column
tCWL
tRCS
tRWD
tRWL
tAWD
tCWD
Don’t Care
W
tWP
tCAC
tDS
tDH
tAA
tCLZ
DQ0 – DQ7
Data
Out
See Note A
tRAC
tOEA
OE
tOHO
Data
In
tOEZ
Don’t Care
tOEH
tOED
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-Cycle Timing
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tRCD
tPC
tCSH
tCAS
CAS
tRAH
tASR
Address
tCRP
tRSH
tCP
Row
tCAL
tCAH
tASC
tRAL
Don’t Care
Column
Column
tAA†
tRRH
tRCH
tRCS
W
tCAC†
tRAD
tCPA†
tCAC
tAA
tOFF
tOH
tRAC
tCLZ
DQ0 – DQ7
Valid
Out
Valid
Out
See Note A
tOHO
tOEZ
OE
Don’t Care
tOEA
tOEA
tOHO
tOEZ
† Access time is tCPA-, tCAC-, or tAA-dependent.
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
17
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tPC
tCRP
tRSH
tRCD
tCAL
tASC
CAS
tCAS
tRAH
tCP
Address
tRAL
tCAH
tASR
Row
Don’t Care
Column
Column
tRAD
tCWL
tCWL
tWP
tRWL
tWCS
tWCH
W
Don’t Care
Don’t Care
Don’t Care
tDH
tDS
DQ0 – DQ7
Valid
In
Valid Data In
Don’t Care
Don’t Care
OE
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 7. Enhanced-Page-Mode Early-Write-Cycle Timing
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tPC
tCRP
tRSH
tRCD
tCAL
tCAS
tASC
CAS
tRAH
tCP
Address
tRAL
tCAH
tASR
Row
tRAD
tCWL
tCWL
tRWL
tWP
tDS
W
Don’t Care
Don’t Care
Don’t Care
tOEH
tDH
DQ0 – DQ7
Don’t Care
Don’t Care
Column
Column
Valid
In
Valid Data In
tOEH
tOED
Don’t Care
OE
Don’t Care
Don’t Care
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 8. Enhanced-Page-Mode Write-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
19
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRHCP
tCSH
tRSH
tPRWC
tRCD
CAS
tCRP
tCP
tCAS
tASR
tASC
tRAD
tCAH
Row
Address
Column
Don’t Care
Column
tRAH
tCWL
tCWD
tAWD
tRWD
tCPW
tRWL
tWP
W
tCPA
tRCS
tDH
tAA
tRAC
tDS
Valid Out†
tCAC
Valid
In
Valid
In
DQ0 – DQ7
tCLZ
tOEH
Valid Out
tOEZ
tOEA
tOED
tOEH
OE
tOHO
† Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
NOTE A: A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced-Page-Mode Read-Write-Cycle Timing
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tRP
tT
tRPC
Don’t Care
CAS
tASR
tRAH
Don’t Care
Address
Row
Don’t Care
Row
Don’t Care
W
DQ0 – DQ7
Hi-Z
Don’t Care
OE
Figure 10. RAS-Only Refresh-Cycle Timing
tRC
tRP
tRAS
RAS
tRPC
CAS
tCSR
tCHR
tT
W
Don’t Care
Address
Don’t Care
OE
Don’t Care
Hi-Z
DQ0 – DQ7
Figure 11. Automatic-CBR-Refresh-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Address
Row
Col
Don’t Care
tRRH
tRCS
Don’t Care
W
tRAC
tCAC
tAA
tOFF
Valid Data Out
DQ0 – DQ7
tCLZ
tOEZ
tOEA
OE
Figure 12. Hidden-Refresh-Cycle (Read) Timing
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
tRP
tRAS
tRAS
Refresh Cycle
tRP
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Row
Address
Don’t Care
Col
tRRH
tWCS
tWP
W
Don’t Care
tWCH
tDH
tDS
DQ0 – DQ7
Don’t Care
Valid Data
Don’t Care
OE
Figure 13. Hidden-Refresh-Cycle ( Write) Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS416800, TMS417800
2097152-WORD BY 8-BIT HIGH-SPEED DRAMS
SMKS883A – OCTOBER 1995 – REVISED MARCH 1996
MECHANICAL DATA
DZ (R-PDSO-J28)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.730 (18,54)
0.720 (18,29)
28
15
0.445 (11,30)
0.435 (11,05)
0.405 (10,29)
0.395 (10,03)
1
14
0.032 (0,81)
0.026 (0,66)
0.148 (3,76)
0.128 (3,25)
0.106 (2,69) NOM
Seating Plane
0.020 (0,51)
0.016 (0,41)
0.007 (0,18) M
0.004 (0,10)
0.380 (9,65)
0.360 (9,14)
0.008 (0,20) NOM
0.050 (1,27)
4040094-3 / C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
device symbolization (TMS416800 illustrated)
-SS
TI
TMS416800 DZ
Speed ( - 60, - 70, - 80)
Package Code
W
C
Y M LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
24
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
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