IRF IRF6644

PD - 96908C
IRF6644
DirectFET™ Power MOSFET ‚
l
l
l
l
l
l
l
l
l
Typical values (unless otherwise specified)
Lead and Bromide Free 
Low Profile (<0.7 mm)
Dual Sided Cooling Compatible 
Ultra Low Package Inductance
Optimized for High Frequency Switching 
Ideal for High Performance Isolated Converter
Primary Switch Socket
Optimized for Synchronous Rectification
Low Conduction Losses
Compatible with existing Surface Mount Techniques 
VDSS
VGS
RDS(on)
100V max ±20V max 10.7mΩ@ 10V
Qg
Qgd
Vgs(th)
11.5nC
3.7V
tot
35nC
DirectFET™ ISOMETRIC
MN
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
SQ
SX
ST
MQ
MX
MN
MT
Description
The IRF6644 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the
lowest on-state resistance in a package that has the footprint of an SO-8 and only 0.7 mm profile. The DirectFET package is compatible with
existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques,
when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows dual sided
cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF6644 is optimized for primary side bridge topologies in isolated DC-DC applications, for wide range universal input Telecom applications
(36V - 75V), and for secondary side synchronous rectification in regulated DC-DC topologies. The reduced total losses in the device coupled
with the high level of thermal performance enables high efficiency and low temperatures, which are key for system reliability improvements,
and makes this device ideal for high performance isolated DC-DC converters.
Absolute Maximum Ratings
Parameter
Max.
Units
V
VDS
Drain-to-Source Voltage
100
VGS
Gate-to-Source Voltage
±20
e
e
@ 10V f
ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V
10.3
ID @ TA = 70°C
Continuous Drain Current, VGS @ 10V
8.3
ID @ TC = 25°C
Continuous Drain Current, VGS
60
IDM
Pulsed Drain Current
EAS
Single Pulse Avalanche Energy
IAR
Avalanche Current
g
g
82
h
220
mJ
6.2
A
14
0.12
TA= 25°C
(mΩ)
ID = 6.2A
DS(on)
0.08
Typical R
Typical R DS (on), (Ω)
A
0.04
TJ = 125°C
TJ = 25°C
0.00
4.0
6.0
8.0
10.0 12.0 14.0
VGS, Gate-to-Source Voltage (V)
VGS = 8.0V
12
VGS = 10V
VGS = 15V
11
10
16.0
Fig 1. Typical On-Resistance Vs. Gate Voltage
Notes:
 Click on this section to link to the appropriate technical paper.
‚ Click on this section to link to the DirectFET Website.
ƒ Surface mounted on 1 in. square Cu board, steady state.
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VGS = 7.0V
13
0
4
8
12
16
20
ID, Drain Current (A)
Fig 2. Typical On-Resistance Vs. Drain Current
„ TC measured with thermocouple mounted to top (Drain) of part.
… Repetitive rating; pulse width limited by max. junction temperature.
† Starting TJ = 25°C, L = 12mH, RG = 25Ω, IAS = 6.2A.
1
11/23/04
IRF6644
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min.
Conditions
Typ. Max. Units
VGS = 0V, ID = 250µA
BVDSS
Drain-to-Source Breakdown Voltage
100
–––
–––
∆ΒVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
–––
0.11
–––
V/°C Reference to 25°C, ID = 1mA
RDS(on)
Static Drain-to-Source On-Resistance
–––
10.7
13
mΩ
V
VGS = 10V, ID = 10.3A c
VDS = VGS, ID = 150µA
VGS(th)
Gate Threshold Voltage
2.8
–––
4.8
V
∆VGS(th)/∆TJ
Gate Threshold Voltage Coefficient
–––
-10
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
20
µA
VDS = 100V, VGS = 0V
–––
–––
250
VDS = 80V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
IGSS
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
gfs
Forward Transconductance
15
–––
–––
Qg
VGS = -20V
S
VDS = 10V, ID = 6.2A
Total Gate Charge
–––
35
47
Qgs1
Pre-Vth Gate-to-Source Charge
–––
8.0
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
1.6
–––
Qgd
Gate-to-Drain Charge
–––
11.5
17.3
ID = 6.2A
Qgodr
See Fig. 17
VDS = 50V
nC
VGS = 10V
Gate Charge Overdrive
–––
13
–––
Qsw
Switch Charge (Qgs2 + Qgd)
–––
13.1
–––
Qoss
Output Charge
–––
17
–––
nC
RG
Gate Resistance
–––
1.0
2.0
Ω
td(on)
Turn-On Delay Time
–––
17
–––
VDD = 50V, VGS = 10Vc
tr
Rise Time
–––
26
–––
ID = 6.2A
td(off)
Turn-Off Delay Time
–––
34
–––
tf
Fall Time
–––
16
–––
Ciss
Input Capacitance
–––
2210
–––
Coss
Output Capacitance
–––
420
–––
Crss
Reverse Transfer Capacitance
–––
100
–––
ƒ = 1.0MHz
Coss
Output Capacitance
–––
2120
–––
VGS = 0V, VDS = 1.0V, f=1.0MHz
Coss
Output Capacitance
–––
240
–––
VGS = 0V, VDS = 80V, f=1.0MHz
ns
VDS = 16V, VGS = 0V
RG=6.2Ω
VGS = 0V
pF
VDS = 25V
Diode Characteristics
Parameter
IS
Continuous Source Current
Min.
–––
Typ. Max. Units
–––
ISM
Pulsed Source Current
MOSFET symbol
10
(Body Diode)
A
–––
–––
Conditions
showing the
integral reverse
82
p-n junction diode.
(Body Diode)d
VSD
Diode Forward Voltage
–––
–––
1.3
V
TJ = 25°C, IS = 6.2A, VGS = 0V c
trr
Reverse Recovery Time
–––
42
63
ns
TJ = 25°C, IF = 6.2A, VDD = 50V
Qrr
Reverse Recovery Charge
–––
69
100
nC
di/dt = 100A/µs c
Notes:
 Pulse width ≤ 400µs; duty cycle ≤ 2%.
‚ Repetitive rating; pulse width limited by max. junction temperature.
2
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IRF6644
Absolute Maximum Ratings
c
Power Dissipation c
Power Dissipation f
Parameter
Max.
Units
2.8
W
Power Dissipation
PD @TA = 25°C
PD @TA = 70°C
PD @TC = 25°C
1.8
89
TP
Peak Soldering Temperature
TJ
Operating Junction and
TSTG
Storage Temperature Range
270
°C
-40 to + 150
Thermal Resistance
Parameter
Typ.
cg
dg
Junction-to-Ambient eg
Junction-to-Case fg
Max.
RθJA
Junction-to-Ambient
–––
45
RθJA
Junction-to-Ambient
12.5
–––
RθJA
RθJC
RθJ-PCB
Junction-to-PCB Mounted
20
–––
–––
1.4
1.0
–––
Units
°C/W
100
D = 0.50
0.20
0.10
0.05
0.02
0.01
Thermal Response ( Z thJA )
10
1
0.1
τJ
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.001
R1
R1
τJ
τ1
R2
R2
τ2
τ1
R3
R3
τC
τ
τ3
τ2
τ3
τ4
τi (sec)
Ri (°C/W)
R4
R4
τ4
Ci= τi/Ri
Ci i/Ri
0.6784
0.00086
17.299
0.57756
17.566
8.94
9.4701
106
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient 
Notes:
 Surface mounted on 1 in. square Cu board, steady state.
‚ Used double sided cooling , mounting pad.
ƒ Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
 Surface mounted on 1 in. square Cu
board (still air).
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„ TC measured with thermocouple incontact with top (Drain) of part.
… Rθ is measured at TJ of approximately 90°C.
ƒ Mounted to a PCB with
small clip heatsink (still air)
ƒ Mounted on minimum
footprint full size board with
metalized back and with small
clip heatsink (still air)
3
IRF6644
100
6.0V
TOP
10
BOTTOM
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
VGS
15V
10V
8.0V
7.0V
6.0V
≤ 60µs PULSE WIDTH
Tj = 25°C
1
6.0V
TOP
10
BOTTOM
≤ 60µs PULSE WIDTH
Tj = 150°C
1
0.1
1
10
100
0.1
VDS , Drain-to-Source Voltage (V)
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 4. Typical Output Characteristics
Fig 5. Typical Output Characteristics
100.00
2.0
ID = 10.3A
TJ = 150°C
TJ = 25°C
10.00
Typical R DS(on), (Normalized)
ID, Drain-to-Source Current(Α)
VGS
15V
10V
8.0V
7.0V
6.0V
TJ = -40°C
1.00
0.10
VDS = 10V
VGS = 10V
1.5
1.0
≤ 60µs PULSE WIDTH
0.01
3.0
4.0
5.0
6.0
0.5
7.0
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
ID= 6.2A
Ciss
Coss
Crss
100
10
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
4
60
80 100 120 140 160
20
Coss = Cds + Cgd
1000
40
Fig 7. Normalized On-Resistance vs. Temperature
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
10000
20
TJ , Junction Temperature (°C)
Fig 6. Typical Transfer Characteristics
100000
0
VDS = 50V
VDS= 20V
16
12
8
4
0
0
20
40
60
QG Total Gate Charge (nC)
Fig 9. Typical Total Gate Charge vs
Gate-to-Source Voltage
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IRF6644
1000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
1000.0
100.0
TJ = 150°C
TJ = 25°C
TJ = -40°C
10.0
1.0
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100
100µsec
10
1msec
100msec
1
VGS = 0V
0.1
0.1
0.0
1.0
2.0
3.0
4.0
0.01
5.0
0.10
1.00
10.00
100.00 1000.00
VDS , Drain-toSource Voltage (V)
VSD , Source-to-Drain Voltage (V)
Fig 10. Typical Source-Drain Diode Forward Voltage
Fig11. Maximum Safe Operating Area
Typical VGS(th) Gate threshold Voltage (V)
12
10
ID , Drain Current (A)
10msec
TA = 25°C
Tj = 150°C
Single Pulse
8
6
4
2
0
5.0
ID = 1.0A
ID = 1.0mA
4.5
ID = 250µA
ID = 150µA
4.0
3.5
3.0
2.5
2.0
25
50
75
100
125
150
-50
-25
TA , Ambient Temperature (°C)
0
25
50
75
100
125
150
TJ , Junction Temperature ( °C )
Fig 13. Typical Threshold Voltage vs.
Junction Temperature
Fig 12. Maximum Drain Current vs. Ambient Temperature
EAS, Single Pulse Avalanche Energy (mJ)
1000
ID
2.8A
3.3A
BOTTOM 6.2A
TOP
800
600
400
200
0
25
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
Fig 14. Maximum Avalanche Energy Vs. Drain Current
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5
IRF6644
Current Regulator
Same Type as D.U.T.
Id
Vds
50KΩ
Vgs
.2µF
12V
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Qgs1 Qgs2
Current Sampling Resistors
Fig 15a. Gate Charge Test Circuit
Qgd
Qgodr
Fig 15b. Gate Charge Waveform
V(BR)DSS
15V
D.U.T
RG
VGS
20V
DRIVER
L
VDS
tp
+
V
- DD
IAS
A
I AS
0.01Ω
tp
Fig 16c. Unclamped Inductive Waveforms
Fig 16b. Unclamped Inductive Test Circuit
VDS
RD
VDS
90%
VGS
D.U.T.
RG
+
- VDD
10V
Pulse Width ≤ 1 µs
10%
VGS
td(on)
tr
td(off)
tf
Duty Factor ≤ 0.1 %
Fig 17a. Switching Time Test Circuit
6
Fig 17b. Switching Time Waveforms
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IRF6644
D.U.T
Driver Gate Drive
+
ƒ
+
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
di/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
D=
Period
P.W.
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
-
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 18. Diode Reverse Recovery Test Circuit for N-Channel
HEXFET® Power MOSFETs
DirectFET™ Substrate and PCB Layout, MN Outline
(Medium Size Can, N-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
6
3
1
1- Drain
2- Drain
3- Source
4- Source
5- Gate
6- Drain
7- Drain
5
7
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4
2
7
IRF6644
DirectFET™ Outline Dimension, MN Outline
(Medium Size Can, N-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
DIMENSIONS
NOTE: CONTROLLING
DIMENSIONS ARE IN MM
METRIC
MAX
CODE MIN
6.35
A
6.25
5.05
B
4.80
3.95
C
3.85
0.45
D
0.35
0.92
E
0.88
0.82
F
0.78
1.42
G
1.38
0.92
H
0.88
0.52
J
0.48
1.29
K
1.16
2.91
L
2.74
0.70
M
0.59
0.08
N
0.03
0.17
P
0.08
IMPERIAL
MIN
0.246
0.189
0.152
0.014
0.034
0.031
0.054
0.034
0.019
0.046
0.109
0.023
0.001
0.003
MAX
0.250
0.201
0.156
0.018
0.036
0.032
0.056
0.036
0.020
0.051
0.115
0.028
0.003
0.007
DirectFET™ Part Marking
8
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IRF6644
DirectFET™ Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6644). For 1000 parts on 7" reel,
order IRF6644TR1
REEL DIMENSIONS
TR1 OPTION (QTY 1000)
STANDARD OPTION (QTY 4800)
IMPERIAL
IMPERIAL
METRIC
METRIC
MIN
CODE
MIN
MAX
MAX
MIN
MIN
MAX
MAX
12.992
6.9
A
N.C
N.C
330.0
177.77 N.C
N.C
0.795
B
0.75
N.C
20.2
19.06
N.C
N.C
N.C
0.504
0.53
C
0.50
0.520
12.8
13.5
12.8
13.2
0.059
D
0.059
1.5
1.5
N.C
N.C
N.C
N.C
3.937
E
2.31
100.0
58.72
N.C
N.C
N.C
N.C
N.C
F
N.C
0.53
N.C
N.C
0.724
13.50
18.4
G
0.488
0.47
N.C
12.4
11.9
0.567
12.01
14.4
H
0.469
0.47
11.9
11.9
0.606
N.C
12.01
15.4
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
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