XC95144XL High Performance CPLD November 13, 1998 (Version 1.2) Preliminary Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can very substantially depending on the system frequency, design application, and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. • • • • • • Description The XC95144XL is a 3.3 V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 5 ns. See Figure 2 for architecture overview. November 13, 1998 (Version 1.2) For a general estimate of ICC, the following equation may be used: ICC (mA) = MCHP(0.5) + MCLP(0.3) + MC(0.0045 mA/MHz) f Where: MCHP = Macrocells in high-performance (default) mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in graphical form. 200 Typical ICC (mA) • 5 ns pin-to-pin logic delays System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins) Optimized for high-performance 3.3 V systems - Low power operation - 5 V tolerant I/O pins accept 5 V, 3.3 V, and 2.5 V signals - 3.3 V or 2.5 V output capability - Advanced 0.35 micron feature size CMOS FastFLASH™ technology Advanced system features - In-system programmable - Superior pin-locking and routability with FastCONNECT II™ switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with 3 global and one productterm clocks - Individual output enable per output pin with local inversion - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold ciruitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000 V Pin-compatible with 5 V-core XC95144 device in the 100-pin TQFP package 178 MHz e anc form r e hP Hig 104 MHz 150 100 Low P ow er 50 0 50 150 100 Clock Frequency (MHz) 200 X5898C Figure 1: Typical Icc vs. Frequency for XC95144XL 1 XC95144XL High Performance CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 54 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT II Switch Matrix I/O 54 18 Function Block 2 Macrocells 1 to 18 54 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 54 1 I/O/GSR I/O/GTS 18 4 54 18 Function Block 4 Macrocells 1 to 18 Function Block 8 Macrocells 1 to 18 X5922B Figure 2: XC95144XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 November 13, 1998 (Version 1.2) Absolute Maximum Ratings Symbol VCC Description Supply voltage relative to GND Value -0.5 to 4.0 Units V VIN Input voltage relative to GND (Note 1) -0.5 to 5.5 V VTS Voltage applied to 3-state output (Note 1) -0.5 to 5.5 V TSTG Storage temperature (ambient) -65 to +150 oC TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) TJ Junction temperature +260 o C +150 o C Note 1: Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to +7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol VCCINT VCCIO VIL VIH VO Parameter Supply voltage for internal logic Commercial TA = 0oC to 70oC and input buffers Industrial TA = -40oC to +85oC Supply voltage for output drivers for 3.3 V operation Supply voltage for output drivers for 2.5 V operation Low-level input voltage High-level input voltage Output voltage Min 3.0 3.0 3.0 2.3 0 2.0 0 Max 3.6 3.6 3.6 2.7 0.80 5.5 VCCIO Units V V V V V V V Quality and Reliability Characteristics Symbol tDR NPE VESD Parameter Data Retention Program/Erase Cycles (Endurance) Electrostatic Discharge (ESD) Min 20 10,000 2,000 Max - Units Years Cycles Volts DC Characteristics Over Recommended Operating Conditions Symbol VOH Parameter Output high voltage for 3.3 V outputs Output high voltage for 2.5 V outputs Test Conditions IOH = -4.0 mA IOH = -500 µA VOL IIL Output low voltage for 3.3 V outputs Output low voltage for 2.5 V outputs Input leakage current IIH I/O high-Z leakage current CIN I/O capacitance ICC Operating Supply Current (low power mode, active) IOL = 8.0 mA IOL = 500 µA VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz November 13, 1998 (Version 1.2) Min 2.4 90% VCCIO 45 Max Units V V 0.4 0.4 ± 10.0 V V µA ± 10.0 µA 10.0 pF ma 3 XC95144XL High Performance CPLD AC Characteristics Symbol Parameter tPD tSU tH tCO I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GSR to output valid P-term S/R to output valid GCK pulse width (High or Low) P-term clock pulse width (High or Low) fSYSTEM tPSU tPH tPCO tOE tOD tPOE tPOD tAO tPAO tWLH tPLH XC95144XL-5 Max1 Min1 5.0 3.7 0.0 3.5 178.6 1.7 2.0 5.5 4.0 4.0 7.0 7.0 10.0 10.5 2.8 5.0 Advance XC95144XL-7 XC95144XL-10 Min Max Min Max 7.5 10.0 4.8 6.5 0.0 0.0 4.5 5.8 125.0 100.0 1.6 2.1 3.2 4.4 7.7 10.2 5.0 7.0 5.0 7.0 9.5 11.0 9.5 11.0 12.0 14.5 12.6 15.3 4.0 4.5 6.5 7.0 Preliminary Units ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns Note 1:Please contact Xilinx for up-to-date information on advance specifications. VTEST R1 Output Type Device Output R2 CL VCCIO VTEST R1 R2 CL 3.3 V 3.3 V 320 Ω 360 Ω 35 pF 2.5 V 2.5 V 250 Ω 660 Ω 35 pF X5906A Figure 3: AC Load Circuit 4 November 13, 1998 (Version 1.2) Internal Timing Parameters Symbol Parameter Buffer Delays Input buffer delay tIN GCK buffer delay tGCK GSR buffer delay tGSR GTS buffer delay tGTS Output buffer delay tOUT Output buffer enable/disable delay tEN Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial Delays Combinatorial logic propagation delay tPDI Register setup time tSUI Register hold time tHI tECSU Register clock enable setup time tECHO Register clock enable hold time Register clock to output valid time tCOI Register async. S/R to output delay tAOI Register async. S/R recover before clock tRAI tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays FastCONNECT II™ feedback delay tF Time Adders Incremental product term allocator delay tPTA tSLEW Slew-rate limited delay XC95144XL-5 Max1 Min1 XC95144XL-7 Min Max Units 1.5 1.1 2.0 4.0 2.0 0.0 2.3 1.5 3.1 5.0 2.5 0.0 3.5 1.8 4.5 7.0 3.0 0.0 ns ns ns ns ns ns 1.6 1.0 5.5 2.4 1.4 7.2 2.7 1.8 7.5 ns ns ns 1.7 0.5 1.0 5.0 1.4 6.4 1.8 7.3 ns ns ns ns ns ns ns ns ns ns 1.9 3.5 4.2 ns 0.8 4.0 Preliminary 1.0 4.5 ns ns 2.3 1.4 2.3 1.4 1.3 2.6 2.2 2.6 2.2 0.4 6.0 5.0 3.0 3.5 3.0 3.5 0.5 6.4 7.5 0.7 3.0 Advance Note 1: Please contact Xilinx for up-to-date information on advance specifications. November 13, 1998 (Version 1.2) XC95144XL-10 Min Max 1.0 7.0 10.0 5 XC95144XL High Performance CPLD XC95144XL I/O Pins BScan Function Macrocell TQ100 TQ144 CS144 Order Block Notes BScan Function Macrocell TQ100 TQ144 CS144 Order Block 1 1 – 23 H3 429 3 1 – 39 M3 321 1 2 11 16 F1 426 3 2 23 32 L1 318 1 3 12 17 G2 423 3 3 – 41 K4 315 1 4 – 25 J1 420 3 4 – 44 N4 312 1 5 13 19 G3 417 3 5 24 33 L2 309 1 6 14 20 G4 414 3 6 25 34 L3 306 1 7 - - - 411 3 7 – 46 L5 303 1 8 15 21 H1 408 3 8 27 38 N2 300 1 9 16 22 H2 405 3 9 28 40 N3 297 1 10 – 31 K3 402 3 10 – 48 N5 294 1 11 17 24 H4 399 3 11 29 43 M4 291 1 12 18 26 J2 396 3 12 30 45 K5 288 1 13 – - - 393 3 13 – - - 285 1 14 19 27 J3 390 3 14 32 49 K6 282 1 15 20 28 J4 387 3 15 33 50 L6 279 1 16 – 35 M1 384 3 16 – - - 276 1 17 22 30 K2 381 3 17 34 51 M6 273 1 18 – – - 378 3 18 – – - 270 2 1 – 142 C3 375 4 1 – 118 C9 267 2 2 99 143 A2 372 4 2 87 126 A7 264 2 3 – - - 369 4 3 – 133 A5 261 2 4 – 4 C1 366 4 4 – - - 258 2 5 1 2 B1 363 [1] 4 5 89 128 D7 255 2 6 2 3 C2 360 [1] 4 6 90 129 A6 252 2 7 – - - 357 4 7 – - - 249 2 8 3 5 D4 354 [1] 4 8 91 130 B6 246 2 9 4 6 D3 351 [1] 4 9 92 131 C6 243 2 10 – 7 D2 348 4 10 – 135 C5 240 2 11 6 9 E4 345 4 11 93 132 D6 237 2 12 7 10 E3 342 4 12 94 134 B5 234 2 13 – 12 E1 339 4 13 – 137 A4 231 2 14 8 11 E2 336 4 14 95 136 D5 228 2 15 9 13 F4 333 4 15 96 138 B4 225 2 16 – 14 F3 330 4 16 – 139 C4 222 2 17 10 15 F2 327 4 17 97 140 A3 219 2 18 – – - 324 4 18 - - - 216 [1] [1] Notes [1] [1] Note 1: Global control pin. 6 November 13, 1998 (Version 1.2) XC95144XL (Continued) BScan Function Macrocell TQ100 TQ144 CS144 Order Block 5 1 - - - 5 2 35 52 5 3 – 59 5 4 – 5 5 5 6 5 Notes BScan Function Macrocell TQ100 TQ144 CS144 Order Block 213 7 1 – – - 105 N6 210 7 2 50 71 N12 102 L8 207 7 3 – 75 L12 99 - - 204 7 4 – - - 96 36 53 M7 201 7 5 52 74 M13 93 37 54 N7 198 7 6 53 76 L13 90 7 – 66 M10 195 7 7 – 77 K10 87 5 8 39 56 K7 192 7 8 54 78 K11 84 5 9 40 57 N8 189 7 9 55 80 K13 81 5 10 – 68 N11 186 7 10 – 79 K12 78 5 11 41 58 M8 183 7 11 56 82 J11 75 5 12 42 60 K8 180 7 12 58 85 H10 72 5 13 – 70 L11 177 7 13 – 81 J10 69 5 14 43 61 N9 174 7 14 59 86 H11 66 5 15 46 64 K9 171 7 15 60 87 H12 63 5 16 – - - 168 7 16 – 83 J12 60 5 17 49 69 M11 165 7 17 61 88 H13 57 5 18 – – - 162 7 18 – – - 54 6 1 – – - 159 8 1 – – - 51 6 2 74 106 C11 156 8 2 63 91 G11 48 6 3 – - - 153 8 3 – 95 F11 45 6 4 – 111 B11 150 8 4 – 97 E13 42 6 5 76 110 A12 147 8 5 64 92 G10 39 6 6 77 112 A11 144 8 6 65 93 F13 36 6 7 – - - 141 8 7 – - - 33 6 8 78 113 D10 138 8 8 66 94 F12 30 6 9 79 116 A10 135 8 9 67 96 F10 27 6 10 – 115 B10 132 8 10 – 101 D13 24 6 11 80 119 B9 129 8 11 68 98 E12 21 6 12 81 120 A9 126 8 12 70 100 E10 18 6 13 – - - 123 8 13 – 103 D11 15 6 14 82 121 D8 120 8 14 71 102 D12 12 6 15 85 124 A8 117 8 15 72 104 C13 9 6 16 – 117 D9 114 8 16 – 107 B13 6 6 17 86 125 B7 111 8 17 73 105 C12 3 6 18 – – - 108 8 18 – – - 0 November 13, 1998 (Version 1.2) Notes 7 XC95144XL High Performance CPLD XC95144XL Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 3.3 V VCCIO 2.5 V/3.3 V GND No Connects TQ100 TQ144 CS144 22 30 K2 23 32 L1 27 38 N2 3 5 D4 4 6 D3 1 2 B1 2 3 C2 99 143 A2 48 67 L10 45 63 L9 83 122 C8 47 65 N10 5, 57, 98 8, 42, 84, 141 B3, D1, J13, L4 26, 38, 51, 88 1, 37, 55, 73, 109, 127 A1, A13, C7, L7, N1, N13 21, 31, 44, 62, 69, 75, 84, 18, 29, 36, 47, 62, 72, 89, B2, B8, B12, C10, E11, 100 90, 99, 108, 114, 123, 144 G1, G12, G13, K1, M2, M5, M9, M12 – – Ordering Information Example: Device Type XC95144XL -7 TQ 100 C Temperature Range Number of Pins Speed Grade Package Type Speed Options Packaging Options -10 10 ns pin-to-pin delay -7 7.5 ns pin-to-pin delay -5 5 ns pin-to-pin delay TQ100 100-Pin Thin Quad Flat Pack (TQFP) TQ144 144-Pin Thin Quad Flat Pack (TQFP) CS144 144-Pin Chip Scale Package (CSP) Temperature Options C= Commercial TA = 0oC to +70oC I = Industrial TA = -40oC to +85oC 8 November 13, 1998 (Version 1.2) Component Availability Pins Type Code XC95144XL -10 -7 -5 100 Plastic TQFP TQ100 C, I C (C) 144 Plastic TQFP TQ144 C, I C (C) 144 Chip Scale Package CSP CS144 (C) - C = Commercial (TA = 0oC to +70oC) I = Industrial (TA = -40oC to +85oC) ( ) Parenthesis indicate future planned products. Please contact Xilinx for up-to-date availability information. Revision History Date 10/30/98 11/13/98 Revision Minor corrections in CS144 pinout table. V1.2 Minor correction in CS144 pinout table. November 13, 1998 (Version 1.2) 9