WED2ZL64512S White Electronic Designs 512K x 64 Synchronous Pipeline NBL SRAM FEATURES DESCRIPTION n Fast clock speed: 166, 150, 133, and 100MHz The WEDC SyncBurst - SRAM family employs high-speed, lowpower CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb Sync SRAM integrate two 512K x 32 SRAMs into a single BGA package to provide 512K x 64 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The NBL or No Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable are synchronized to input clock. Output Enable controls the outputs at any given time and to Asynchronous Input. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. n Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns n Fast OE access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns n Seperate +2.5V ± 5% power supplys for core I/O (VDD + VDDQ) n Double Word Write Control n Clock-controlled and registered addresses, data I/Os and control signals n Packaging: • 119-bump BGA package n Low capacitive bus loading NOTE: NBL = No Bus Latency is equivalent to the industry ZBT™ devices. FIG. 1 PIN CONFIGURATION (TOP A BLOCK DIAGRAM VIEW) 1 2 3 4 5 6 7 8 9 DQF DQF DQF DQF NC DQG DQG DQG DQG B DQF DQF DQF DQF NC DQG DQG DQG DQG C DQE DQE DQE DQE NC DQH DQH DQH DQH D DQE DQE DQE DQE NC DQH DQH DQH DQH E NC NC NC VDDQ VDDQ VDDQ NC NC NC F SA VDDQ VDD VDD VDD VDD VDD VDDQ SA G SA CE VSS VSS VSS VSS VSS SA SA H SA NC VSS WE1 VSS VSS VSS SA SA J SA18 CE2 SSCLK OE NC NC NC SA 1 SA0 K SA CE2 VSS WE0 VSS VSS VSS SA SA L SA NC VSS VSS VSS VSS VSS SA SA M SA VDDQ VDD VDD VDD VDD VDD VDDQ SA N NC NC NC VDDQ VDDQ VDDQ NC NC NC P DQD DQD DQD DQD NC DQA DQA DQA DQA R DQD DQD DQD DQD NC DQA DQA DQA DQA T DQC DQC DQC DQC NC DQB DQ B DQB DQB U DQC DQC DQC DQC NC DQB DQ B DQB DQB October 2001 Rev. 0 ECO #14597 SA 0 – 18 DQ 0 – 31 DQ 32 – 63 OEB WEB_LW CLK CS2B CS2 CS1B A0 – A18 OE WE CLK CS2 CS2 CS1 U1 DQ 0 – 31 512K x 36 A0 – A18 WEB_HW OE WE CLK CS2 CS2 CS1 U2 DQ 0 – 31 512K x 36 1 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com White Electronic Designs WED2ZL64512S FUNCTION DESCRIPTION The WED2ZL64512S is an NBL SSRAM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE) are synchronized to rising clock edges. rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. During read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. The pipe-lined NBL SSRAM uses a latelate write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle later. Output Enable (OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, the write enable input signals WE are driven high. The internal array is read between the first rising edge and the second S YNCHRONOUS T RUTH T ABLE TRUTH TABLES NOTES: CEx WE OE CLK Address Accessed Operation H X X á N/A Deselect L H L á Current Address Read Cycle L H H á N/A NOP/Dummy Read X X H á N/A Dummy Read L L X á Current Address Write Cycle L L X á N/A NOP/Write Abort 1. X means “Don’t Care.” 2. The rising edge of clock is symbolized by ( á ) 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 2 October 2001 Rev. 0 ECO #14597 WED2ZL64512S White Electronic Designs A BSOLUTE VOLTAGE ON VDD SUPPLY RELATIVE TO VSS VIN (DQX) VIN (INPUTS) STORAGE TEMPERATURE (BGA) SHORT CIRCUIT OUTPUT CURRENT M AXIMUM R ATINGS * -0.3V TO +3.6V -0.3V TO +3.6V -0.3V TO +3.6V -55°C TO +125°C 100mA *Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability. E L E C T R I C A L C H A R A C T E R I S T I C S (0°C DESCRIPTION INPUT HIGH (LOGIC 1) VOLTAGE INPUT LOW (LOGIC 0) VOLTAGE INPUT LEAKAGE CURRENT OUTPUT LEAKAGE CURRENT OUTPUT HIGH VOLTAGE OUTPUT LOW VOLTAGE SUPPLY VOLTAGE NOTES: S YMBOL VIH VIL ILI ILO VOH VOL VDD £ TA CONDITIONS MIN 1.7 -0.3 -5 -5 2.0 --2.375 0V - VIN - VDD OUTPUT(S) DISABLED, 0V - VIN - VDD IOH = -1.0mA IOL = 1.0mA MAX VDD +0.3 0.7 5 5 --0.4 2.625 UNITS V V µA µA V V V NOTES 1 1 1 1 1 1. All voltages referenced to Vss (GND) DC C H A R A C T E R I S T I C S DESCRIPTION POWER SUPPLY CURRENT: OPERATING POWER SUPPLY CURRENT: STANDBY CLOCK RUNNING STANDBY CURRENT NOTES: 70°C) £ SYMBOL IDD ISB2 ISB4 CONDITIONS TYP DEVICE SELECTED; ALL INPUTS £ VIL OR ³ VIH; CYCLE TIME = TCYC MIN; VDD = MAX; OUTPUT OPEN DEVICE DESELECTED; VDD = MAX; ALL INPUTS £ VSS + 0.2 OR VDD - 0.2; ALL INPUTS STATIC; CLK FREQUENCY = 0 DEVICE DESELECTED; VDD = MAX; ALL INPUTS £ VSS + 0.2 OR V DD - 0.2; C YCLE TIME = TCYC MIN 166 150 133 100 MHZ MHZ MHZ MHZ UNITS NOTES 650 600 560 500 mA 1, 2 60 60 60 60 mA 2 140 120 100 80 mA 2 30 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. 2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time. BGA C APACITANCE DESCRIPTION SYMBOL CONTROL INPUT CAPACITANCE INPUT/OUTPUT CAPACITANCE (DQ) ADDRESS CAPACITANCE CLOCK CAPACITANCE NOTES: CL CO CA CCK CONDITIONS TA = 25°C; f TA = 25°C; f TA = 25°C; f TA = 25°C; f = 1MHZ = 1MHZ = 1MHZ = 1MHZ TYP MAX UNITS NOTES 5 6 5 3 7 8 7 5 pF pF pF pF 1 1 1 1 1. This parameter is sampled. October 2001 Rev. 0 ECO #14597 3 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED2ZL64512S White Electronic Designs AC C HARACTERISTICS SYMBOL PARAMETER CLOCK TIME CLOCK ACCESS T IME OUTPUT ENABLE TO D ATA V ALID CLOCK H IGH TO O UTPUT L OW -Z OUTPUT H OLD FROM C LOCK H IGH OUTPUT E NABLE L OW TO OUTPUT L OW -Z OUTPUT E NABLE H IGH TO OUTPUT HIGH -Z CLOCK H IGH TO O UTPUT H IGH -Z CLOCK HIGH P ULSE W IDTH CLOCK LOW P ULSE W IDTH ADDRESS S ETUP TO C LOCK H IGH CKE SETUP TO C LOCK H IGH DATA S ETUP TO C LOCK HIGH WRITE SETUP TO C LOCK H IGH CHIP SELECT S ETUP TO CLOCK H IGH ADDRESS H OLD TO C LOCK HIGH CKE HOLD TO C LOCK H IGH DATA H OLD TO C LOCK H IGH WRITE H OLD TO C LOCK H IGH CHIP SELECT H OLD TO C LOCK H IGH t CYC t CD tOE t LZC t OH tLZOE tHZOE t HZC t CH tCL tAS t CES tDS t WS tCSS tAH t CEH tDH tWH tCSH 166MHZ MIN MAX 6.0 -3.5 -3.5 1.5 -1.5 -0.0 --3.0 -3.0 2.2 -2.2 -1.5 -1.5 -1.5 -1.5 -1.5 0.5 -0.5 -0.5 -0.5 -0.5 -- 150MHZ MIN MAX 6.7 -3.8 -3.8 1.5 -1.5 -0.0 --3.0 -3.0 2.5 -2.5 -1.5 -1.5 -1.5 -1.5 -1.5 0.5 -0.5 -0.5 -0.5 -0.5 -- 133MHZ MIN MAX 7.5 -4.2 -4.2 1.5 -1.5 -0.0 --3.5 -3.5 3.0 -3.0 -1.5 -1.5 -1.5 -1.5 -1.5 0.5 -0.5 -0.5 -0.5 -0.5 -- 100MHZ MIN MAX 10.0 -5.0 -5.0 1.5 -1.5 -0.0 --3.5 -3.5 3.0 -3.0 -1.5 -1.5 -1.5 -1.5 -1.5 0.5 -0.5 -0.5 -0.5 -0.5 -- UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CEx is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registered into the device. A Read cycle is defined by WE High. Both cases must meet setup and hold times. AC TEST CONDITIONS (TA = 0 TO 70°C, VDD = 2.5V ± 5%, UNLESS OTHERWISE SPECIFIED) Parameter Input Pulse Level Input Rise and Fall Time (Measured at 20% to 80%) Input and Output Timing Reference Levels Output Load O UTPUT L O A D (B) (FOR tLZC, tLZOE , tHZOE , AND tHZC ) O UTPUT L OAD (A) Dout RL=50 Zo=50 Value 0 to 2.5V 1.0V/ns 1.25V See Output Load (A) +2.5V VL=1.25V 30pF* 1667 Dout 1538 5pF* *Including Scope and Jig Capacitance White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 4 October 2001 Rev. 0 ECO #14597 White Electronic Designs FIG. 3 WED2ZL64512S TIMING WAVEFORM OF READ CYCLE tCH tCL Clock tAS tAH A1 Address A2 tWS tWH tCSS tCSH WE0B WE1B CEx OEB tOE tHZOE tLZOE Q1-1 Data Out NOTES: tCD tOH Q2-1 WRITE = L means WE = L, and BWx = L CEx refers to the combination of CE1, CE2 and CE2. Don't Care Undefined October 2001 Rev. 0 ECO #14597 5 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com White Electronic Designs FIG. 4 WED2ZL64512S TIMING WAVEFORM OF WRITE CYCLE tCH tCL Clock Address A2 A1 WE0B WE1B CEx OEB Data In D1-1 D2-1 tHZOE Data Out Q0-3 NOTES: Q0-4 WRITE = L means WE = L, and BWx = L CEx refers to the combination of CE1, CE2 and CE2. Don't Care Undefined White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 6 October 2001 Rev. 0 ECO #14597 WED2ZL64512S White Electronic Designs FIG. 5 TIMING WAVEFORM OF SINGLE READ/WRITE tCH tCL Clock Address A1 A2 A3 A4 Q1 Q3 A5 A6 A8 A7 A9 WE0B WE1B CEx OEB tOE tLZOE Data Out Q6 Q7 tDH tDS Data In Q4 D2 D5 Don't Care NOTES: October 2001 Rev. 0 ECO #14597 WRITE = L means WE = L, and BWx = L CEx refers to the combination of CE1, CE2 and CE2. Undefined 7 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com WED2ZL64512S White Electronic Designs FIG. 7 TIMING WAVEFORM OF CE OPERATION tCH tCL Clock tCYC Address A1 A2 A3 A4 A5 WE0B WE1B CEx OEB tHZC tOE tLZOE Data Out Q1 tCD tLZC Q2 Q4 tDS tDH Data In D3 NOTES: Don't Care WRITE = L means WE = L, and BWx = L CEx refers to the combination of CE1, CE2 and CE2. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com D5 Undefined 8 October 2001 Rev. 0 ECO #14597 WED2ZL64512S White Electronic Designs PACKAGE DIMENSION: 119 BUMP PBGA 1.90 (0.075) MAX 7.62 (0.300) TYP 17.00 (0.669) TYP A A1 CORNER B C D E F 1.27 (0.050) TYP G H 20.32 (0.800) TYP 23.00 (0.905) TYP J K L M N P R T U 0.711 (0.028) MAX 1.27 (0.050) TYP ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined. ORDERING INFORMATION C OMMERCIAL T EMP R ANGE (0°C TO 70°C) Part Number Configuration tCD Clock (ns) (MHz) WED2ZL64512S35BC512K x 64 3.5 166 WED2ZL64512S38BC512K x 64 3.8 150 WED2ZL64512S42BC512K x 64 4.2 133 WED2ZL64512S50BC512K x 64 5.0 100 October 2001 Rev. 0 ECO #14597 9 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com