WEDPY256K72V-XBX 256Kx72 Synchronous Pipeline SRAM Preliminary* FEATURES DESCRIPTION ! Fast clock speed: 100, 133, 150, 166 and 200** MHz The WEDPY256K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate two 256K x 36 SRAMs into a single PBGA package to provide 256K x 72 configuration. All synchronous inputs are controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, and active LOW chip selects (CS). Asynchronous inputs include the output enable (OE1/OE2), clock (CLK). ! Fast access time: 5.0, 4.0, 3.8, 3.5, 3.1ns ! +3.3V power supply (VDD) ! +2.5V output buffer supply (VDDQ) ! Single-cycle deselect ! Common data inputs and data outputs ! Clock-controlled and registered addresses, data I/Os and control signals * This data sheet describes a product that is not fully qualified or characterized and is subject to change without notice. ! SNOOZE MODE for reduced-power standby ! Individual BYTE WRITE control and GLOBAL WRITE ! Six chip enables for simple depth expansion and address pipeline FIG. 1 ! Internally self-timed WRITE cycle SA0-17 ADSC ADSP ADV BWa BWb BWc BWd BWE CS11 CS21 CS21 CLK GW MODE OE1 ZZ ! Burst control (interleaved or linear burst) ! Packaging: ! 159-bump PBGA package, 14mm x 22mm ! Commercial, industrial, and military temperature ranges ! User configurable as 512K x 36, or 1M x 18 ! Upgradable to 512K x 72 SSRAM (contact factory for information) **200 MHz for commercial and industrial temperature only. BLOCK DIAGRAM 256Kx36 A0-17 SSRAM ADSC ADSP ADV BWa BWb BWc BWd WE DQ0-35 CS1 CS2 CS2 CLK GW MODE OE ZZ IC1 DQ0-35 256Kx36 BWe BWf BWg BWh CS11 CS22 CS22 OE2 November 2003 Rev. 6 1 A0-17 SSRAM ADSC ADSP ADV BWa BWb BWc BWd WE CS1 CS2 CS2 CLK GW MODE OE ZZ IC2 DQ36-71 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPY256K72V-XBX PIN CONFIGURATION (TOP V IEW) 1 2 3 4 5 6 7 8 9 A — DQ16 DQ14 DQ12 B ADV DQ17 DQ15 DQ11 C OE1 ADSP GW D CS21 CLK 10 DQ10 ZZ DQ6 DQ4 DQØ DQ8 DQ9 DQ7 DQ5 DQ3 DQ1 SA13 DQ13 DNU GND DQ29 DQ2 SA12 SA10 BWa GND GND VDD VDDQ SA11 SA9 SA6 E BW C BWb BWd GND VDD GND GND SA8 SA7 SAØ F CS21 DQ18 DQ22 VDD VDDQ GND VDD DQ30 DQ34 SA1 G CS11 DQ19 DQ23 GND VDD VDDQ GND DQ31 DQ33 SA5 H DQ26 DQ20 DQ24 VDDQ VDDQ VDD VDD DQ28 DQ32 DQ35 J SA17 DQ21 DQ25 VDD VDD VDDQ VDDQ DQ27 DQ39 DQ37 K SA16 DQ52 DQ49 GND VDDQ VDD GND DQ40 DQ38 DQ36 L SA14 DQ51 DQ50 VDD GND VDDQ VDD DQ42 DQ41 DQ44 M SA15 DQ53 DQ48 GND GND VDD GND DQ43 SA3 DNU N OE2 ADSC DQ47 VDDQ VDD GND GND MODE SA2 SA4 P BWE CS22 DQ46 DQ45 GND DNU DQ59 DQ64 DQ66 DQ70 R BWh BWg BWf BWe DQ56 DQ60 DQ61 DQ65 DQ69 DQ71 T CS12 CS22 DQ62 DQ54 DQ55 DQ57 DQ58 DQ63 DQ67 DQ68 DNU = DO NOT USE. Reserved for future upgrades. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 2 WEDPY256K72V-XBX INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS (X36) Function READ READ WRITE Byte "a" WRITE All Bytes WRITE All Bytes GW H H H H L BWE H L L L X BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X NOTE: 1. Using BWE and BWa through BWd, any one or more bytes may be written. 2. Insert BWe through BWh for DQ36-71 control. 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPY256K72V-XBX TRUTH TABLE Operation Address Used CS1 CS2 CS2 ZZ Deselected Cycle, Power-Down None H X Deselected Cycle, Power-Down None L Deselected Cycle, Power-Down None L Deselected Cycle, Power-Down None L ADSP ADSC ADV WRITE OE CLK DQ X L X L X X X L-H HIGH Z X L L L X X X X L-H HIGH Z H X L L X X X X L-H HIGH Z X L L H L X X X L-H HIGH Z Deselected Cycle, Power-Down None L H X L H L X X X L-H HIGH Z SNOOZE MODE, Power-Down None X X X H X X X X X X HIGH Z READ Cycle, Begin Burst External L L H L L X X X L L-H Q READ Cycle, Begin Burst WRITE Cycle, Begin Burst External External L L L L H H L L L H X L X X X L H X L-H L-H HIGH Z D READ Cycle, Begin Burst External L L H L H L X H L L-H Q READ Cycle, Begin Burst External L L H L H L X H H L-H HIGH Z READ Cycle, Continue Burst Next X X X L H H L H L L-H Q READ Cycle, Continue Burst Next X X X L H H L H H L-H HIGH Z READ Cycle, Continue Burst Next H X X L X H L H L L-H Q READ Cycle, Continue Burst Next H X X L X H L H H L-H HIGH Z WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q READ Cycle, Suspend Burst Current X X X L H H H H H L-H HIGH Z READ Cycle, Suspend Burst Current H X X L X H H H L H Q READ Cycle, Suspend Burst Current H X X L X H H H H L-H HIGH Z WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D NOTE: 1. X means "Don't Care." means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc, or WE) are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW High. 3. BWa enables WRITEs to DQ0-8. BWb enables WRITEs to DQ9-17. BWc enables WRITEs to DQ18-26. BWd enables WRITE to DQ27-35. 4. All inputs excepts OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending bursts. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be held in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 4 WEDPY256K72V-XBX ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply relative to VSS -0.5V to +4.6V Voltage on V DDQ Supply relative to V SS -0.5V to +4.6V VIN (DQx) -0.5V to VDDQ +0.5V VIN (Inputs) -0.5V to V DD +0.5V Storage Temperature (BGA) -55°C to +150°C Short Circuit Output Current 100 mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS -55°C ≤ TA ≤ +125°C Description Input High (Logic 1)Voltage Symbol Conditions Min Max Units VIH Inputs 1.7 VDD +0.3 V Notes 1 VIHQ Data (DQ) 1.7 VDDQ +0.3 V 1 Input Low (Logic 0) Voltage VIL -0.3 0.7 V 1 Input Leakage Current ILI 0V ≤ VIN ≤ VDD -2.0 2.0 µA 2 Ouptut Leakage Current I LO Outputs disabled, 0V ≤ VIN ≤ VDDQ (DQX) -1.0 1.0 µA Output High Voltage VOH IOH = -1.0mA 2.0 — V 1 Output Low Voltage VOL IOL = 1.0mA — 0.4 V 1 Supply Voltage VDD 3.135 3.6 V 1 Output Buffer Supply VDDQ 2.375 2.9 V 1 NOTES: 1. All voltages referenced to Vss (GND). DC CHARACTERISTICS -55°C ≤ TA ≤ +125°C Description Conditions 100 MHz Power Supply Current: Operating IDD Device selected; All inputs ≤ VIL or ≥ VIH; Cycle time ≥ tKC MIN; VDD = MAX; Outputs open CMOS Standby ISB2 Device deselected; VDD = MAX; All inputs ≤ Vss + 0.2 Clock Running ISB4 Device deselected; VDD = MAX; All inputs ≤ Vss + 0.2 or ≥ VDD -0.2; Cycle time ≥ tKC MIN; ADSC, ADSP, GW, BWx, ADV, ≥ VIH 133 MHz 150 MHz 160 MHz 200 MHz Units Notes 600 750 950 950 1050 mA 1.2 20 20 20 20 20 mA 2 170 180 220 220 240 mA 2 NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. 2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down mode). BGA CAPACITANCE (TA = +25°C, F = 1MHZ) Description BGA THERMAL RESISTANCE Symbol Max Units Notes CI 6 pF 1 Description Junction to Ambient Common Control Input Capacitance (2) CIC 15 pF 1 (No Airflow) Input/Output Capacitance (DQ) CO 10 pF 1 Junction to Ball Theta JB 17.3 0 C/W 1 Address Capacitance (SA) Cs A 15 pF 1 Junction to Case (Top) Theta JC 0 C/W 1 Clock Capacitance (CLK) CCK 12 pF 1 Control Input Capacitance Symbol Max Units Theta JA 30.5 0C/W 9.8 Notes 1 NOTE 1: Refer to BGA Thermal Resistance Correlation application note at www.whiteedc.com in the application notes section for modeling conditions. NOTES: 1. This parameter is guaranteed by design but not tested. 2. Common Inputs = zz, ADV, ADSP, GW, ADSC, MODE, BWE 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPY256K72V-XBX AC CHARACTERISTICS -55°C ≤ TA ≤ +125°C Symbol Parameter Min. 100MHz Max 133MHz Min Max 150MHz Min Max 166MHz Min Max 200MHz* Min Max 7.5 7.0 6.0 5.0 Units Clock Clock Cycle Time tkc Clock Frequency tkf 10 Clock HIGH Time (6) tkh 3.0 2.5 2.5 2.3 2.0 ns Clock LOW Time (6) tkl 3.0 2.5 2.5 2.3 2.0 ns 100 133 150 166 ns 200 MHz Output Times Clock to output valid tkq Clock to output invalid (2) tkqx 1.5 1.5 1.5 15 1.0 ns Clock to output on Low-Z (2,3,4) tkqlz 1.5 0 0 0 0 ns Clock to output in High-Z (2,3,4) tkqhz 5.0 4.2 4.0 3.5 3.1 ns OE to output valid (5) toeq 5.0 4.2 4.0 3.5 3.1 ns OE to output in Low-Z (2,3,4) toelz OE to output in High Z (2,3,4) toehz 5.0 0 4.0 0 3.8 3.5 0 4.5 4.2 0 3.1 ns 0 4.0 3.5 ns 3.0 ns Setup Time Address (6,7) tas 2.0 1.5 1.5 1.5 1.5 ns Write Enable (WE) (7) tws 2.0 1.5 1.5 1.5 1.5 ns Address status, (ADSC, ADSP) (7) tadss 2.0 1.5 1.5 1.5 1.5 ns Address advance (ADV) (7) Data-in (6,7) taas tds 2.0 2.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns Chip enable (CE) (7) tces 2.0 1.5 1.5 1.5 1.5 ns ns Hold Times Address (7) (7) tah 0.5 0.5 0.5 0.5 0.5 Address status (ADSC, ADSP) (7) tadsh 0.5 0.5 0.5 0.5 0.5 ns Address advance (ADV) (7) taah 0.5 0.5 0.5 0.5 0.5 ns Write Enable (WE) (7) Data-in (6,7) twh tdh 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns Chip Enable (CS) (7) tceh 0.5 0.5 0.5 0.5 0.5 ns * Commercial and industrial temperatures only. NOTES: 1. Test conditions as specified with the output loading as shown in test conditions unless otherwise noted. 2. This parameter is measured with output load as shown in test conditions. 3. This parameter is not tested. 4. Transition is measured ±500mV from steady state voltage. 5. OE is a “Don’t Care” when a byte write enable is sampled LOW. 6. Measured at HIGH above VIH and LOW below VIL 7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK to remain enabled. OUTPUT LOADS AC TEST CONDITIONS Parameter 2.5V I/O Input Pulse Levels Vss to 2.5 V 1 ns Input Rise and Fall Times Input Timing Reference Levels 1.25 V Output Timing Reference Levels 1.25 V Output Load AC Output Load Equivalent White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 6 Unit See figures, at left WEDPY256K72V-XBX SNOOZE MODE ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tzz is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and a ignored. SNOOZE MODE ELECTRICAL CHARACTERISTICS Description Conditions Symbol Current during SNOOZE MODE ZZ ≥ V IH Min Max Units mA I SB2Z 20 ZZ active to input ignored tZZ 2 (tKC) ZZ inactive to input sampled tRZZ ZZ active to snooze current tZZI ZZ inactive to exit snooze current tRZZI 2(tKC) 2 (tKC) 0 Notes ns 1 ns 1 ns 1 ns 1 NOTES: 1. This parameter is sampled. SNOOZE MODE WAVEFORM CLOCK t ZZ t RZZ ZZ t ZZI ISUPPLY ALL INPUTS (except ZZ) t RZZI I ISB2Z DESELECT or READ Only Deselect or Read Only Normal Operation Cycle Output (Q) HIGH-Z DON'T CARE 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPY256K72V-XBX FIG. 2: READ TIMING3 NOTES: 1. DQ (A2) refers to output from address A2. DQ (A2+ 1) refers to output from the next internal burst address following A2. 2. CS2 and CS2 have timing identical to CS1. On this diagram. When CS1 is LOW, CS2 is LOW and CS2 is HIGH. When CS1 is HIGH, CS2 is HIGH and CS2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge. 4. Outputs are disabled within two clock cycles after deselect. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 8 WEDPY256K72V-XBX FIG. 3: WRITE TIMING NOTES: 1. D(A2) refers to input for address A2. D(A2 +1) refers to input for the next internal burst address following A2. 2. CS2 and CS2 have timing identical to CS1. On this diagram, when CS1 is LOW, CS2 is LOW and CS2 is HIGH. When CS1 is HIGH, CS2 is HIGH and CS2 is LOW. 3. OE msut be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contentinon for th etime period prior to the byte write enable inputs being sampled. 4. ADV must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW LOW; or GW HIGH, BWE LOW and BWa-BWd LOW. 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPY256K72V-XBX FIG. 5: READ/WRITE TIMING3 NOTES: 1. Q(A4) refers to output from addrss A4. Q(A4 + 1) refers to output from the next internal burst address to following A4. 2. CS2 and CS2 have timing identical to CS1. On this diagram, when CS1 is LOW, CS2 is LOW and CS2 is HIGH. When CS1 is HIGH, CS2 is HIGH and CS2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP, ADSC, or ADV cycle is performed. 4. GW is HIGH. 5. Back-to back READs may be controlled by either ADSP or ADSC. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 10 WEDPY256K72V-XBX PACKAGE DIMENSION: 159 BUMP PBGA BOTTOM VIEW 22.1 (0.870) MAX 19.05 (0.750) NOM 1.27 (0.050) NOM 159x ∅ 0.762 (0.030) NOM 0.61 (0.024) NOM 1.27 (0.050) NOM 11.43 (0.450) NOM 2.03 (0.080) MAX 14.1 (0.555) MAX ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION WED P Y 256K72 V - X B X DEVICE GRADE: M = Military -55°C to +125°C I = Industrial -40°C to +85°C C = Commercial 0°C to +70°C PACKAGE: B = 159 Plastic Ball Grid Array (PBGA) FREQUENCY (MHz) 100 = 100MHz 133 = 133MHz 150 = 150MHz 166 = 166MHz 200 = 200MHZ 3.3V Power Supply CONFIGURATION, 256k x 72 SSRAM, Pipeline Burst PLASTIC WHITE ELECTRONIC DESIGNS CORP. 11 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WEDPY256K72V-XBX Document Title 256K x 72 Synchronous SRAM Revision History Rev # History Release Date Status Rev 0 Initial Release July 2001 Advanced Rev 1 Changes (Pg. 1, 5) 1.1 Add speed grades (100MHz-200MHz) to DC Characteristics Table Rev 2 Change (Pg. 1) January 2002 1.1 Change product status from Advanced to Preliminary. Preliminary Rev 3 Change (Pg. 1, 11) September 2002 1.1 Change Package Dimension title from Top View to Bottom View Preliminary Rev 4 Changes (Pg. 1, 5) November 2002 Preliminary 1.1 BGA Capacitance: Change CI from 10pF to 6pF 1.2 Change CIP to CIC, capacitance from 20pF to 15pF 1.3 Change CCK from 20pF to 12pF 1.4 Change CO from 12pF to 10pF 1.5 Change CSA from 20pF to 15pF 1.6 Add Note 2: Control Inputs = zz, ADV#, ADSP#, GW#, ADSC#, MODE#, BWE#. Rev 5 Changes (Pg. 1, 5, 7, 12) 1.1 Add Thermal Resistance Table 1.2 Correct formatting on page 7 May 2003 Preliminary Rev 6 Changes (Pg. 1, 11, 12) 1.1 Change mechanical drawing to new style November 2003 Preliminary White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 12