ETC WED2ZL362MSJ

WED2ZL362MSJ
White Electronic Designs
72Mb, 2M x 36 Synchronous Pipeline Burst NBL SRAM
Advanced
FEATURES
DESCRIPTION
n
n
n
n
n
n
n
The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDC’s 72Mb
SyncBurst SRAMs integrate two 2M x 18 SRAMs into a
single BGA package to provide a 2M x 36 configuration.
All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input
(CLK). The NBL or No Bus Latency Memory utilizes all
the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except
output enable and linear burst order are synchronized
to input clock. Burst order control must be tied “High or
Low.” Asynchronous inputs include the sleep mode enable (ZZ) and Output Enable (OE). Write cycles are internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip
write pulse generation and provides increased timing
flexibility for incoming signals.
Fast clock speed: 225, 200, 166 and 150MHz
Fast access times: 2.8, 3.0, 3.5 and 3.8ns
Fast OE access times: 2.8, 3.0, 3.5 and 3.8ns
Separate Core and I/O Power Supply
Snooze Mode for reduced-standby power
Individual Byte Write control
Clock-controlled and registered addresses, data I/Os
and control signals
n Burst control (interleaved or linear burst)
n Packaging:
• 119-bump BGA package, JEDEC Pin Definition
n Low capacitive bus loading
FIG. 1 PIN CONFIGURATION
(TOP VIEW)
July 2002 Rev 0
ECO # 15239
2
SA
CE 2
SA
DQP C
DQ C
DQ C
DQ C
DQ C
VDD
DQ D
DQ D
DQ D
DQ D
DQP D
SA
SA
RFU
3
SA
SA
SA
V SS
V SS
V SS
BW C
V SS
NC
V SS
BW D
V SS
V SS
V SS
LBO
SA
RFU
4
SA
ADV
VDD
NC
CE 1
OE
SA
WE
VDD
CLK
NC
CKE
SA 1
SA 0
VDD
SA
RFU
5
SA
SA
SA
V SS
V SS
V SS
BW B
V SS
NC
V SS
BW A
V SS
V SS
V SS
NC
SA
RFU
6
SA
CE 2
SA
DQP B
DQ B
DQ B
DQ B
DQ B
VDD
DQ A
DQ A
DQ A
DQ A
DQP A
SA
SA
NC
7
V DDQ
NC
NC
DQ B
DQ B
V DDQ
DQ B
DQ B
V DDQ
DQ A
DQ A
V DDQ
DQ A
DQ A
NC
ZZ
V DDQ
BWA
BWB
1
V DDQ
NC
NC
DQ C
DQ C
V DDQ
DQ C
DQ C
V DDQ
DQ D
DQ D
V DDQ
DQ D
DQ D
NC
NC
V DDQ
BWC
BWD
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
BLOCK DIAGRAM
2M x 18
CLK
CKE
ADV
LBO
CE1
CE2
CE2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
2M x 18
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
Address Bus
(SA0 ñ SA20)
DQC, DQD
DQPC, DQPD
DQA, DQB
DQPA, DQPB
DQA ñ DQD
DQPA ñ DQPD
1
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WED2ZL362MSJ
FUNCTION DESCRIPTION
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write
operation. The pipe-lined NBL SSRAM uses a late-late
write cycle to utilize 100% of the bandwidth. At the first
rising edge of the clock, WE and address are registered,
and the data associated with that address is required two
cycle later.
The WED2ZL362MSJ is an NBL SSRAM designed to
sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or vice
versa. All inputs (with the exception of OE, LBO and ZZ)
are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV
should be driven to Low once the device has been deselected in order to load a new address for next operation.
Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of
the burst seguence is provided by the external address.
The burst address counter wraps around to its initial state
upon completion. The burst sequence is determined by
the state of the LBO pin. When this pin is low, linear burst
sequence is selected. And when this pin is high, Interleaved burst sequence is selected.
Clock Enable (CKE) pin allows the operation of the chip
to be suspended as long as necessary. When CKE is
high, all synchronous inputs are ignored and the internal
device registers will hold their previous values. NBL
SSRAM latches external address and initiates a cycle
when CKE and ADV are driven low at the rising edge of
the clock.
During normal operation, ZZ must be driven low. When
ZZ is driven high, the SRAM will enter a Power Sleep
Mode after 2 cycles. At this time, internal state of the
SRAM is preserved. When ZZ returns to low, the SRAM
operates after 2 cycles of wake up time.
Output Enable (OE) can be used to disable the output at
any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the
address inputs are latched in the address register, CKE
is driven low, the write enable input signals WE are driven
high, and ADV driven low. The internal array is read between the first rising edge and the second rising edge of
the clock and the data is latched in the output register. At
the second clock edge the data is driven out of the SRAM.
During read operation OE must be driven low for the
device to drive out the requested data.
BURST SEQUENCE TABLE
LBO Pin High
First Address
Fourth Address
Case 1
A1
A0
0
0
0
1
1
0
1
1
(Interleaved Burst, LBO = High)
Case 2
Case 3
Case 4
A1
A0
A1
A0
A1
A0
0
1
1
0
1
1
0
0
1
1
1
0
1
1
0
0
0
1
1
0
0
1
0
0
LBO Pin High
First Address
Fourth Address
NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed.
White Electronic Designs Corporation • Westborough, MA • (508) 366-5151
2
Case 1
A1
A0
0
0
0
1
1
0
1
1
(Linear Burst, LBO = Low)
Case 2
Case 3
Case 4
A1
A0
A1
A0
A1
A0
0
1
1
0
1
1
1
0
1
1
0
0
1
1
0
0
0
1
0
0
0
1
1
0
WED2ZL362MSJ
White Electronic Designs
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CEx
H
X
L
X
L
X
L
X
L
X
X
ADV
L
H
L
H
L
H
L
H
L
H
X
WE
X
X
H
X
H
X
L
X
L
X
X
BWx
X
X
X
X
X
X
L
L
H
H
X
OE
X
X
L
L
H
H
X
X
X
X
X
CKE
L
L
L
L
L
L
L
L
L
L
H
CLK
­
­
­
­
­
­
­
­
­
­
­
Address Accessed
N/A
N/A
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
Next Address
Current Address
Operation
Deselect
Continue Deselect
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
Ignore Clock
NOTES:
1. X means “Don’t Care.”
2. The rising edge of clock is symbolized by (­ )
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins (ZZ and OE).
6. CEx refers to the combination of CE1, CE2 and CE2.
WRITE TRUTH TABLE
WE
H
L
L
L
L
L
L
BWa
X
L
H
H
H
L
H
BWb
X
H
L
H
H
L
H
BWc
X
H
H
L
H
L
H
BWd
X
H
H
H
L
L
H
Operation
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write Abort/NOP
NOTES:
1. X means “Don’t Care.”
2. All inputs in this table must meet setup and hold time around the rising edge of
CLK (­ ).
3
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WED2ZL362MSJ
White Electronic Designs
A BSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS
VIN (DQx)
VIN (Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
-0.3V to +3.6V
-0.3V to +3.6V
-0.3V to +3.6V
-55°C to +125°C
100mA
*Stress greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating condtions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Symbol
VIH
VIL
ILI
ILO
VOH
VOL
VDD
Conditions
Min
1.7
-0.3
-5
-5
2.0
—
2.375
0V £ VIN £ VDD
Output(s) Disabled, 0V £ VIN £ VDD
I OH = -1.0mA
I OL = 1.0mA
Max
VDD +0.3
0.7
5
5
—
0.4
2.625
Units
V
V
µA
µA
V
V
V
Notes
1
1
2
1
1
1
NOTES:
1. All voltages referenced to VSS (GND)
2. ZZ pin has an internal pull-up, and input leakage is higher.
DC CHARACTERISTICS
Description
Power Supply
Current: Operating
Power Supply
Current: Standby
Symbol
I DD
I SB 2
Power Supply
Current: Current
ISB3
Clock Running
Standby Current
ISB4
Conditions
Device Selected; All Inputs £ VIL or ³ VIH; Cycle
Time = tCYC MIN; VDD = MAX; Output Open
Device Deselected; VDD = MAX; All Inputs £ VSS + 0.2
or VDD - 0.2; All Inputs Static; CLK Frequency = 0;
ZZ £ VIL
Device Selected; All Inputs £ VIL or ³ VIH; Cycle
Time = tCYC MIN; VDD = MAX; Output Open;
ZZ ³ VDD - 0.2V
Device Deselected; VDD = MAX; All Inputs
£ VSS + 0.2 or VDD - 0.2; Cycle Time = t CYC
MIN; ZZ £ VIL
Typ
225
MHz
800
200
MHz
740
166
MHz
690
150
MHz
640
Units
mA
Notes
1, 2
30
60
60
60
60
mA
3
20
40
40
40
40
mA
2
160
148
135
125
mA
2
NOTES:
1. IDD is specified with no output current and increases with faster cycle times.
2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time.
3. Typical values are measured at 2.5V, 25°C.
BGA CAPACITANCE
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
Symbol
CI
CO
CA
CCK
Conditions
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
NOTES:
1. This parameter is sampled.
White Electronic Designs Corporation • Westborough, MA • (508) 366-5151
4
Typ
5
6
5
3
Max
7
8
7
5
Units
pF
pF
pF
pF
Notes
1
1
1
1
WED2ZL362MSJ
White Electronic Designs
AC CHARACTERISTICS
Symbol
Parameter
Clock Time
Clock Access Time
Output enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
Address Advance to Clock High
Chip Select Setup to Clock High
Address Hold to Clock high
CKE Hold to Clock High
Data Hold to Clock High
Write Hold to Clock High
Address Advance to Clock High
Chip Select Hold to Clock High
tCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
tCH
tCL
tAS
tCES
tDS
tWS
tADVS
tCSS
tAH
tCEH
tDH
tWH
tADVH
tCSH
225MHz
Min
Max
4.4
—
2.8
—
2.8
1.5
—
1.5
—
0.0
—
—
2.5
—
2.5
1.8
—
1.8
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
1.5
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
200MHz
Min
Max
5.0
—
3.0
—
3.0
1.5
—
1.5
—
0.0
—
—
2.5
—
2.5
2.0
—
2.0
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
1.5
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
166MHz
Min
Max
6.0
—
3.5
—
3.5
1.5
—
1.5
—
0.0
—
—
3.0
—
3.0
2.2
—
2.2
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
1.5
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
150MHz
Min
Max
6.7
—
3.8
—
3.8
1.5
—
1.5
—
0.0
—
—
3.0
—
3.0
2.5
—
2.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
1.5
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CEx is
sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.
3. A WRITE cycle is defined by WE low having been registered into the device at ADV Low.
A READ cycle is defined by WE High with ADV Low. Both cases must meet setup and hold times.
AC TEST CONDITIONS
(VDD = 2.5V ± 5%, UNLESS OTHERWISE SPECIFIED)
Parameter
Input Pulse Level
Input Rise and Fall Time (Measured at 20% to 80%)
Input and Output Timing Reference Levels
Output Load
OUTPUT LOAD (A)
Value
0 to 2.5V
1.0V/ns
1.25V
See Output Load (A)
OUTPUT LOAD (B)
(FOR tLZC, tLZOE, tHZOE, AND tHZC)
+2.5V
Dout
RL=50Ω
Zo=50Ω
1667Ω
Dout
VL=1.25V
30pF*
1538Ω
5pF*
*Including Scope and Jig Capacitance
5
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WED2ZL362MSJ
White Electronic Designs
SNOOZE MODE
When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE
is not guaranteed to complete successfully. Therefore,
SNOOZE MODE must not be initiated until valid pending operations are completed.
SNOOZE MODE is a low-current, “power-down” mode in
which the device is deselected and current is reduced to
ISB2Z. The duration of SNOOZE MODE is dictated by the
length of time Z is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated
inputs and are ignored. ZZ is an asynchronous, active
HIGH input that causes the device to enter SNOOZE
MODE.
SNOOZE MODE
Description
Current during SNOOZE MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
Conditions
ZZ ³ VIH
Symbol
I SB2Z
tZZ
tRZZ
tZZI
tRZZI
Min
Max
10
2(tKC)
Units
mA
ns
ns
ns
ns
2(tKC)
2(tKC)
FIG. 2 SNOOZE MODE TIMING DIAGRAM
CLOCK
t ZZ
t RZZ
ZZ
t ZZI
ISUPPLY
t RZZI
I ISB2Z
ALL INPUTS
(except ZZ)
Output (Q)
DESELECT or READ Only
HIGH-Z
DON'T CARE
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Notes
1
1
1
1
WED2ZL362MSJ
White Electronic Designs
FIG. 3 TIMING WAVEFORM OF READ CYCLE
tCH
tCL
Clock
tCYC
tCES
tCEH
CKE
tAS
tAH
A1
Address
A2
tWS
tWH
tCSS
tCSH
tADVS
tADVH
A3
WRITE
CEx
ADV
OE
tOE
tHZOE
tLZOE
Data Out
Q1-1
tCD
tOH
Q2-1
tHZC
Q2-2
Q2-3
Q2-4
Q3-1
Q3-2
Q3-3
Q3-4
Don't Care
NOTES: WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
Undefined
7
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WED2ZL362MSJ
White Electronic Designs
FIG. 4 TIMING WAVEFORM OF WRITE CYCLE
tCH
tCL
Clock
tCYC
tCES tCEH
CKE
Address
A2
A1
A3
WRITE
CEx
ADV
OE
tDS
Data In
D1-1
D2-1
D2-2
D2-3
D2-4
D3-1
tDH
D3-2
D3-3
D3-4
tHZOE
Data Out
Q0-3
Q0-4
Don't Care
NOTES: WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
White Electronic Designs Corporation • Westborough, MA • (508) 366-5151
Undefined
8
WED2ZL362MSJ
White Electronic Designs
FIG. 5 TIMING WAVEFORM OF SINGLE READ/WRITE
tCH
tCL
Clock
tCYC
tCES tCEH
CKE
Address
A1
A2
A3
A4
Q1
Q3
A5
A6
A8
A7
A9
WRITE
CEx
ADV
OE
tOE
tLZOE
Data Out
Q6
Q7
tDH
tDS
Data In
Q4
D2
D5
Don't Care
NOTES: WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
Undefined
9
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WED2ZL362MSJ
White Electronic Designs
FIG. 6 TIMING WAVEFORM OF CKE OPERATION
tCL
tCH
Clock
tCES tCEH
tCYC
CKE
Address
A1
A2
A3
A4
A5
A6
WRITE
CEx
ADV
OE
tCD
tLZC
Data Out
tHZC
Q1
Q3
tDH
tDS
Data In
Q4
D2
Don't Care
NOTES: WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
White Electronic Designs Corporation • Westborough, MA • (508) 366-5151
Undefined
10
WED2ZL362MSJ
White Electronic Designs
FIG. 7 TIMING WAVEFORM OF CE OPERATION
tCH
tCL
Clock
tCYC
tCEH
tCES
CKE
Address
A1
A2
A3
A4
A5
WRITE
CEx
ADV
OE
tHZC
tOE
tLZOE
Data Out
Q1
tCD
tLZC
Q2
Q4
tDS tDH
Data In
D3
D5
Don't Care
NOTES: WRITE = L means WE = L, and BWx = L
CEx refers to the combination of CE1, CE2 and CE2.
Undefined
11
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WED2ZL362MSJ
White Electronic Designs
PACKAGE DIMENSION: 119 BUMP PBGA
2.50 (0.099)
MAX
7.62 (0.300)
TYP
14.00 (0.551) TYP
R 1.52 (0.060)
MAX (4x)
7 6 5 4 3 2 1
A
B
A1
CORNER
C
D
E
F
1.27 (0.050)
TYP
G
H
20.32 (0.800)
TYP
22.00 (0.866)
TYP
J
K
L
M
N
P
R
T
U
0.600 (0.024)
MAX
1.27 (0.050) TYP
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined.
ORDERING INFORMATION
Commercial Temp Range (0°C to 70°C), Industrial Temp. Range (-40° to 85°C)
Part Number
Configuration
t CD
Clock
Operating
(ns)
(MHz)
Range
WED2ZL362MSJ35ES
2M x 36
3.5
166
Engineering Samples
WED2ZL362MSJ38ES
2M x 36
3.8
150
Engineering Samples
WED2ZL362MSJ28BC
2M x 36
2.8
225
Commercial
WED2ZL362MSJ30BC
2M x 36
3.0
200
Commercial
WED2ZL362MSJ35BC
2M x 36
3.5
166
Commercial
WED2ZL362MSJ38BC
2M x 36
3.8
150
Commercial
WED2ZL362MSJ30BI
2M x 36
3.0
200
Industrial
WED2ZL362MSJ35BI
2M x 36
3.5
166
Industrial
WED2ZL362MSJ38BI
2M x 36
3.8
150
Industrial
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12