CY23EP09 2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer Features Functional Description • 10 MHz to 220 MHz maximum operating range • Zero input-output propagation delay, adjustable by loading on CLKOUT pin • Multiple low-skew outputs — 45 ps typical output-output skew — One input drives nine outputs, grouped as 4 + 4 + 1 • 25 ps typical cycle-to-cycle jitter • 15 ps typical period jitter • Standard and High drive strength options • Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The -1H version operates up to 220 (200) MHz frequencies at 3.3V (2.5V), and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. There are two banks of four outputs each, which can be controlled by the Select inputs as shown in the “Select Input Decoding” table on page 2. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The PLL enters a power-down mode when there are no rising edges on the REF input (less than ~2 MHz). In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25 µA of current draw. • 3.3V or 2.5V operation • Industrial temperature available In the special case when S2:S1 is 1:0, the PLL is bypassed and REF is output from DC to the maximum allowable frequency. The part behaves like a non-zero delay buffer in this mode, and the outputs are not tri-stated. The CY23EP09 is available in different configurations, as shown in the Ordering Information table. The CY23EP09-1 is the base part. The CY23EP09-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. These parts are not intended for 5V input-tolerant applications Pin Configuration Block Diagram PLL MUX REF CLKOUT Top View CLKA1 REF CLKA1 1 16 CLKA2 2 15 CLKA2 VDD 3 14 CLKA3 4 13 GND CLKB1 CLKB2 S2 5 12 6 11 7 10 8 9 CLKA4 CLKB1 S2 Select Input Decoding CLKB2 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 CLKB3 S1 CLKB4 Cypress Semiconductor Corporation Document #: 38-07760 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 5, 2005 CY23EP09 Pin Definition Pin Signal Description 1 REF[1] Input reference frequency 2 CLKA1[2] Buffered clock output, Bank A 3 CLKA2[2] Buffered clock output, Bank A 4 VDD 3.3V or 2.5V supply 5 GND Ground 6 CLKB1[2] Buffered clock output, Bank B 7 [2] CLKB2 Buffered clock output, Bank B 8 S2[3] Select input, bit 2 9 S1[3] Select input, bit 1 10 CLKB3[2] Buffered clock output, Bank B 11 CLKB4[2] Buffered clock output, Bank B 12 GND Ground 13 VDD 3.3V or 2.5V supply 14 CLKA3[2] Buffered clock output, Bank A 15 CLKA4[2] Buffered clock output, Bank A 16 CLKOUT[2] Buffered output, internal feedback on this pin Select Input Decoding S2 S1 CLOCK A1–A4 CLOCK B1–B4 CLKOUT[4] Output Source PLL Shutdown 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. The output driving the CLKOUT pin will be driving a total load of 5 pF plus any additional load externally connected to this pin. For applications requiring zero input-output delay, the total load on each output pin (including CLKOUT) must be the same. If input-output delay adjustments are required, the CLKOUT load may be changed to vary the delay between the REF input and remaining outputs. For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note entitled “CY2305 and CY2309 as PCI and SDRAM Buffers”. Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Document #: 38-07760 Rev. *B Page 2 of 13 CY23EP09 Absolute Maximum Conditions Storage Temperature .................................... –65°C to 150°C Junction Temperature .................................................. 150°C Supply Voltage to Ground Potential ................. –0.5V to 4.6V Static Discharge Voltage (per MIL-STD-883, Method 3015.............................. > 2000V DC Input Voltage...................................... VSS – 0.5V to 4.6V Operating Conditions Parameter Description Min. Max. Unit VDD3.3 3.3V Supply Voltage 3.0 3.6 V VDD2.5 2.5V Supply Voltage 2.3 2.7 V TA Operating Temperature (Ambient Temperature)—Commercial Operating Temperature (Ambient Temperature)—Industrial CL[5] 0 70 °C –40 85 °C Load Capacitance, <100 MHz, 3.3V – 30 pF Load Capacitance, <100 MHz, 2.5V with High drive – 30 pF Load Capacitance, <133.3 MHz, 3.3V – 22 pF Load Capacitance, <133.3 MHz, 2.5V with High drive – 22 pF Load Capacitance, <133.3 MHz, 2.5V with Standard drive – 15 pF Load Capacitance, >133.3 MHz, 3.3V – 15 pF Load Capacitance, >133.3 MHz, 2.5V with High drive – 15 pF CIN Input Capacitance[6] – 5 pF BW Closed-loop bandwidth (typical), 3.3V 1–1.5 MHz Closed-loop bandwidth (typical), 2.5V 0.8 MHz Output Impedance (typical), 3.3V High drive 29 Ω Output Impedance (typical), 3.3V Standard drive 41 Ω Output Impedance (typical), 2.5V High drive 37 Ω Output Impedance (typical), 2.5V Standard drive 41 Ω ROUT tPU Power-up time for all VDD’s to reach minimum specified voltage (power ramps must be monotonic) Theta Ja[7] Dissipation, Junction to Ambient, 16-pin SOIC 95 °C/W Dissipation, Junction to Ambient, 16-pin TSSOP 70 °C/W Dissipation, Junction to Case, 16-pin SOIC 58 °C/W Dissipation, Junction to Case, 16-pin TSSOP 48 °C/W Theta Jc[7] 0.01 50 ms 3.3V DC Electrical Specifications Parameter Description Test Conditions Min. Max. Unit 3.0 3.6 V – 0.8 V VDD Supply Voltage VIL Input LOW Voltage VIH Input HIGH Voltage 2.0 VDD+0.3 V IIL Input Leakage Current 0 < VIN < VIL – ±10 µA IIH Input HIGH Current VIN = VDD – 100 µA VOL Output LOW Voltage IOL = 8 mA (standard drive) IOL = 12 mA (High drive) – – 0.4 0.4 V V VOH Output HIGH Voltage IOH = –8 mA (standard drive) IOH = –12 mA (High drive) 2.4 2.4 – – V V IDD (PD mode) Power Down Supply Current REF = 0 MHz (Commercial) IDD Supply Current – 12 µA REF = 0 MHz (Industrial) – 25 µA Unloaded outputs, 66-MHz REF – 30 mA Notes: 5. Applies to Test Circuit #1. 6. Applies to both REF Clock and internal feedback path on CLKOUT. 7. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1. Document #: 38-07760 Rev. *B Page 3 of 13 CY23EP09 2.5V DC Electrical Specifications Parameter Description Test Conditions VDD Supply Voltage VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input Leakage Current 0<VIN < VDD IIH Input HIGH Current VOL Output LOW Voltage VOH Output HIGH Voltage IOH = –8 mA (Standard drive) IOH = –12 mA (High drive) IDD (PD mode) Power Down Supply Current REF = 0 MHz (Commercial) IDD Supply Current Min. Max. Unit 2.3 2.7 V – 0.7 V 1.7 VDD+ 0.3 V – 10 µA VIN = VDD – 100 µA IOL = 8 mA (Standard drive) IOL = 12 mA (High drive) – – 0.5 0.5 V V VDD – 0.6 VDD – 0.6 – – V V – 12 µA REF = 0 MHz (Industrial) – 25 µA Unloaded outputs, 66-MHz REF – 45 mA 3.3V and 2.5V AC Electrical Specifications Parameter 1/t1 Description Maximum Frequency[8] (Input/Output) Min. Typ. Max. Unit 3.3V High drive Test Conditions 10 – 220 MHz 3.3V Standard drive 10 – 167 MHz 2.5V High drive 10 – 200 MHz 2.5V Standard drive 10 – 133 MHz TIDC Input Duty Cycle <133.3 MHz 25 – 75 % >133.3 MHz 40 – 60 % t2 ÷ t1 Output Duty Cycle[9] <133.3 MHz 47 – 53 % >133.3 MHz 45 – 55 % t3,t4 Rise, Fall Time (3.3V)[9] Std drive, CL = 30 pF, <100 MHz – – 1.6 ns Std drive, CL = 22 pF, <133.3 MHz – – 1.6 ns Std drive, CL = 15 pF, <167 MHz – – 0.6 ns High drive, CL = 30 pF, <100 MHz – – 1.2 ns High drive, CL = 22 pF, <133.3 MHz – – 1.2 ns High drive, CL = 15 pF, >133.3 MHz – – 0.5 ns Std drive, CL = 15 pF, <133.33 MHz – – 1.5 ns High drive, CL = 30 pF, <100 MHz – – 2.1 ns High drive, CL = 22 pF, <133.3 MHz – – 1.3 ns High drive, CL = 15 pF, >133.3 MHz – – 1.2 ns – 45 100 ps – – 110 ps t3, t4 t5 Rise, Fall Time (2.5V)[9] Output to Output Skew [9] All outputs equally loaded, 3.3V supply, 2.5 supply standard drive All outputs equally loaded, 2.5V supply high drive t6 t7 Delay, REF Rising Edge to PLL Bypass mode CLKOUT Rising Edge[9] PLL enabled @ 3.3V 1.5 – 4.4 ns –100 – 100 ps PLL enabled @2.5V Part to Part Skew[9] –200 – 200 ps Measured at VDD/2. Any output to any output, 3.3V supply – – ±150 ps Measured at VDD/2. Any output to any output, 2.5V supply – – ±300 ps Notes: 8. For the given maximum loading conditions. See CL in Operating Conditions Table. 9. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07760 Rev. *B Page 4 of 13 CY23EP09 3.3V and 2.5V AC Electrical Specifications (continued) Parameter Description Test Conditions Min. Typ. Max. Unit – – 1.0 ms – 25 55 ps 3.3V supply, >66 MHz, <30 pF, standard drive – 65 125 ps 3.3V supply, >66 MHz, <30 pF, high drive – 53 100 ps tLOCK PLL Lock Time[9] TJCC[9,10] Cycle-to-cycle Jitter, Peak 3.3V supply, >66 MHz, <15 pF TPER[9,10] Stable power supply, valid clocks presented on REF and CLKOUT pins Period Jitter, Peak 2.5V supply, >66 MHz, <15 pF, standard drive – 35 95 ps 2.5V supply, >66 MHz, <15 pF, high drive – 30 65 ps 2.5V supply, >66 MHz, <30 pF, high drive – 75 145 ps S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive – 16 – ps S2:S1 = 1:0 mode, 3.3V, <15pF, high drive – 14 – ps S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive – 23 – ps S2:S1 = 1:0 mode, 2.5V, <15pF, high drive – 22 – ps 3.3V supply, 66–100 MHz, <15 pF – 20 75 ps 3.3V supply, >100 MHz, <15 pF – 15 45 ps 3.3V supply, >66 MHz, <30 pF, standard drive – 40 100 ps 3.3V supply, >66 MHz, <30 pF, high drive – 30 70 ps 2.5V supply, >66 MHz, <15 pF, standard drive – 25 60 ps 2.5V supply, 66–100 MHz, <15 pF, high drive – 25 60 ps 2.5V supply, >100 MHz, <15 pF, high drive – 15 45 ps S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive – 28 – ps S2:S1 = 1:0 mode, 3.3V, <15pF, high drive – 24 – ps S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive – 40 – ps S2:S1 = 1:0 mode, 2.5V, <15pF, high drive – 37 – ps Note: 10. Typical jitter is measured at 3.3V or 2.5V, 29°C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be found in the application note “Understanding Data Sheet Jitter Specifications for Cypress Clock Products.” Switching Waveforms Duty Cycle Timing t1 t2 VDD/2 VDD/2 VDD/2 All Outputs Rise/Fall Time OUTPUT 2.0V(1.8V) 0.8V(0.6V) t3 Document #: 38-07760 Rev. *B 2.0V(1.8V) 0.8V(0.6V) 3.3V(2.5V) 0V t4 Page 5 of 13 CY23EP09 Switching Waveforms (continued) Output-Output Skew OUTPUT VDD/2 VDD/2 OUTPUT t5 Input-Output Propagation Delay INPUT VDD/2 VDD/2 CLKOUT t6 Part-Part Skew VDD/2 Any output, Part 1 or 2 VDD/2 Any output, Part 1 or 2 t7 Test Circuits Test Circuit # 1 V DD CLK 0.1 µ F OUTPUTS C LOAD V DD 0.1 µ F GND Document #: 38-07760 Rev. *B GND Page 6 of 13 CY23EP09 Delay REF Input to CLKA/B (ps) Supplemental Parametric Information 1200 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -1200 S tandard D rive H igh D rive -20 -10 0 10 20 Load C LK O U T- Load C LK A/B (pF) Figure 1. 2.5V Typical Room Temperature Graph for REF Input to CLKA/CLKB Delay versus Loading Difference between CLKOUT and CLKA/CLKB. Data is shown for 66 MHz. Delay is a weak function of frequency. 1200 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -1200 Standard Drive High Drive -20 -10 0 10 20 Load CLKOUT- Load CLKA/B (pF) Figure 2. 3.3V Typical Room Temperature Graph for REF Input to CLKA/CLKB Delay versus Loading Difference between CLKOUT and CLKA/CLKB. Data is shown for 66 MHz. Delay is a weak function of frequency. Document #: 38-07760 Rev. *B Page 7 of 13 CY23EP09 200 175 150 125 100 15pF, -45C, Standard Drive 15pF, 90C, Standard Drive 30pF, -45C, Standard Drive 30pF, 90C, Standard Drive 15pF, -45C, High Drive 15pF, 90C, High Drive 30pF, -45C, High Drive 30pF, 90C, High Drive 75 50 25 33 66 100 133 166 200 233 Frequency (MHz) Figure 3. 3.6V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature. Note that the 30-pF data above 100 MHz is beyond the data sheet specification of 22 pF. 120 100 80 15pF, -45C, Standard Drive 60 15pF, 90C, Standard Drive 15pF, -45C, High Drive 40 15pF, 90C, High Drive 30pF, -45C, High Drive 30pF, 90C, High Drive 20 33 66 100 133 166 200 Frequency (MHz) Figure 4. 2.7V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature. Note that the 30-pF high-drive data above 100bMHz is beyond the data sheet specification of 22 pF. Document #: 38-07760 Rev. *B Page 8 of 13 CY23EP09 350 15 15 30 30 300 250 pF, pF, pF, pF, S ta n d a rd D riv e H ig h D riv e S ta n d a rd D riv e H ig h D riv e 200 150 100 50 0 0 50 100 150 200 250 F re q u e n c y (M H z ) Figure 5. Typical 3.3V Measured Cycle-to-cycle Jitter at 29°C, versus Frequency, Drive Strength, and Loading 350 1 5 p F , S t a n d a r d D r iv e 1 5 p F , H ig h D r iv e 3 0 p F , H ig h D r iv e 300 250 200 150 100 50 0 0 20 40 60 80 100 120 140 160 180 200 F re q u e n c y (M H z ) Figure 6. Typical 2.5V Measured Cycle-to-cycle Jitter at 29°C, versus Frequency, Drive Strength, and Loading 250 15 15 30 30 200 pF, pF, pF, pF, S t a n d a r d D r iv e H ig h D r iv e S t a n d a r d D r iv e H ig h D r iv e 150 100 50 0 0 50 100 150 200 250 F re q u e n c y (M H z ) Figure 7. Typical 3.3V Measured Period Jitter at 29°C, versus Frequency, Drive Strength, and Loading 250 1 5 p F , S t a n d a r d D r iv e 1 5 p F , H ig h D r iv e 3 0 p F , H ig h D r iv e 200 150 100 50 0 0 50 100 150 200 250 F re q u e n c y (M H z ) Figure 8. Typical 2.5V Measured Period Jitter at 29°C, versus Frequency, Drive Strength, and Loading Document #: 38-07760 Rev. *B Page 9 of 13 CY23EP09 SSB Phase Noise (dBc/Hz) -90 2.5V, Standard Drive 2.5V, High Drive -100 3.3V, Standard Drive 3.3V, High Drive -110 -120 2.5V, Standard Drive 2.5V, High Drive -130 100 MHz -140 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 Offset Frequency (Hz) 1.E+06 1.E+07 1.E+08 SSB Phase Noise (dBc/Hz) -90 2.5V, High Drive 3.3V, High Drive -100 -110 3.3V, Standard Drive 2.5V, Standard Drive -120 -130 156.25 MHz -140 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 Offset Frequency (Hz) 1.E+06 1.E+07 1.E+08 Figure 9. Typical Phase-noise Data at 100 MHz (top) and 156.25 MHz (bottom) across VDD and Drive Strength[10] Document #: 38-07760 Rev. *B Page 10 of 13 CY23EP09 Ordering Information Ordering Code Package Type Operating Range Lead-free CY23EP09SXC-1 16-pin 150-mil SOIC CY23EP09SXC-1T 16-pin 150-mil SOIC – Tape and Reel Commercial CY23EP09SXI-1 16-pin 150-mil SOIC – Industrial CY23EP09SXI-1T 16-pin 150-mil SOIC – Tape and Reel Industrial CY23EP09SXC-1H 16-pin 150-mil SOIC Commercial CY23EP09SXC-1HT 16-pin 150-mil SOIC – Tape and Reel Commercial CY23EP09SXI-1H 16-pin 150-mil SOIC Industrial CY23EP09SXI-1HT 16-pin 150-mil SOIC – Tape and Reel Industrial CY23EP09ZXC-1H 16-pin 4.4-mm TSSOP Commercial CY23EP09ZXC-1HT 16-pin 4.4-mm TSSOP – Tape and Reel Commercial CY23EP09ZXI-1H 16-pin 4.4-mm TSSOP Industrial CY23EP09ZXI-1HT 16-pin 4.4-mm TSSOP – Tape and Reel Industrial Package Drawing and Dimensions 16 Lead (150 Mil) SOIC Commercial 16-Lead (150-Mil) SOIC S16 PIN 1 ID 8 1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 PACKAGE WEIGHT 0.15gms 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16 0.386[9.804] 0.393[9.982] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0°~8° 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85068-*B Document #: 38-07760 Rev. *B Page 11 of 13 CY23EP09 Package Drawing and Dimensions (continued) 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07760 Rev. *B Page 12 of 13 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY23EP09 Document History Page Document Title: CY23EP09 2.5V or 3.3V, 10-220-MHz, Low Jitter, 9-Output Zero Delay Buffer Document Number: 38-07760 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 345446 See ECN RGL New data sheet *A 355777 See ECN RGL Updated part to part skew to agree with latest char results *B 401036 See ECN RGL Added PLL-bypass jitter Added Phase-noise graph Added 2.5V Delay vs. Load graph Removed Preliminary Document #: 38-07760 Rev. *B Page 13 of 13