CY29940 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Features 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible inputs 18 clock outputs: drive up to 36 clock lines 60 ps typical output-to-output skew Dual or single supply operation: — 3.3V core and 3.3V outputs — 3.3V core and 2.5V outputs — 2.5V core and 2.5V outputs • Pin compatible with MPC940L, MPC9109 • Available in Commercial and Industrial temperature • 32-pin LQFP package The CY29940 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS/LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output skews make the CY29940 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. Block Diagram Q0 Q1 Q2 VDDC Q3 Q4 Q5 VSS 31 30 29 28 27 26 25 13 14 15 16 Q14 Q13 Q12 VDDC CY29940 12 1 2 3 4 5 6 7 8 VSS VSS VSS TCLK TCLK_SEL PECL_CLK PECL_CLK# VDD VDDC 11 1 TCLK_SEL Q0-Q17 Q15 18 9 TCLK 0 10 PECL_CLK PECL_CLK# VDDC Q16 VDD 32 Pin Configuration Q17 • • • • • • Description 24 23 22 21 20 19 18 17 Q6 Q7 Q8 VDD Q9 Q10 Q11 VSS Pin Description[1] Pin Name PWR I/O Description 5 PECL_CLK I, PU PECL Input Clock 6 PECL_CLK# I, PD PECL Input Clock 3 TCLK I, PD External Reference/Test Clock Input 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 Q(17:0) 4 TCLK_SEL 8, 16, 29 VDDC 3.3V or 2.5V Power Supply for Output Clock Buffers 7, 21 VDD 3.3V or 2.5V Power Supply 1, 2, 12, 17, 25 VSS Common Ground VDDC O I, PD Clock Outputs Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. Note: 1. PD = Internal Pull-Down, PU = Internal Pull-up Cypress Semiconductor Corporation Document #: 38-07283 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 4, 2006 [+] Feedback CY29940 Maximum Ratings[2] Storage Temperature: ................................ –65°C to + 150°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Operating Temperature: ................................ –40°C to +85°C VSS < (Vin or Vout) < VDD Maximum ESD Protection............................................... 2 kV Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................±20 mA DC Parameters[2]: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C Parameter Description VIL Input Low Voltage VIH Input High Voltage IIL Input Low Current Typ. Max. Unit. VSS – 0.8 V 2.0 – VDD V – –200 µA Current[3] Input High VPP Peak-to-Peak Input Voltage PECL_CLK VCMR Common Mode Range[4] PECL_CLK Voltage[5, 6, 7] VOL Output Low VOH Output High Voltage[5, 6, 7] IDDQ Quiescent Supply Current IDD Dynamic Supply Current Cin Min. [3] IIH Zout Conditions Output Impedance Input Capacitance – 200 µA 500 – 1000 mV VDD = 3.3V VDD – 1.4 – VDD – 0.6 V VDD = 2.5V VDD – 1.0 – VDD – 0.6 V IOL = 20 mA – – 0.5 V IOH = –20 mA, VDDC = 3.3V 2.4 – – V IOH = –20 mA, VDDC = 2.5V 1.8 – – V – 5 7 mA VDD = 3.3V, Outputs @ 150 MHz, CL = 15 pF – 285 – mA VDD = 3.3V, Outputs @ 200 MHz, CL = 15 pF – 335 – VDD = 2.5V, Outputs @ 150 MHz, CL = 15 pF – 200 – VDD = 2.5V, Outputs @ 200 MHz, CL = 15 pF – 240 – VDD = 3.3V 8 12 16 VDD = 2.5V 10 15 20 – 4 – Ω pF Notes: 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines 5. Outputs driving 50Ω transmission lines. 6. See Figure 1 &2. 7. 50% input duty cycle. Document #: 38-07283 Rev. *C Page 2 of 7 [+] Feedback CY29940 AC Parameters[8]: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C Parameter Description Fmax Input Frequency tPD PECL_CLK to Q Delay[5, 6, 11] </=150 MHz tPD tJ FoutDC Tskew Tskew(pp) Tskew(pp) Tskew(pp) tR/tF LVCMOS to Q Delay[5, 6, 11] </=150 MHz Total Jitter Output Duty Cycle[5, 6, 7] Output-to-Output Skew[5, 6] Part-to-Part Skew[9] Conditions – Min. Typ. Max. Unit. – – 200 MHz VDD = 3.3V 85°C tPHL 2.0 – 3.2 ns tPLH 2.1 – 3.4 VDD = 3.3V 70°C tPHL 1.9 – 3.1 tPLH 2.0 – 3.2 VDD = 2.5V 85°C tPHL 2.5 – 5.2 tPLH 2.6 – 5 VDD = 2.5V 70°C tPHL 2.5 – 5 tPLH 2.6 – 5 VDD = 3.3V 85°C tPHL 1.9 – 3 tPLH 2.0 – 3.2 VDD = 3.3V 70°C tPHL 1.8 – 2.9 tPLH 1.8 – 3.1 VDD = 2.5V 85°C tPHL 2.5 – 4 tPLH 2.5 – 4 VDD = 2.5V 70°C tPHL 2.3 – 3.8 tPLH ns 2.3 – 3.8 VDD = 3.3V @ 150MHz – – 10 ps FCLK < 134 MHz – – 55 % FCLK > 134 MHz – – 60 VDD = 3.3V – 60 150 VDD = 2.5V – PECL, VDDC = 3.3V – – 1.4 PECL, VDDC = 2.5V – – 2.2 TCLK, VDDC = 3.3V – – 1.2 TCLK, VDDC = 2.5V – – 1.7 PECL_CLK – – 850 TCLK – – 750 Output Clocks Rise/Fall Time[5, 6] 0.7V to 2.0V, VDDC = 3.3V 0.3 – 1.1 0.5V to 1.8V, VDDC = 2.5V 0.3 – 1.2 Part-to-Part Skew[9] Part to Part Skew[10] ps 200 ns ns ps ns Notes: 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 9. Across temperature and voltage ranges, includes output skew. 10. For a specific temperature and voltage, includes output skew 11. Parameters tested @ 150 MHz. Document #: 38-07283 Rev. *C Page 3 of 7 [+] Feedback CY29940 CY29940 DUT Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 1. LVCMOS_CLK CY29940 Test Reference for VCC = 3.3V and VCC = 2.5V Zo = 50 ohm Differential Pulse Generator Z = 50 ohm CY29940 DUT Zo = 50 ohm Zo = 50 ohm RT = 50 ohm VTT RT = 50 ohm VTT Figure 2. PECL_CLK CY29940 Test Reference for VCC = 3.3V and VCC = 2.5V PECL_CLK PECL_CLK VPP VCC VCMR VCC /2 tP GND VCC Q VCC /2 tPD GND Figure 3. Propagation Delay (TPD) Test Reference T0 DC = tP / T0 x 100% Figure 5. Output Duty Cycle (FoutDC) VCC LVCMOS_CLK VCC VCC /2 VCC /2 GND GND VCC Q VCC VCC /2 tPD GND Figure 4. LVCMOS Propagation Delay (TPD) Test Reference Document #: 38-07283 Rev. *C VCC /2 tSK(0) GND Figure 6. Output-to-Output Skew tsk(0) Page 4 of 7 [+] Feedback CY29940 Ordering Information Part Number CY29940AI CY29940AIT CY29940AC Package Type Production Flow 32 Pin LQFP Industrial, –40°C to +85°C 32 Pin LQFP – Tape and Reel Industrial, –40°C to +85°C 32 Pin LQFP Commercial, 0°C to 70°C 32 Pin LQFP – Tape and Reel Commercial, 0°C to 70°C 32 Pin LQFP Industrial, –40°C to +85°C CY29940AXIT 32 Pin LQFP – Tape and Reel Industrial, –40°C to +85°C CY29940AXC 32 Pin LQFP Commercial, 0°C to 70°C 32 Pin LQFP – Tape and Reel Commercial, 0°C to 70°C CY29940ACT Lead-free CY29940AXI CY29940AXCT Document #: 38-07283 Rev. *C Page 5 of 7 [+] Feedback CY29940 Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14 51-85088-*B All product and company names mentioned in this document may be the trademarks of their respective owners. Document #: 38-07283 Rev. *C Page 6 of 7 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY29940 Document History Page Document Title: CY29940 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Document Number: 38-07283 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 111094 02/01/02 BRK New data sheet *A 116776 08/15/02 HWT Incorporate results of final characterization using corporate methods, added output impedance on page 3 and added output duty cycle on page 4. Add commercial temperature range in the ordering information on page 6. *B 122875 12/21/02 RBI Add power up requirements to maximum rating information *C 448379 See ECN RGL Add typical value for output-to-output skew Add Lead-free devices Document #: 38-07283 Rev. *C Page 7 of 7 [+] Feedback