W3DG7268V-D1 -JD1 White Electronic Designs PRELIMINARY* 512MB- 64Mx72 SDRAM UNBUFFERED FEATURES DESCRIPTION PC100 and PC133 Compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs The W3DG7268V is a 64Mx72 synchronous DRAM module which consists of nine 64Mx8 SDRAM components in TSOP II package, and one 2K EEPROM in an 8 pin TSSOP package for Serial Presence Detect which are mounted on a 144 Pin SO-DIMM multilayer FR4 Substrate. Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V ± 0.3V Power Supply 144 Pin SO-DIMM JEDEC * This product is under development, is not qualified or characterized and is subject to change without notice. • Package height option: JD1: 31.75 (1.25") PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) PIN NAMES PIN FRONT PIN BACK PIN FRONT PIN BACK PIN FRONT PIN BACK 1 VSS 2 VSS 49 DQ13 50 DQ45 97 DQ22 98 DQ54 3 DQ0 4 DQ32 51 DQ14 52 DQ46 99 DQ23 100 DQ55 5 DQ1 6 DQ33 53 DQ15 54 DQ47 101 VCC 102 VCC 7 DQ2 8 DQ34 55 VSS 56 VSS 103 A6 104 A7 9 DQ3 10 DQ35 57 CB0 58 CB4 105 A8 106 BA0 11 VCC 12 VCC 59 CB1 60 CB5 107 VSS 108 VSS 13 DQ4 14 DQ36 61 CLK0 62 CKE0 109 A9 110 BA1 15 DQ5 16 DQ37 63 VCC 64 VCC 111 A10 112 A11 17 DQ6 18 DQ38 65 RAS# 66 CAS# 113 VCC 114 VCC 19 DQ7 20 DQ39 67 WE# 68 NC 115 DQMB2 116 DQMB6 21 VSS 22 VSS 69 CS0# 70 A12 117 DQMB3 118 DQMB7 23 DQMB0 24 DQB4 71 NC 72 NC 119 VSS 120 VSS 25 DQMB1 26 DQB5 73 NC 74 CLK1 121 DQ24 122 DQ56 27 VCC 28 VCC 75 VSS 76 VSS 123 DQ25 124 DQ57 29 A0 30 A3 77 CB2 78 CB6 125 DQ26 126 DQ58 31 A1 32 A4 79 CB3 80 CB7 127 DQ27 128 DQ59 33 A2 34 A5 81 VCC 82 VCC 129 VCC 130 VCC 35 VSS 36 VSS 83 DQ16 84 DQ48 131 DQ28 132 DQ60 37 DQ8 38 DQ40 85 DQ17 86 DQ49 133 DQ29 134 DQ61 39 DQ9 40 DQ41 87 DQ18 88 DQ50 135 DQ30 136 DQ62 41 DQ10 42 DQ42 89 DQ19 90 DQ51 137 DQ31 138 DQ63 43 DQ11 44 DQ43 91 VSS 92 VSS 139 VSS 140 VSS 45 VCC 46 VCC 93 DQ20 94 DQ52 141 SDA 142 SCL 47 DQ12 48 DQ44 95 DQ21 96 DQ53 143 VCC 144 VCC October 2004 Rev. 2 1 A0 – A12 BA0-1 DQ0-63 Address input (Multiplexed) Select Bank Data Input/Output CB0-7 CLK0,CK1 CKE0 CS0# RAS# CAS# WE# DQMB0-7 VCC VSS SDA SCL DNU NC Check bit (Data-in/data-out) Clock input Clock Enable input Chip select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Serial data I/O Serial clock Do not use No Connect White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3DG7268V-D1 -JD1 White Electronic Designs PRELIMINARY FUNCTIONAL BLOCK DIAGRAM WE# CS0# DQMB0 DQMB4 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O CS0# WE# DQM 0 1 2 3 4 5 6 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB1 I/O I/O I/O I/O I/O I/O I/O CS0# WE# CS0# WE# CS0# WE# CS0# WE# 0 1 2 3 4 5 6 I/O 7 DQMB5 DQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O I/O I/O I/O I/O CS0# WE# DQM 0 1 2 3 4 5 6 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 DQMB6 DQM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O I/O I/O I/O I/O I/O I/O I/O CS0# WE# DQM 0 1 2 3 4 5 6 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB2 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 DQMB7 DQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O I/O I/O I/O I/O DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O I/O I/O I/O CS0# WE# DQM 0 1 2 3 4 5 6 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O I/O I/O I/O I/O I/O I/O I/O 0 1 2 3 4 5 6 7 DQMB3 DQM CS0# WE# Note: DQ wiring may differ than described in this drawing, however DQ/DQMB/CKE/S relationships must be maintained as shown. 0 1 2 3 4 5 6 I/O 7 *CLOCK WIRING RAS# CAS# CKE0 BA0-BA1 A0-A12 RAS#: SDRAM D0-D8 CAS#: SDRAM D0-D8 CKE: SDRAM D0-D8 BA0-BA1: SDRAM D0-D8 A0-A12: SDRAM D0-D8 CLOCK INPUT SDRAMS *CLK0 5 SDRAMS *CLK1 4 SDRAMS *Wire per Clock Loading Table/Wiring Diagrams VCC D0-D8 VSS D0-D8 SERIAL PD SCL SDA A0 October 2004 Rev. 2 2 A1 A2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3DG7268V-D1 -JD1 White Electronic Designs PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Storage Temperature Power Dissipation PD 9 W Short Circuit Current IOS 50 mA Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS Voltage Referenced to: VSS = 0V, 0°C ≤ TA ≤ +70°C Parameter Symbol Min Typ Max Unit Supply Voltage VCC 3.0 3.3 3.6 V Note Input High Voltage VIH 2.0 3.0 VCCQ+0.3 V 1 Input Low Voltage VIL -0.3 — 0.8 V 2 Output High Voltage VOH 2.4 — — V IOH = -2mA Output Low Voltage VOL — — 0.4 V IOL= + 2mA Input Leakage Current ILI -10 — 10 µA 3 Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE TA = 25°C, f = 1MHz, VCC = 3.3V, VREF = 1.4V ± 200mV Parameter Symbol Max Unit Input Capacitance (A0-A12) CIN1 36 pF Input Capacitance (RAS#,CAS#,WE#) CIN2 36 pF Input Capacitance (CKE0) CIN3 36 pF Input Capacitance (CK0) CIN4 20 pF Input Capacitance (CS0#) CIN5 36 pF Input Capacitance (DQM0-DQM7) CIN6 7 pF Input Capacitance (BA0-BA1) CIN7 36 pF Data Input/Output Capacitance (DQ0-DQ63) COUT 9 pF Data input/output capacitance (CB0-CB7) COUT1 9 pF October 2004 Rev. 2 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3DG7268V-D1 -JD1 White Electronic Designs PRELIMINARY OPERATING CURRENT CHARACTERISTICS VCC = 3.3V, 0°C ≤ TA ≤ +70°C Version Parameter Symbol Conditions 100/133 Units Note 1800 mA 1 Operating Current (One bank active) ICC1 Burst Length = 1 tRC ≤ tRC(min) IOL = 0mA Precharge Standby Current in Power Down Mode ICC2 CKE ≤ VIL(max), tCC = 10ns 54 Active Standby Current in Power-Down Mode ICC3 CKE ≥ VIL(max), tCC = 10ns 90 ICC4 Io = mA Page burst 4 Banks activated tCCD = 2CK 1125 mA 1 2205 mA 2 54 mA Operating Current (Burst mode) Refresh Current ICC5 tRC ≥ tRC(min) Self Refresh Current ICC6 CKE ≤ 0.2V mA mA Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. October 2004 Rev. 2 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3DG7268V-D1 -JD1 White Electronic Designs PRELIMINARY ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC CHARACTERISTICS 7 PARAMETER Access time from CLK (pos. edge) SYMBOL CL = 3 tAC(3) CL = 2 tAC(2) MIN 75/10 MAX MIN 5.4 5.4 MAX UNITS NOTES 5.4 ns 27 6 ns Address hold time tAH 0.8 0.8 ns Address setup time tAS 1.5 1.5 ns CLK high-level width tCH 2.5 2.5 ns CLK low-level width tCL 2.5 2.5 ns Clock cycle time CL = 3 tCK(3) 7 7.5 ns 23 CL = 2 tCK(2) 7.5 10 ns 23 CKE hold time tCKH 0.8 0.8 ns CKE setup time tCKS 1.5 1.5 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 ns Data-in hold time tDH 0.8 0.8 ns Data-in setup time tDS 1.5 1.5 Data-out high-impedance time Data-out low-impedance time CL = 3 tHZ(3) CL = 2 tHZ(2) 5.4 5.4 ns 5.4 ns 10 6 ns 10 tLZ 1 1 ns Data-out hold time (load) tOH 2.7 2.7 ns Data-out hold time (no load) tOHN 1.8 1.8 ns ACTIVE to PRECHARGE command tRAS 37 ACTIVE to ACTIVE command period tRC 60 ACTIVE to READ or WRITE delay tRCD 15 Refresh period (8,192 rows) tREF AUTO REFRESH period tRFC 66 66 ns PRECHARGE command period tRP 15 20 ns ACTIVE bank a to ACTIVE bank b command tRRD 14 15 ns Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command October 2004 Rev. 2 120K 44 120K 66 ns 64 tT 0.3 ns 7 1 CLK + 7ns 1 CLK + 7ns - 24 14 15 ns 14, 25 67 75 ns 20 5 0.3 1.2 ms tWR tXSR 1.2 ns ns 20 64 28 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3DG7268V-D1 -JD1 White Electronic Designs PRELIMINARY AC FUNCTIONAL CHARACTERISTICS PARAMETER SYMBOL 7 75/10 UNITS NOTES READ/WRITE command to READ/WRITE command tCCD 1 1 tCK 17 CKE to clock disable or power-down entry mode tCKED 1 1 tCK 14 CKE to clock enable or power-down exit setup mode tPED 1 1 tCK 14 DQM to input data delay tDQD 0 0 tCK 17 DQM to data mask during WRITEs tDQM 0 0 tCK 17 DQM to data high-impedance during READs tDQZ 2 2 tCK 17 WRITE command to input data delay tDWD 0 0 tCK 17 Data-in to ACTIVE command tDAL 4 5 tCK 15, 21 Data-in to PRECHARGE command tDPL 2 2 tCK 16, 21 Last data-in to burst STOP command tBDL 1 1 tCK 17 Last data-in to new READ/WRITE command tCDL 1 1 tCK 17 Last data-in to PRECHARGE command tRDL 2 2 tCK 16, 21 LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 tCK 26 CL = 3 tROH(3) 3 3 tCK 17 CL = 2 tROH(2) 2 2 tCK 17 Data-out to high-impedance from PRECHARGE command October 2004 Rev. 2 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3DG7268V-D1 -JD1 PRELIMINARY Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VCC, VCCQ = +3.3V; = 25°C; pin under test biased at 1.4V. f = 1 MHz, TA 3. IDD is dependent on output loading and cycle rates.Specified values are obtained with mini-mum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ ≤ 70°C) is TA ensured. 6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VCC and VCCQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner. 9. Outputs measured at 1.5V with equivalent load: 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease in a proportional amount by the amount the frequency is altered for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 7.5ns for 75/10 and 7. 22. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL under-shoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after the first clock delay, after the last WRITE is executed. 25. Precharge mode only. 26. JEDEC and PC100, PC133 specify three clocks. 27. tAC for 75/10/7 at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. For 75/10, CL = 3, tCK = 7.5ns; For 7, CL = 2, tCK = 7.5ns 30. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are other-wise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. October 2004 Rev. 2 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3DG7268V-D1 -JD1 White Electronic Designs PRELIMINARY PACKAGE DIMENSIONS FOR JD1 Ordering Information Speed CAS Latency Height* W3DG7268V10JD1 100MHz CL=2 31.75 (1.25”) MAX W3DG7268V7JD1 133MHz CL=2 31.75 (1.25”) MAX W3DG7268V75JD1 133MHz CL=3 31.75 (1.25”) MAX Note: For industrial temperature range product, add an "I" to the end of the part number. PACKAGE DIMENSIONS FOR JD1 67.72 (2.661 Max) 3.81 (0.150) MAX. 2.01 (0.079 Min) WEDC 301 31.75 (1.25) Max 3.99 (0.157) 19.99 (0.787) 23.14 (0.913) 0.99 (0.039) (± 0.004) 32.79 (1.291) 4.60 (0.181) 28.2 (1.112) 1.50 (0.059) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES). October 2004 Rev. 2 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3DG7268V-D1 -JD1 White Electronic Designs PRELIMINARY PACKAGE DIMENSIONS FOR D1 Ordering Information Speed CAS Latency Height* W3DG7268V10AD1 100MHz CL=2 31.75 (1.25”) MAX W3DG7268V7AD1 133MHz CL=2 31.75 (1.25”) MAX W3DG7268V75AD1 133MHz CL=3 31.75 (1.25”) MAX Note: For industrial temperature range product, add an "I" to the end of the part number. PACKAGE DIMENSIONS FOR D1 S N IG S E D W E N R O F D E D N E M M O C E R 67.72 (2.661 Max) 3.81 (0.150) MAX. 2.01 (0.079 Min) 3.99 (0.157) 31.75 (1.25) Max 19.99 (0.787) 23.14 (0.913) T O N 0.99 (0.039) (± 0.004) 32.79 (1.291) 4.60 (0.181) 28.2 (1.112) 1.50 (0.059) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES). October 2004 Rev. 2 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3DG7268V-D1 -JD1 White Electronic Designs PRELIMINARY Document Title 256MB - 64Mx72 SDRAM UNBUFFERED Revision History Rev # History Release Date Status Rev 0 Created Datasheet 6-2-03 Advanced 1.1 Updated CAP and IDD Spec. 6-04 Preliminary 10-15-04 Preliminary Rev 1 1.2 Added AD1 package option 1.3 Created document title page 1.4 Moved from Advanced to Preliminary Rev 2 October 2004 Rev. 2 2.1 Added AC Spec. 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com