WED3DG6435V-D1 -JD1 White Electronic Designs 256MB – 32Mx64 SDRAM UNBUFFERED FEATURES DESCRIPTION PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM The WED3DG6435V is a 32Mx64 synchronous DRAM module which consists of eight 32Mx8 SDRAM components in TSOP II package, and one 2Kb EEPROM in an 8 pin TSOP package for Serial Presence Detect which are mounted on a 144 pin SO-DIMM multilayer FR4 Substrate. Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V ±0.3V Power Supply * This product is subject to change without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option 144 Pin SO-DIMM JEDEC • Package height Option: JD1: 31.75mm (1.25”) PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) PIN NAMES PINOUT PIN FRONT PIN BACK PIN FRONT PIN BACK PIN BACK PIN BACK 1 VSS 2 VSS 49 DQ13 50 DQ45 97 DQ22 98 DQ54 3 DQ0 4 DQ32 51 DQ14 52 DQ46 99 DQ23 100 DQ55 A0 – A12 Address Input (Multiplexed) BA0-1 Select Bank DQ0-63 Data Input/Output 5 DQ1 6 DQ33 53 DQ15 54 DQ47 101 VCC 102 VCC CK0, CK1 Clock Input 7 DQ2 8 DQ34 55 VSS 56 VSS 103 A6 104 A7 CKE0 Clock Enable Input 9 DQ3 10 DQ35 57 NC 58 NC 105 A8 106 BA0 11 VCC 12 VCC 59 NC 60 NC 107 VSS 108 VSS CS0 Chip Select Input Row Address Strobe 13 DQ4 14 DQ36 61 CK0 62 CKE0 109 A9 110 BA1 RAS# 15 DQ5 16 DQ37 63 VCC 64 VCC 111 A10 112 A11 CAS# Column Address Strobe 17 DQ6 18 DQ38 65 RAS# 66 CAS# 113 VCC 114 VCC WE# Write Enable 19 DQ7 20 DQ39 67 WE# 68 NC 115 DQMB2 116 DQMB6 21 VSS 22 VSS 69 CS0# 70 A12 117 DQMB3 118 DQMB7 DQMB0-7 DQM 23 DQMB0 24 DQMB4 71 NC 72 NC 119 VSS 120 VSS VCC Power Supply (3.3V) 25 DQMB1 26 DQMB5 73 NC 74 CK1 121 DQ24 122 DQ56 VSS Ground 27 VCC 28 VCC 75 VSS 76 VSS 123 DQ25 124 DQ57 SDA Serial Data I/O 29 A0 30 A3 77 NC 78 NC 125 DQ26 126 DQ58 31 A1 32 A4 79 NC 80 NC 127 DQ27 128 DQ59 SCL Serial Clock DNU Do Not Use NC No Connect 33 A2 34 A5 81 VCC 82 VCC 129 VCC 130 VCC 35 VSS 36 VSS 83 DQ16 84 DQ48 131 DQ28 132 DQ60 37 DQ8 38 DQ40 85 DQ17 86 DQ49 133 DQ29 134 DQ61 39 DQ9 40 DQ41 87 DQ18 88 DQ50 135 DQ30 136 DQ62 41 DQ10 42 DQ42 89 DQ19 90 DQ51 137 DQ31 138 DQ63 43 DQ11 44 DQ43 91 VSS 92 VSS 139 VSS 140 VSS 45 VCC 46 VCC 93 DQ20 94 DQ52 141 SDA 142 SCL 47 DQ12 48 DQ44 95 DQ21 96 DQ53 143 VCC 144 VCC July 2005 Rev. 5 1 ** These pins should be NC in the system which does not support SPD. White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3DG6435V-D1 -JD1 White Electronic Designs FUNCTIONAL BLOCK DIAGRAM WE# S0# DQMB0 DQMB4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# WE# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB1 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# WE# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# WE# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# WE# DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0# WE# DQMB5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 WE# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB6 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 WE# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB3 DQMB7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 WE# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 NOTE: DQ writing may differ than described in this drawing, however DQ/DQMB/CKE/S relationships must be maintained as shown. RAS# CAS# CKE0 BA0-BA1 A0-A12 RAS#: SDRAM CAS#: SDRAM CKE0: SDRAM BA0-BA1: SDRAM A0-A12: SDRAM *CLOCK WIRING CLOCK SDRAMS INPUT *CK0 4 - SDRAMS *CK1 4 - SDRAMS *Wire per Clock Loading Table/Wiring Diagrams VCC VSS SERIAL PD SDRAM SDA SCL SDRAM A0 A1 A2 Note: All resister values are 10Ω unless otherwise specified. July 2005 Rev. 5 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3DG6435V-D1 -JD1 White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Storage Temperature Power Dissipation PD 9 W Short Circuit Current IOS 50 mA Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C Parameter Symbol Min Typ Max Unit Supply Voltage VCC 3.0 3.3 3.6 V Note Input High Voltage VIH 2.0 3.0 VCCQ+0.3 V 1 Input Low Voltage VIL -0.3 — 0.8 V 2 Output High Voltage VOH 2.4 — — V IOH = -2mA Output Low Voltage VOL — — 0.4 V IOL= -2mA Input Leakage Current ILI -10 — 10 µA 3 Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE TA = 25°C, f = 1MHz, VCC = 3.3V, VREF = 1.4V ± 200mV Parameter Symbol Max Unit Input Capacitance (A0-A12) CIN1 36 pF Input Capacitance (RAS#,CAS#,WE#) CIN2 36 pF Input Capacitance (CKE0) CIN3 36 pF Input Capacitance (CK0) CIN4 16 pF Input Capacitance (CS0#) CIN5 36 pF Input Capacitance (DQM0-DQM7) CIN6 7 pF Input Capacitance (BA0-BA1) CIN7 36 pF Data Input/Output Capacitance (DQ0-DQ63) COUT 10 pF July 2005 Rev. 5 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3DG6435V-D1 -JD1 White Electronic Designs OPERATING CURRENT CHARACTERISTICS VCC = 3.3V, TA = 0°C to +70°C Version Parameter Symbol Conditions 100/133 Units Note 1080 mA 1 Operating Current (One bank active) ICC1 Burst Length = 1 tRC ≤ tRC(min) IOL = 0mA Precharge Standby Current in Power Down Mode ICC2P CKE ≤ VIL(max), tCC = 10ns Active Standby Current in Non-Power Down Mode ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns Input signals are changed one time during 20ns ICC4 Io = mA Page burst 4 Banks activated tCCD = 2CK 1,200 mA 1 2,280 mA 2 24 mA Operating Current (Burst mode) Refresh Current ICC5 tRC ≥ tRC(min) Self Refresh Current ICC6 CKE ≤ 0.2V 16 360 mA mA Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. July 2005 Rev. 5 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3DG6435V-D1 -JD1 White Electronic Designs AC TIMING PARAMETERS Speed Grade 100MHz Symbol tCK tCH tCL tIS tIH tAC tOH tOHZ tCCD tCBD tCKE tRP tRAS tRCD tRRD tRC tDQD tDWD tMRD tROH tDQZ tDQM tDPL tDAL tSB tSRX tPDE tCKSTP tREF tRFC 1. 2. 3. 4. 5. 6. Parameter Clock Period Clock High Time Rated @1.5V Clock Low Time Input Setup Times Address/ Command & CKE Data Input Hold Times Address/Command & CKE Data Output Valid From Clock CAS# Latency = 2 or 3, LVTTL levels, Rated @ 50 pF all outputs switching Output Hold From Clock Rated @ 50 pF (1.8 ns @ 0 pf) Output Valid to Z CAS to CAS Delay CAS Bank Delay CKE to Clock Disable RAS Precharge Time RAS Active Time Activate to Command Delay (RAS to CAS Delay) RAS to RAS Bank Activate Delay RAS Cycle Time DQM to Input Data Delay Write Cmd. to Input Data Delay Mode Register set to Active delay Precharge to O/P in High Z DQM to Data in High Z for read DQM to Data mask for write Data-in to PRE Command Period Data-in to ACT (PRE) Command period (Auto precharge) Power Down Mode Entry Self Refresh Exit Time Power Down Exit Set up Time Clock Stop During Self Refresh or Power Down Refresh Period Row Refresh Cycle Time Min 10 3 3 2 2 1 1 Max Speed Grade 133MHz Min 7.5 2.5 2.5 1.5 1.5 0.8 0.8 6.0 (tco = 5.2) 3 3 1 1 1 20 50 20 20 70 0 0 3 9 5.4 (tco = 4.6) 2.7 2.7 1 1 1 20 45 20 15 67.5 0 0 3 CL 2 0 20 5 Max 7 CL 2 0 15 5 1 10 1 200 1 10 1 200 64 80.0 64 75.0 Units ns ns ns ns ns ns ns ns ns ns tCK tCK tCK ns ns ns ns ns tCK tCK tCK tCK tCK tCK ns tCK tCK ns tCK tCK ms ns Notes 1 2 3 4 5 6 Access times to be measured w/input signals of 1 V/ns edge rate, 0.8 V to 2.0 V, tCO is clock to output with no load. CL = CAS Latency Data Masked on the same clock Self refresh Exit is asynchronous, requiring 10 ns to ensure initiation. Self refresh exit is complete in 10 ns + tRC. Timing is asynchronous. If tIS is not met by rising edge of CK then CKE is assumed latched on next cycle. If the clock is stopped during self refresh or power down, 200 clocks are required before CKE is high. July 2005 Rev. 5 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com WED3DG6435V-D1 -JD1 White Electronic Designs ORDERING INFORMATION FOR D1 Ordering Information WED3DG6435V10D1 Speed 100MHz CAS Latency CL=2 Height* 31.75 (1.250”) WED3DG6435V7D1 133MHz CL=2 31.75 (1.250”) WED3DG6435V75D1 133MHz CL=3 31.75 (1.250”) NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option ORDERING INFORMATION FOR JD1 Ordering Information WED3DG6435V10JD1 Speed 100MHz CAS Latency CL=2 Height* 31.75 (1.250”) WED3DG6435V7JD1 133MHz CL=2 31.75 (1.250”) WED3DG6435V75JD1 133MHz CL=3 31.75 (1.250”) NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR D1 AND JD1 67.72 (2.661 Max) 3.81 (0.150) MAX. 2.01 (0.079 Min) 31.75 (1.250) Max 3.99 (0.157) 19.99 (0.787) 23.14 (0.913) 0.99 (0.039) (± 0.004) 32.79 (1.291) 4.60 (0.181) 28.2 (1.112) 1.50 (0.059) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES). July 2005 Rev. 5 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3DG6435V-D1 -JD1 Document Title 256MB – 32Mx64 SDRAM UNBUFFERED Revision History Rev # History Release Date Status Rev 0 Created Data sheet 6-4-03 Advanced Rev 1 1.1 Updated Data sheet 3-3-04 Preliminary Rev 2 2.1 Removed AD1 package option 9-04 Preliminary 9-04 Final 7-05 Final 7-05 Final 2.2 Added JD1 package option Rev 3 3.1 Added timing parameters 3.2 Moved from Preliminary to Final 3.3 Added D1 package option “Not Recommended for New Designs” Rev 4 4.1 Added RoHS compliant notification 4.2 Indicated vendor source options 4.3 Added industrial temperature option Rev 5 July 2005 Rev. 5 5.1 Added “ED” to part number 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com