White Electronic Designs W3DG7232V-D2 PRELIMINARY* 256MB – 32Mx72 SDRAM, REGISTER and SPD, w/PLL FEATURES DESCRIPTION Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock The W3DG7232V is a 32Mx72 synchronous DRAM module which consists of nine 32Meg x 8 SDRAM components in TSOP II package, two 18 bit Drive ICs for input control signal and one 2Kb EEPROM in an 8 pin TSSOP package for Serial Presence Detect which are mounted on a 168 pin DIMM multilayer FR4 Substrate. Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V ± 0.3V Power Supply 168 Pin DIMM JEDEC * This product is under development, is not qualified or characterized and is subject to change without notice. NOTE: Consult factory for availability of: • Lead-Free Products • Vendor source control options • Industrial temperature options PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FRONT VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC WE# DQMB0 February 2005 Rev. 1 PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 BACK DQMB1 CS0# DNU VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC VCC CK0 VSS DNU CS2# DQMB2 DQMB3 DNU VCC NC NC CB2 CB3 VSS DQ16 DQ17 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 FRONT DQ18 DQ19 VCC DQ20 NC *VREF *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS *CK2 NC NC **SDA **SCL VCC PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 BACK VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC CAS# DQMB4 PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 BACK DQMB5 *CS1# RAS# VSS A1 A3 A5 A7 A9 BA0 A11 VCC *CK1 A12 VSS CKE0 *CS3# DQMB6 DQMB7 *A13 VCC NC NC CB6 CB7 VSS DQ48 DQ49 1 PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PIN NAMES BACK DQ50 DQ51 VCC DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS *CK3 NC **SA0 **SA1 **SA2 VCC A0 – A12 BA0-1 DQ0-63 CB0-7 CK0 CKE0 CS0#, CS2# RAS# CAS# WE# DQMB0-7 VCC VSS *VREF REGE SDA SCL SA0-2 DNU NC Address Input (Multiplexed) Select Bank Data Input/Output Check Bit (Data-In/Data-Out) Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable DQMB Power Supply (3.3V) Ground Power Supply for Reference Register Enable Serial Data I/O Serial Clock Address in EEPROM Do Not Use No Connect * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3DG7232V-D2 PRELIMINARY FUNCTIONAL BLOCK DIAGRAM CS0# DQMB0 DQMB4 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQMB1 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQMB5 DQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQM CS DQM CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SDRAM CK0 PLL REGISTER 12pF DQMB6 DQM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CK1-CK3 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 12pF SERIAL PD SCL DQMB7 CS2# DQMB2 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SDA A0 A1 A2 SA0 SA1 SA2 CS DQM DQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VCC SDRAM VSS SDRAM DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS NOTE: DQ wiring may differ than described in this drawing, however DQ/DQMB/CKE/S relationships must be maintained as shown. CS0#/CS2# DQMB0 - DQMB7 BA0 - BA1 A0 - A12 RAS# CAS# CKE0 WE# R E G I S T E R RCS0#/RCS2# RDQMB0 - RDQMB7 RBA0 - RBA1: SDRAMS RA0 - RA12: SDRAMS RRAS#: SDRAMS RCAS#: SDRAMS RCKE0: SDRAMS RWE#: SDRAMS REGE PCK * Wire per Clock Loading Table/Wiring Diagrams NOTE: All resistor values are 10 ohms. February 2005 Rev. 1 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3DG7232V-D2 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 ~ 4.6 V °C TSTG -55 ~ +150 Power Dissipation PD 9 W Short Circuit Current IOS 50 mA Storage Temperature Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS Voltage Referenced to: VSS = 0V, 0°C ≤ TA ≤ 70° Parameter Symbol Min Typ Max Unit Supply Voltage VCC 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 VCCQ+0.3 V Note 1 Input Low Voltage VIL -0.3 — 0.8 V 2 Output High Voltage VOH 2.4 — — V IOH= -2mA Output Low Voltage VOL — — 0.4 V IOL= -2mA Input Leakage Current ILI -10 — 10 μA 3 Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE TA = 25 °C, f = 1MHz, VCC = 3.3V, VREF = 1.4V ± 200mV Parameter Symbol Max Unit Input Capacitance (A0-A12) CIN1 50 pF Input Capacitance (RAS#,CAS#,WE#) CIN2 50 pF Input Capacitance (CKE0) CIN3 50 pF Input Capacitance (CLK0) CIN4 6 pF Input Capacitance (CS0#,CS2#) CIN5 50 pF Input Capacitance (DQMB0-DQMB7) CIN6 13 pF Input Capacitance (BA0-BA1) CIN7 50 pF Data input/output capacitance (DQ0-DQ63) COUT 16 pF Data input/output capacitance (CB0-CB7) COUT1 16 pF February 2005 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3DG7232V-D2 PRELIMINARY OPERATING CURRENT CHARACTERISTICS VCC = 3.3V, 0°C ≤ TA ≤ 70°C Parameters Symbol Conditions Versions 133/100 Units Note Operating Current (One bank active) ICC1 Burst Length = 1 tRC ≥ tRC(min) IOL = 0mA 900 mA 1 Precharge Standby Current in Power Down Mode ICC2P CKE ≤ VIL(max), tCC = 10ns 18 mA 3 Active standby in current non powerdown mode ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are charged one time during 20ns 270 mA 3 Operating current (Burst mode) ICC4 Io = mA Page burst 4 Banks activated tCCD = 2CLK 990 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 1980 mA 2 Self refresh current ICC6 CKE ≤ 0.2V 27 mA 3 Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1 PLL & 2 Drive ICs. February 2005 Rev. 1 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3DG7232V-D2 PRELIMINARY ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS VCC, VCCQ = +3.3V ±0.3V AC CHARACTERISTICS 7 PARAMETER Access timefrom CLK (pos.edge) SYMBOL CL = 3 tAC(3) CL = 2 tAC(2) Address hold time MIN 7.5 MAX MIN 5.4 10 MAX MIN 5.4 5.4 6 MAX UNITS NOTE 6 ns 27 6 ns tAH 0.8 0.8 1 ns Address setup time tAS 1.5 1.5 2 ns CLK high-level width tCH 2.5 2.5 3 ns CLK low-level width tCL 2.5 2.5 3 ns CL = 3 tCK(3) 7 7.5 8 ns 23 CL = 2 tCK(2) 7.5 10 10 ns 23 tCKH 0.8 0.8 1 ns CKE setup time tCKS 1.5 1.5 2 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 1 ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 2 ns Data-in hold time tDH 0.8 0.8 1 ns Data-in setup time tDS 1.5 1.5 2 ns Clock cycle time CKE hold time Data-out high-impedance time CL = 3 tHZ(3) 5.4 5.4 6 ns 10 CL = 2 tHZ(2) 5.4 6 6 ns 10 Data-out low-impedance time tLZ 1 1 1 ns Data-out hold time (load) tOH 2.7 2.7 2.7 ns Data-out hold time (no load) tOHN 1.8 ACTIVE to PRECHARGE command tRAS 37 ACTIVE to ACTIVE command period tRC 60 66 66 ns ACTIVE to READ or WRITE delay tRCD 15 20 20 ns 1.8 120,000 1.8 44 120,000 tREF tRFC 66 66 66 ns PRECHARGE command period tRP 15 20 20 ns ACTIVE bank a to ACTIVE bank b command tRRD 14 tT 0.3 tWR 1 CLK + 7ns 1 CLK + 7.5ns 1 CLK + 7.5ns 14 15 15 ns 25 67 75 80 ns 20 Exit SELF REFRESH to ACTIVE command February 2005 Rev. 1 tXSR 15 1.2 5 64 28 ns AUTOREFRESH period WRITE recovery time 64 ns 120,000 Refresh period Transition time 64 50 15 0.3 1.2 0.3 ms ns 1.2 ns 7 24 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3DG7232V-D2 PRELIMINARY AC FUNCTIONAL CHARACTERISTICS VCC, VCCQ = +3.3V ±0.3V PARAMETER SYMBOL 7 7.5 10 UNITS NOTES READ/WRITE command to READ/WRITE command tCCD 1 1 1 tCK 17 CKE to clock disable or power-down entry mode tCKED 1 1 1 tCK 14 CKE to clock enable or power-down exit setup mode tPED 1 1 1 tCK 14 DQM to input data delay tDQD 0 0 0 tCK 17 DQM to data mask during WRITEs tDQM 0 0 0 tCK 17 DQMto data high-impedance during READs tDQZ 2 2 2 tCK 17 WRITE command to input data delay tDWD 0 0 0 tCK 17 Data-into ACTIVE command tDAL 4 5 5 tCK 15, 21 Data-into PRECHARGE command tDPL 2 2 2 tCK 16, 21 Last data-in to burst STOP command tBDL 1 1 1 tCK 17 Last data-in to new READ/WRITE command tCDL 1 1 1 tCK 17 Lastdata-into PRECHARGE command tRDL 2 2 2 tCK 16, 21 LOADMODEREGISTER command to ACTIVE or REFRESH command tMRD 2 2 2 tCK 26 CL = 3 tROH(3) 3 3 3 tCK 17 CL = 2 tROH(2) 2 2 2 tCK 17 Data-out to high-impedance from PRECHARGE command February 2005 Rev. 1 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3DG7232V-D2 PRELIMINARY Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VCC, VCCQ = +3.3V; TA = 25°C; pin under test biased at 1.4V; f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with mini-mum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VCC and VCCQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner. 9. Outputs measured at 1.5V with equivalent load: Q 50pF 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 10ns for 10, and tCK = 7.5ns for 7 and 7.5. 22. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL under-shoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for 7; 7.5ns for 7.5 and 7.5ns for 10 after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC133, PC100 specify three clocks. 27. tAC for 7/7.5 at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are other-wise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. February 2005 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3DG7232V-D2 PRELIMINARY ORDERING INFORMATION FOR D2 Part Number Speed CAS Latency Height* W3DG7232V10D2 100MHz CL=2 30.48 (1.20”) W3DG7232V7D2 133MHz CL=2 30.48 (1.20”) W3DG7232V75D2 133MHz CL=3 30.48 (1.20”) NOTES: • Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS 3.99 (0.157) (2X) 4.32 (0.170) MAX. 133.48 (5.255) MAX. 3.18 (0.125) (2X) SEE NOTE 1 30.48 (1.20) 17.78 MAX. (0.700) 11.43 (0.450) 15.60 (0.614) 36.83 (1.450) 54.61 (2.150) 6.35 (0.250) 6.35 (0.250) 42.19 (1.661) 3.99 (0.157) MIN. 1.27 ± 0.10 (0.050 ± 0.004) MEASURED AFTER PLATING OVER FINGERS. 115.57 (4.550) ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) February 2005 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3DG7232V-D2 PRELIMINARY Document Title 256MB – 32Mx72 SDRAM, REGISTER and SPD, w/ PLL Revision History Rev # History Release Date Status Rev A History page 10-25-01 Advanced B.1 Changed block diagram 1-15-02 Advanced 7-2004 Preliminary 2-2005 Preliminary Rev B B.2 Changed module height to 1.10 B.3 Add order information Rev 0 0.1 Updated CAP and IDD Specs 0.2 Removed “ED” from part number 0.3 Added new title page 0.4 Moved from Advanced to Preliminary Rev 1 February 2005 Rev. 1 1.1 Added AC specs 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com