White Electronic Designs WED2CG472512V-D2 ADVANCED* 16MB (4x512Kx72) SYNC / SYNC BURST, DUAL KEY DIMM SRAM MODULE FEATURES DESCRIPTION 4x512Kx72 Synchronous, Synchronous Burst Flow-Through Architecture Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1# - BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Asynchronous Output Enable (G#) The WED2CG472512V is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x512Kx72. The Module contains sixteen (16) Synchronous Burst RAM devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The Module Architecture is defined as a Sync/SyncBurst, Flow-Through, with support for either linear or sequential burst. This Module provides high performance, 2-1-1-1 accesses when used in Burst Mode, and when used in Synchronous Only Mode, provides a high performance cost advantage over BiCMOS asynchronous device architectures. Internally Self-Timed Write Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4) Gold Lead Finish 3.3V ± 10% Operation Frequency(s): 100, 83, 67, 50MHz Access Speed(s): tKHQV = 7.5, 9, 10, 12, 15ns Common Data I/O High Capacitance (30pF) Drive, at Rated Access Speed Single Total Array Clock Synchronous Only operations are performed via strapping ADSC# Low, and ADSP#/ADV# High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes. Synchronous/Synchronous Burst operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output Enable. This Module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as Quad Words in both Read and Write Operations. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. White Electronic Designs Corp. reserves the right to change products or specifications without notice. Aug. 2002 Rev. B 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED2CG472512V-D2 ADVANCED FIG. 1 PIN DESCRIPTION PIN CONFIGURATION PIN IDENTIFIER VSS A0 A16 A2 A14 VCC A4 A12 A6 A10 VSS A8 RFU E4 # E2# VSS MODE EM# GW# RFU VCC BW4# BW3# BW8# BW7# ADSC# ADSP# VSS NC VCC DQ0 DQ1 DQ2 DQ3 VSS ZZ1 VCC DQ8 DQ9 DQ10 DQ11 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 VSS A17 A1 A15 A3 VCC A13 A5 A11 A7 VSS A9 A18 E1 # E3# VSS CK VSS G# BWE# VCC BW2# BW1# BW6# BW5# VSS ADV# VSS DQP0 VCC DQ7 DQ6 DQ5 DQ4 VSS DQP1 VCC DQ15 DQ14 DQ13 DQ12 VSS NC VCC DQ16 DQ17 DQ18 DQ19 VSS ZZ2 VCC DQ24 DQ25 DQ26 DQ27 VSS NC VCC DQ32 DQ33 DQ34 DQ35 VSS ZZ3 VCC DQ40 DQ41 DQ42 DQ43 VSS NC VCC DQ48 DQ49 DQ50 DQ51 VSS ZZ4 VCC DQ56 DQ57 DQ58 DQ59 VSS 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQP2 VCC DQ23 DQ22 DQ21 DQ20 VSS DQP3 VCC DQ31 DQ30 DQ29 DQ28 VSS DQP4 VCC DQ39 DQ38 DQ37 DQ36 VSS DQP5 VCC DQ47 DQ46 DQ45 DQ44 VSS DQP6 VCC DQ55 DQ54 DQ53 DQ52 VSS DQP7 VCC DQ63 DQ62 DQ61 DQ60 VSS DQ0 - DQ63 Input/Output Bus DQP0 - DQP7 Parity Bits A0 - A18 Address Bus EM# Module Enable E1#, E2#, E3#, E4# Synchronous Bank Enables BWE# Byte Write Mode Enable BW1# - BW8# Byte Write Enables CK Array Clock GW# Synchronous Global Write Enable G# Asynchronous Output Enable ZZ1, ZZ2, ZZ3, ZZ4 Bank Sleep Mode Enables Vcc 3.3V Power Supply Vss Gnd White Electronic Designs Corp. reserves the right to change products or specifications without notice. Aug. 2002 Rev. B 2 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs WED2CG472512V-D2 ADVANCED FIG. 2 FUNCTIONAL BLOCK DIAGRAM ADDR BW8# BW7# BW6# BW5# BW4# BW3# BW2# BW1# BWE# E4# E3# E2# E1# BW8# BW7# BW6# BW5# BW4# BW3# BW2# BW1# BWE# E4 # E3# E2# E1# ADV# ADV# BW4# BW3# BW2# BW1# BWE# BW4# BW3# BW2# BW1# BWE# 512K x 18 SBFT ADV# BW4# BW3# BW2# BW1# BWE# 512K x 18 SBFT E2 ZZ2 E1 # ZZ1 512K x 18 SBFT GW# G# ADSP# ADSC# 512K x 18 SBFT 512K x 18 SBFT E4 ZZ4 GW# G# ADSP# ADSC# BW4# BW3# BW2# BW1# BWE# 512K x 18 SBFT E3 ZZ3 GW# G# ADSP# ADSC# ADV# 512K x 18 SBFT GW# G# ADSP# ADSC# 512K x 18 SBFT Data (DQ) GW# G# MODE ADSP# ADSC# ADV# BW8# BW7# BW6# BW5# BWE# E1 # ZZ1 GW# G# ZZ1 ZZ2 512K x 18 SBFT BW8# BW7# BW6# BW5# BWE# E2# ZZ2 ZZ3 ADSP# ADSC# ZZ4 ADV# 512K x 18 SBFT BW8# BW7# BW6# BW5# BWE# E3# ZZ3 512K x 18 SBFT GW# G# ADSP# ADSC# 512K x 18 SBFT BW8# BW7# BW6# BW5# BWE# E4# ZZ4 GW# G# ADSP# ADSC# 512K x 18 SBFT ADV# 512K x 18 SBFT ADV# 512K x 18 SBFT GW# G# ADSP# ADSC# 512K x 18 SBFT ADV# CK U1 -U8 EQUAL LENGTH NET ROUTES White Electronic Designs Corp. reserves the right to change products or specifications without notice. Aug. 2002 Rev. B 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs WED2CG472512V-D2 ADVANCED SYNC BURST – TRUTH TABLE Operation Deselected Cycle, Power Down; Bank 1 Deselected Cycle, Power Down; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst, Bank 2 Read Cycle, Begin Burst; Bank 2 Write Cycle, Begin Burst; Bank 1 Write Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 2 E1# H X L L H H L H L L H H X X H H H H H H X H H H X X H H H H H H X H H H E 2# X H H H L L H L H H L L H H X X H H H H H H X H H H X X H H H H H H X H E3# E4# * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ADSP# ADSC# X L X L L X L X L X L X H L H L H L H L H L H L X H X H X H X H X H X H X H X H H H X H H H X H H H H H H H H H X H X H X H X H H H X H H H X H ADV# X X X X X X X X X X X X L L L L L L L L L L L L H H H H H H H H H H H H GW# X X X X X X L L H H H H H H H H H H H H L L L L H H H H H H H H L L L L G# X X L H L H X X L H L H L H L H L H L H X X X X L H L H L H L H X X X X CK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z D D D D Q High-Z Q High-Z Q High-Z Q High-Z D D D D Addr. Used None None External External External External External External External External External External Next Next Next Next Next Next Next Next Next Next Next Next Current Current Current Current Current Current Current Current Current Current Current Current Note A: All truth Table Functions Repeat for Bank 3 (E3#) and Bank 4 (E4#). SYNCHRONOUS ONLY – TRUTH TABLE Operation Synchronous Write - Bank 1 E1# L E2# H Synchronous Read - Bank 1 L H Synchronous Write - Bank 2 H L Synchronous Read - Bank 2 H L Synchronous Write - Bank 3 H H E3# H E4# H GW# L H H H H H L H H H L H L G# H ZZ L CK L L H L L L H L Synchronous Read - Bank 3 H H L H H L L Synchronous Write - Bank 4 H H H L L H L Synchronous Read - Bank 4 H H H L H L L Snooze Mode X X X X X X H X DQ High-Z High-Z High-Z High-Z High-Z White Electronic Designs Corp. reserves the right to change products or specifications without notice. Aug. 2002 Rev. B 4 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs WED2CG472512V-D2 ADVANCED ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Relative to Vss RECOMMENDED DC OPERATING CONDITIONS -0.3V to +4.6V VIN -0.3V to Vcc +0.5V Storage Temperature -55°C to + 125°C Operating Temperature (Commercial) 0°C to +70°C Operating Temperature (Industrial) -40°C to +85°C Short Circuit Output Current 100mA Parameter Sym Min Typ Max Units Supply Voltage Supply Voltage Vcc Vss 3.3 0 3.3 0 3.6 0 V V Input High Input Low Input Leakage Output Leakage VIH VIL ILI ILo 2.0 -0.3 -2 -2 3.0 0 1 1 Vcc+0.3 0.3 2 2 V V mA mA *Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS READ CYCLE Max Description Sym Typ 8.5 10 12 15 Units Power Supply Current Icc1 2.0 2.9 2.7 2.7 2.5 A Power Supply Current Device Selected, No Operation Icc 875 1.8 1.8 1.3 1.3 A IccZZ 270 350 350 350 350 mA Snooze Mode CMOS Standby Icc3 500 700 700 700 700 mA Clock Running-Deselect IccK 900 1.1 1.1 1.0 1.0 A AC TEST LOAD AC TEST CONDITIONS Input Pulse Levels DQ Output Z0 Z0==50Ω 50Ω Input and Output Timing Ref. Output Test Equivalencies Vss to 3.0V 1.25V See figure at left RL = 50Ω VL = 1.25V OUTPUT TEST EQUIVALENCIES White Electronic Designs Corp. reserves the right to change products or specifications without notice. Aug. 2002 Rev. B 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs WED2CG472512V-D2 ADVANCED READ CYCLE TIMING PARAMETERS 9ns Description Sym Min 10ns Max Min 12ns Max Min 15ns Max Min Max Units 50 MHz Frequency fMAX Clock Cycle Time tKHKH 10 12 15 20 ns Clock High Time tKHKL 4 5 5 6 ns Clock Low Time tKLKH 4 5 5 6 ns 100 83 67 Clock to Output Valid tKHQV Clock to Output Invalid tKHQX1 3 3 3 3 ns Clock to Output Low-Z tKHQX 4 4 4 4 ns Output Enable to Output Valid tGLQV Output Enable to Output Low-Z tGLQX 9 10 4 12 5 0 0 5 0 4 15 5 0 5 ns ns ns Output Enable to Output High-Z tGHQZ Address Setup tAVKH 2.5 2.5 2.5 5 2.5 5 ns ns Bank Enable Setup tEVKH 2.5 2.5 2.5 2.5 ns Address Hold tKHAX 1.0 1.0 1.0 1.0 ns Bank Enable Hold tKHEX 1.0 1.0 1.0 1.0 ns WRITE CYCLE TIMING PARAMETERS 9ns Description Sym Min 10ns Max Min 100 12ns Max Min 83 15ns Max Min 67 Max Units 50 MHz Frequency fMAX Clock Cycle Time tKHKH 12 12 15 20 ns Clock High Time tKHKL 4 5 5 6 ns Clock Low Time tKLKH 4 5 5 6 ns Address Setup tAVKH 2.5 2.5 2.5 2.5 ns Address Hold tKHAX 1.0 1.0 1.0 1.0 ns Bank Enable Setup tEVKH 2.5 2.5 2.5 2.5 ns Bank Enable Hold tKHEX 1.0 1.0 1.0 1.0 ns Global Write Enable Setup tWVKH 2.5 2.5 2.5 2.5 ns Global Write Enable Hold tKHWX 1.0 1.0 1.0 1.0 ns Data Setup tDVKH 2.5 2.5 2.5 2.5 ns Data Hold tKHDX 1.0 1.0 1.0 1.0 ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. Aug. 2002 Rev. B 6 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs WED2CG472512V-D2 ADVANCED FIG. 3 SYNCHRONOUS ONLY READ CYCLE tKHKH tKLKH tKHKL CK tAVKH Ex# ADDR G# Addr 1 Addr 1 Addr 2 tKHAX tKHQV tGLQV tGLQX GW# tKHQX DQ0-63 Q(Addr 1) Q(Addr 1) tKHQZ tKHQX1 Read Cycle FIG. 4 Q(Addr 2) Back to Back Read SYNC-BURST READ CYCLE tKHKH tKHKL tKLKH CK tSPVKH tKHSPX ADSP# tSCVKH tKHSCX ADSC# tAVKH tKHAX ADDR BWx#, GW# tEVKH tKHEX CE# tAVVKH tKHAVX ADV# tGHQX tKHQV G# tGLQV tGLQX tGHQZ DQ tKHQX tKHQX Burst Read Cycle Read Cycle White Electronic Designs Corp. reserves the right to change products or specifications without notice. Aug. 2002 Rev. B 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs WED2CG472512V-D2 ADVANCED FIG. 5 SYNC (NON-BURST) WRITE CYCLE tKHKH tKHKL tAVKH tKHAX tKLKH CK Ex# ADDR Addr 1 Addr 1 tGWLKH Addr 2 tKHGWH GW# G# tKHGH tKHDX tDVKH tGHKH Back to Back Writes Write Cycle White Electronic Designs Corp. reserves the right to change products or specifications without notice. Aug. 2002 Rev. B 8 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs WED2CG472512V-D2 ADVANCED FIG. 6 SYNC-BURST WRITE CYCLE tKHKH tKHKL tKLKH CK ADSP# ADSC# tAVKH tKHAX ADDR BWx#, GW# tEVKH tKHEX CE# tAVVKH tKHAVX ADV# G# tDVKH tKHQX DQ tKHQX Early Write Cycle Burst - Late Write- Cycle White Electronic Designs Corp. reserves the right to change products or specifications without notice. Aug. 2002 Rev. B 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com White Electronic Designs WED2CG472512V-D2 ADVANCED PACKAGE DIMENSION: 168 GOLD LEAD DIMM 0.195 MAX. 5.255 MAX. 0.157 (2x) 195 1.500 MAX. 0.700 P1 0.078 (2X) 0.450 0.575 0.050 TYP. 0.250 1.450 0.350 0.925 0.225 MIN. 2.150 0.125 1.700 ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION Part Number Configuration Voltage (V) Data Package Access Time WED2CG472512V9D2 4 x 512K x 72 3.3VDC 9ns 168 Gold Lead DIMM WED2CG472512V10D2 4 x 512K x 72 3.3VDC 10ns 168 Gold Lead DIMM WED2CG472512V12D2 4 x 512K x 72 3.3VDC 12ns 168 Gold Lead DIMM WED2CG472512V15D2 4 x 512K x 72 3.3VDC 15ns 168 Gold Lead DIMM White Electronic Designs Corp. reserves the right to change products or specifications without notice. Aug. 2002 Rev. B 10 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com