EDI2DL32256V 256Kx32 Synchronous Pipline Burst SRAM 3.3V FEATURES DESCRIPTION ■ tKHQV times of 3.5, 3.8 and 4.0ns The EDI2DL32256VxxBC is a 3.3V, 256Kx32 Synchronous Pipeline Burst SRAM constructed with two 256Kx16 die mounted on a multi-layer laminate substrate. The device is packaged in a 119 lead, 14mm by 22mm, BGA. It is available with clock speeds of166, 150 and 133 MHz. The device is a Pipeline Burst SRAM, allowing the user to develop a fast external memory for Texas Instruments’ “C6x”. In Burst Mode data from the first memory location is available in three clock cycles, while the subsequent data is available in one clock cycle (3/1/1/1). Subsequent burst addresses are generated by the TMS320C6x DSP. Individual address locations can also be read, allowing one memory access in 3 clock cycles. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, chip enable (CE\), burst control input (ADSC\), byte write enables (BW0\ to BW3\) and Write Enable (BWE\). ■ 166, 150 and 133 MHz clock speed ■ DSP Memory Solution • Texas Instruments’ TMS320C6201 • Texas Instruments’ TMS320C67x ■ Package: • 119 pin BGA, JEDEC MO-163 ■ 3.3V Operating Supply Voltage ■ 3.5ns Output Enable access time ■ Single Write Control and Output Enable Lines ■ Single Chip Enable Line ■ 56% space savings vs. monolithic TQFPs ■ Multiple VCC and VSS pins Asynchronous inputs include the output enable (OE\), burst mode control (MODE), and sleep mode control (ZZ). The data outputs (DQ), enabled by OE\, are also asynchronous. ■ Reduced inductance and capacitance Address lines and the chip enable are registered with the address status controller (ADSC\) input pin. FIG. 1 PIN CONFIGURATION 1 2 3 4 5 BLOCK DIAGRAM 6 7 A VDD A A NC A A VDD A B NC NC A ADSC\ A A NC B C NC A A VDD A A NC C D DQ16 NC VSS NC VSS NC DQ8 D E DQ18 DQ17 VSS CE\ VSS DQ9 DQ10 E F VDD DQ19 VSS OE\ VSS DQ11 VDD F G DQ21 DQ20 BE2\ NC BE1\ DQ12 DQ13 G H DQ23 DQ22 VSS NC VSS DQ14 DQ15 H J VDD VDD NC VDD NC VDD VDD J K DQ31 DQ30 VSS CLK VSS DQ6 DQ7 K L DQ29 DQ28 BE3\ NC BE0\ DQ4 DQ5 L M VDD DQ27 VSS BWE\ VSS DQ3 VDD M N DQ26 DQ25 VSS A1 VSS DQ1 DQ2 N P DQ24 NC VSS A0 VSS NC DQ0 P R NC A MODE VDD NC A NC R T NC NC A A A NC ZZ T U VDD NC NC NC NC NC VDD U 1 2 3 4 5 6 7 November 2000, Rev. 1 ECO #13417 A0-17 CLK ADSC\ OE\ BWE\ CE\ MODE ZZ BE0\ BE1\ 256K X 16 SSRAM BE2\ BE3\ 256K X 16 SSRAM 1 DQ0-7 DQ8-15 DQ16-23 DQ24-31 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI2DL32256V PIN DESCRIPTIONS Pin Symbol Type Various A0-17 L5,G5 G3,L3 M4 BE0\,BE1\, BE2\,BE3\ BWE\ K4 CLK E4 CE\ F4 B4 OE\ ADSC\ R3 MODE Input Synchronous Input Synchronous Input Synchronous Input Synchronous Input Synchronous Input Input Synchronous Input Description T7 ZZ Various Various Various DQ0-31 Vcc Vss Input Synchronous Input/Output Supply Ground Addresses: These inputs are registered and must meet setup and hold times around the rising edge of CLK. Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ BE2\, BE3\ cycle. BE0\ controls DQ0-7. BE1\ controls DQ8-15. BE2\ controls DQ16-23. BE3\ controls DQ24-31 Byte Write Enable: This active LOW input gates byte write operations and must meet the setup and hold times around the rising edge of CLK. Clock:This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clockís rising edge. Chip Enable: This active LOW inputs is used to enable the device. Output Enable: This active LOW asynchronous input enables the data output drivers Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Static Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (no connect) Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31 Core power supply: +3.3V -5%/+5% Ground TRUTH TABLE Operation Deselected Cycle, Power Down WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None External External External Current Current Current Current Current Current CE\ H L L L X X H H X H ADSC\ L L L L H H H H H H WRITE\ X L H H H H H H L L OE\ X X L H L H L H X X DQ High-Z D Q High-Z Q High-Z Q High-Z D D NOTE: 1. X means ìdonít careî, H means logic HIGH. L means logic LOW. 2a.WRITE\ = L, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals LOW 2b.WRITE\ = H, means [BE0\*BE1\*BE2\*BE3\]*BWE\ equals HIGH 3. All inputs except OE\ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 4. Suspending burst generates wait cycle 5. For a write operation following a read operation, OE\ must be HIGH before the input data required setup time plus High-Z time for OE\ and staying HIGH though out the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 2 November 2000, Rev. 1 ECO #13417 EDI2DL32256V ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss RECOMMENDED OPERATING CONDITIONS -0.5V to 4.6V VIN Symbol Min Max -0.5V to Vcc+0.5V Input High Voltage VIH 2 Vcc+0.3 V -55°C to +110°C Input Low Voltage VIL -0.3 0.7 V Supply Voltage Vcc 3.135 3.465 V Storage Temperature Junction Temperature +110°C Power Dissipation 3 Watts Short Circuit Output Current (per I/O) Description 20 mA CAPACITANCE (f = 1MHz, VIN = VCC or VSS) * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Address Lines Data Lines Control Lines PARTIAL TRUTH TABLE Function BWE\ BE0\ BE1\ BE2\ READ H X X X X WRITE one Byte (DQ0-7) L L H H H WRITE all Bytes L L L L L Unit Symbol Max Unit CA TBD pF CD/Q TBD pF CC TBD pF BE\3 DC ELECTRICAL CHARACTERISTICS (f = 1MHz, VIN = VCC or Vss) Parameter Symbol Power Supply Current: Operating I CC1 CMOS Standby I SB2 TTL Standby I SB3 TTL Standby I SB4 Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage IL I IL O VOH VOL Conditions Min Device Selected; all inputs ≤ V IL or ≥ VIH; cycle time ≥ tKC MIN; V CC = MAX; outputs open Device deselected; V CC = MAX; all inputs ≤ VSS +0.2 or ≥ V CC -0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs ≤ V IL or ≥ VIH; all inputs static; V CC = MAX; CLK frequency = 0 Device deselected; all inputs ≤ V IL or ≥ VIH; VCC = MAX; CLK cycle time ≥ t CK MIN 0V < VIN < V CC Output(s) disabled, 0V ≤ V OUT ≤ V CC I OH = -2.0mA I OL = 2.0mA AC TEST CIRCUIT Units 850 mA 20 mA 40 mA 40 mA 2 2 µA µA V V -2 -2 2.4 0.7 AC TEST CONDITIONS Parameter Output Max Z0 Z0==50Ω 50Ω Input Pulse Levels Input Rise and Fall Times (max) Input and Output Timing Levels 50Ω Output Load I/O Unit VSS to 2.5 V 1.8 ns 1.25 V See figure, at left Vt = 1.5V 1.25V AC Output Load Equivalent November 2000, Rev. 1 ECO #13417 3 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI2DL32256V AC ELECTRICAL CHARACTERISTICS Description Symbol Min 3.5ns Max Min 3.8ns Max Min 4.0ns Max Units Clock Clock cycle time tKHKH 6 6.7 7.5 Clock HIGH time tKHKL 2.4 2.6 2.8 Clock LOW time tKLKH 2.4 2.6 2.8 Output Times Clock to output valid tKHQV Clock to output in Low-Z tKHQX 0 3.5 Clock to output in High-Z tKHQZ 1.5 OE to output valid tOELQV OE to output in Low-Z tOELQX OE to output in High-Z tOEHQZ 3.8 0 6 1.5 3.5 0 4.0 0 6.7 1.5 3.5 0 3.5 7.5 3.8 0 3.5 3.8 Setup Times Address Status Controller valid to Clock tSCVKH 1.5 1.5 1.5 Address valid to Clock tAVKH 1.5 1.5 1.5 Chip Enable valid to Clock tEVKH 1.5 1.5 1.5 Write Enable (BWE\) valid to Clock tWLKH 1.5 1.5 1.5 Data Valid to Clock tDVKH 1.5 1.5 1.5 Address Status Controller Hold time tKHSCX 0.5 0.5 0.5 Address Hold time tKHAX 0.5 0.5 0.5 Chip Enable Hold time tKHEX 0.5 0.5 0.5 Write Enable (BWE\) Hold time tKHWX 0.5 0.5 0.5 Data Hold time tKHDX 0.5 0.5 0.5 Hold Times White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 4 November 2000, Rev. 1 ECO #13417 EDI2DL32256V FIG. 2 READ TIMING tKHKL tKLKH tKHKH CLK tSC VKH tKHSC X ADSC\ tEVKH CE\ tKHEX tAVKH ADDR A1 A2 A3 A5 A4 tKHAX OE\ tOELQ X tOEHQZ tOELQ V WRITE\ tKHQ Z tKHQ V tKHQ X DQ November 2000, Rev. 1 ECO #13417 Q(A1) Q(A2) 5 Q(A3) Q(A4) Q(A5) White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI2DL32256V FIG. 3 WRITE TIMING tKHK H t KHK L t KLKH CLK t SC VKH t KHSCX ADSC\ t EVKH CE\ t KHEX t AVKH ADDR A2 A1 A3 A4 A5 t KHAX OE\ KHG WX t WVKH t KHWX WRITE\ t DVK H DQ D(A1) White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com t KHDX D(A2) 6 D(A3) D (A4) D(A5) November 2000, Rev. 1 ECO #13417 EDI2DL32256V ORDERING INFORMATION Commercial Temperature Range (0°C to +70°C) Part Number tKQ (ns) Clock Frequency (MHz) EDI2DL32256V35BC 3.5 166 EDI2DL32256V38BC 3.8 150 TBD EDI2DL32256V40BC 4.0 133 TBD PACKAGE DESCRIPTION: Industrial Temperature Range (-40°C to +85°C) Part Number tKQ (ns) Clock Frequency (MHz) EDI2DL32256V40BI 4.0 133 Package No. TBD Package No. TBD 119 LEAD BGA JEDEC MO-163 0.110 MAX 0.300 BSC 0.551 BSC R 0.062 MAX (4x) A B PIN 1 INDEX C D E F G 0.800 BSC 0.050 TYP H 0.866 BSC J K L M N P R T U 0.028 MAX 0.050 TYP ALL DIMENSIONS ARE IN INCHES November 2000, Rev. 1 ECO #13417 7 White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com EDI2DL32256V FIG. 5 INTERFACING THE TEXAS INSTRUMENTS TMS320C6201 WITH THE EDI2DL32256V (256Kx32 SSRAM) EA0-22 A0-17 (NOTE 1) CE2\ CE1\ CE0\ CE\ (NOTE 4) MODE NC, Vss, Vcc ZZ (NOTE 2) BE3\ BE2\ EDI2DL32256V BE1\ BE0\ OE\ ADSC\ ADV\ GW\ (NOTE 3) CLK BE3\ Texas Instruments BE2\ 1\ TMS320C6201 BE BE0\ SSOE\ SSADS\ SSADV\ SSWE\ CLKOUT1 CLKOUT2 ED0-31 DQ0-31 NOTES: 1. Either CE0 or CE2 can be used to enable the device. 2. When the ZZ pin is asserted HIGH, the device will be in CMOS standby mode regardless of the state of any other pins. While in standby mode the device will take one complete Clock cycle to become active again after a LOW is asserted on the ZZ pin. One possible option for the designer concerned about power is to tie the ZZ signal to the chip enable they are using for the device. Any time the chip is disabled (by driving the chip enable pin HIGH) the device will go into standby mode. Standby mode can also be achieved by tying the ZZ pin LOW or allowing it to float and meeting all the signal conditions specified in the data sheet. 3. Use CLKOUT1 for running the memory at the same clock speed as the C6x. Use CLKOUT2 for running the SBSRAM at one half the clock rate of the C6x. 4. The MODE pin can be tied to Vss (Linear Burst), tied to Vcc (Interleaved Burst) or allowed to float (Interleaved Burst). White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com 8 November 2000, Rev. 1 ECO #13417