SIMTEK UL635H256

Obsolete - Not Recommended for New Designs
UL635H256
Low Voltage PowerStore 32K x 8 nvSRAM
Features
Description
•
The UL635H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disabled.
The UL635H256 is a fast static
RAM (35 and 45 ns), with a nonvolatile electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resides in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in system
capacitance. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on powerup.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High-performance CMOS nonvolatile static RAM 32768 x 8 bits
35 and 45 ns Access Times
15 and 20 ns Output Enable
Access Times
ICC = 8 mA typ. at 200 ns Cycle
Time
Automatic STORE to EEPROM
on Power Down using system
capacitance
Software initiated STORE
Automatic STORE Timing
106 STORE cycles to EEPROM
100 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
EEPROM
Wide voltage range: 2.7 ... 3.6 V
(3.0 ... 3.6 V for 35 ns type)
Operating temperature range:
0 to 70 °C
-40 to 85 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
RoHS compliance and Pb- free
Package:SOP28 (330 mil)
Pin Description
Pin Configuration
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SOP
Top View
March 31, 2006
28
27
26
25
24
23
22
21
20
19
18
17
16
15
The UL635H256 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initiated under user control via a software sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initiated by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
G
A11
A9
A8
A13
W
n. c.
VCC
n. c.
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
n.c.
Top View
STK Control #ML0059
1
Signal Name
Signal Description
A0 - A14
Address Inputs
DQ0 - DQ7
Data In/Out
E
Chip Enable
G
Output Enable
W
VCC
Write Enable
Power Supply Voltage
VSS
Ground
Rev 1.0
UL635H256
Block Diagram
EEPROM Array
512 x (64 x 8)
A5
A6
A7
A8
A9
A11
A12
A13
A14
VCC
VSS
Row Decoder
STORE
RECALL
SRAM
Array
Power
Control
VCC
512 Rows x
64 x 8 Columns
Store/
Recall
Control
DQ0
DQ1
Column I/O
Input Buffers
DQ2
DQ3
DQ4
DQ5
DQ6
Software
Detect
Column Decoder
G
A0 A1 A2 A3 A4 A10
DQ7
A0 - A13
E
W
Truth Table for SRAM Operations
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
H
*
*
High-Z
Internal Read
L
H
H
High-Z
Read
L
H
L
Data Outputs Low-Z
Write
L
L
*
Data Inputs High-Z
* H or L
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
VCC
-0.5
4.6
V
Input Voltage
VI
-0.3
VCC+0.5
V
Output Voltage
VO
-0.3
VCC+0.5
V
Power Dissipation
PD
1
W
Power Supply Voltage
Operating Temperature
Storage Temperature
a:
C-Type
K-Type
Ta
0
-40
70
85
°C
°C
Tstg
-65
150
°C
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
STK Control #ML0059
2
Rev 1.0
March 31, 2006
UL635H256
Recommended
Operating Conditions
Symbol
Power Supply Voltage
VCC
Input Low Voltage
VIL
Input High Voltage
VIH
DC Characteristics
Symbol
Conditions
Min.
Max.
Unit
tc = 35 ns
tc = 45 ns
3.0
2.7
3.6
3.6
V
V
-2 V at Pulse Width
10 ns permitted
-0.3
0.8
V
2.2
VCC+0.3
V
C-Type
K-Type
Conditions
Unit
Min.
Operating Supply Currentb
ICC1
Max.
Min.
Max.
VCC
VIL
VIH
= 3.6 V
= 0.8 V
= 2.2 V
tc
tc
= 35 ns
= 45 ns
45
35
47
37
mA
mA
Average Supply Current duringc
STORE
ICC2
VCC
E
W
VIL
VIH
= 3.6 V
≤ 0.2 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
3
4
mA
Operating Supply Currentb
at tcR = 200 ns
(Cycling CMOS Input Levels)
ICC3
VCC
W
VIL
VIH
= 3.6 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
10
11
mA
Average Supply Current duringc
PowerStore Cycle
ICC4
VCC
VIL
VIH
= VCCmin
= 0.2 V
≥ VCC-0.2 V
2
2
mA
ICC(SB)1
VCC
E
= 3.6 V
= VIH
tc
tc
= 35 ns
= 45 ns
11
9
12
10
mA
mA
VCC
E
VIL
VIH
= 3.6 V
≥ VCC-0.2 V
≤ 0.2 V
≥ VCC-0.2 V
1
1
mA
Standby Supply Currentd
(Cycling TTL Input Levels)
Standby Supply Curentd
(Stable CMOS Input Levels)
ICC(SB)
b: ICC1 and ICC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
The current ICC1 is measured for WRITE/READ - ratio of 1/2.
c: ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles.
d: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION
table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
March 31, 2006
STK Control #ML0059
3
Rev 1.0
UL635H256
C-Type
DC Characteristics
Symbol
Unit
Min.
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
IOL
= VCCmin
=-2 mA
= 2 mA
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VOL
= VCCmin
= 2.4 V
= 0.4 V
VCC
= 3.6 V
VIH
VIL
= 3.6 V
= 0V
VCC
= 3.6 V
VOH
VOL
= 3.6 V
= 0V
Input Leakage Current
High
Low
IIH
IIL
Output Leakage Current
High at Three-State- Output
Low at Three-State- Output
K-Type
Conditions
IOHZ
IOLZ
Max.
Min.
2.4
Max.
2.4
0.4
0.4
-2
2
-2
mA
mA
1
μA
μA
2
1
-1
-1
1
1
-1
V
V
-1
μA
μA
SRAM Memory Operations
No.
e:
f:
g:
h:
Symbol
Switching Characteristics
Read Cycle
35
45
Unit
Alt.
IEC
Min.
35
Max.
Min.
Max.
1
Read Cycle Timef
tAVAV
tcR
2
Address Access Time to Data Validg
tAVQV
ta(A)
35
45
ns
3
Chip Enable Access Time to Data Valid
tELQV
ta(E)
35
45
ns
4
Output Enable Access Time to Data
Valid
tGLQV
ta(G)
15
20
ns
5
E HIGH to Output in High-Zh
tEHQZ
tdis(E)
13
15
ns
6
G HIGH to Output in High-Zh
tGHQZ
tdis(G)
13
15
ns
7
E LOW to Output in Low-Z
tELQX
ten(E)
5
5
ns
8
G LOW to Output in Low-Z
tGLQX
ten(G)
0
0
ns
9
Output Hold Time after Address Change
tAXQX
tv(A)
3
3
ns
10 Chip Enable to Power Activee
tELICCH
tPU
0
0
ns
11 Chip Disable to Power Standbyd, e
tEHICCL
tPD
45
35
ns
45
ns
Parameter guaranteed but not tested.
Device is continuously selected with E and G both Low.
Address valid prior to or coincident with E transition LOW.
Measured ± 200 mV from steady state output voltage.
STK Control #ML0059
4
Rev 1.0
March 31, 2006
UL635H256
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
tcR (1)
Ai
Address Valid
ta(A) (2)
DQi
Output Data Valid
Previous Data Valid
Output
tv(A) (9)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
tcR (1)
Ai
Address Valid
ta(A) (2)
ta(E) (3)
E
(11)
tdis(E) (5)
ten(E) (7)
G
ta(G) (4)
tdis(G) (6)
ten(G) (8)
DQi
High Impedance
Output
Output Data Valid
tPU (10)
ACTIVE
ICC
No.
tPD
STANDBY
Switching Characteristics
Write Cycle
Symbol
35
45
Unit
Alt. #1 Alt. #2
12 Write Cycle Time
tAVAV
13 Write Pulse Width
tWLWH
14 Write Pulse Width Setup Time
IEC
Min.
tcW
35
45
ns
tw(W)
25
30
ns
tWLEH
tsu(W)
25
30
ns
tAVAV
Max.
Min.
Max.
15 Address Setup Time
tAVWL
tAVEL
tsu(A)
0
0
ns
16 Address Valid to End of Write
tAVWH
tAVEH
tsu(A-WH)
25
30
ns
17 Chip Enable Setup Time
tELWH
tsu(E)
25
30
ns
tELEH
tw(E)
25
30
ns
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
tDVWH
tDVEH
tsu(D)
12
15
ns
20 Data Hold Time after End of Write
tWHDX
tEHDX
th(D)
0
0
ns
21 Address Hold after End of Write
tWHAX
tEHAX
th(A)
0
0
ns
22 W LOW to Output in High-Zh, i
tWLQZ
tdis(W)
23 W HIGH to Output in Low-Z
tWHQX
ten(W)
March 31, 2006
STK Control #ML0059
5
13
5
15
5
Rev 1.0
ns
ns
UL635H256
Write Cycle #1: W-controlledj
tcW
Ai
(12)
Address Valid
tsu(E) (17)
th(A) (21)
E
W
tsu(A-WH) (16)
tw(W) (13)
tsu(A)
(15)
Input Data Valid
Input
DQi
Output
th(D) (20)
tsu(D) (19)
DQi
tdis(W)
(22)
Previous Data Valid
ten(W) (23)
High Impedance
Write Cycle #2: E-controlledj
tcW (12)
Ai
E
Address Valid
tsu(A) (15)
th(A)
tw(E) (18)
(21)
tsu(W) (14)
W
tsu(D) (19)
DQi
th(D) (20)
Input Data Valid
Input
DQi
High Impedance
Output
undefined
i:
j:
L- to H-level
H- to L-level
If W is low and when E goes low, the outputs remain in the high impedance state.
E or W must be VIH during address transition.
STK Control #ML0059
6
Rev 1.0
March 31, 2006
UL635H256
Nonvolatile Memory Operations
Mode Selection
E
W
A13 - A0
(hex)
Mode
I/O
Power
H
X
X
Not Selected
Output High Z
Standby
L
H
X
Read SRAM
Output Data
Active
L
L
X
Write SRAM
Input Data
Active
L
H
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
L
H
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
Notes
m
k: The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.
l: While there are 15 addresses on the UL635H256, only the lower 14 are used to control software modes.
Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G ≤ VIL.
No.
24 Power Up RECALL Durationn
25 STORE Cycle Durationf, e
26
Conditions
Alt.
the power supply decay
rate has to be smaller
than 10 Vs-1 after the
start of the STORE
operation
tPDSTORE
tDELAY
500
VSWITCH
2.4
tRESTORE starts from the time VCC rises above VSWITCH.
March 31, 2006
Min.
STK Control #ML0059
Max.
Unit
650
μs
10
ms
IEC
tRESTORE
Time allowed to Complete SRAM
Cyclef
Low Voltage Trigger Level
n:
Symbol
PowerStore
Power Up RECALL
7
Rev 1.0
ns
2.7
V
UL635H256
PowerStore and automatic Power Up RECALL
VCC
3.0 V
VSWITCH
t
PowerStore
tPDSTOREp
Power Up
RECALL
W
(24)
(24)
tRESTORE
tRESTORE
tDELAYp
DQi
BROWN OUT
PowerStore
POWER UP BROWN OUT
RECALL
NO STORE
(NO SRAM WRITES)
No.
o:
p:
q:
r:
s:
t:
Software Controlled STORE/RECALL
Cyclek, o
35
Symbol
45
Unit
Alt.
IEC
Min.
27 STORE/RECALL Initiation Time
tAVAV
tcR
35
28 Chip Enable to Output Inactivep
tELQZ
tdis(E)SR
600
600
ns
29 STORE Cycle Timeq
tELQXS
td(E)S
10
10
ms
30 RECALL Cycle Timer
tELQXR
td(E)R
20
20
μs
31 Address Setup to Chip Enables
tAVELN
tsu(A)SR
0
0
ns
32 Chip Enable Pulse Widths, t
tELEHN
tw(E)SR
25
30
ns
33 Chip Disable to Address Changes
tEHAXN
th(A)SR
0
0
ns
Max.
Min.
Max.
45
ns
The software sequence is clocked with E controlled READs.
Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit).
An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below
VSWITCH once it has been exceeded for the RECALL to function properly.
Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
STK Control #ML0059
8
Rev 1.0
March 31, 2006
UL635H256
Software Controlled STORE/RECALL Cyclet, u, v (E = HIGH after STORE initiation)
Ai
tcR (27)
tcR (27)
ADDRESS 1
ADDRESS 6
tw(E)SR
E
tsu(A)SR (31)
DQi
(32)
High Impedance
Output
th(A)SR (33)
td(E)R (30)
td(E)S (29)
VALID
VALID
tdis(E)SR (28)
Software Controlled STORE/RECALL Cyclet, u, v, w (E = LOW after STORE initiation)
tcR (29)
Ai
ADDRESS 1
tw(E)SR
E
tsu(A)SR (33)
DQi
Output
ADDRESS 6
th(A)SR
(34)
High Impedance
th(A)SR (35)
(33)
tsu(A)SR
td(E)S (31)
(35)
td(E)R (32)
VALID
tdis(E)SR (30)
VALID
u: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the UL635H256 performs a STORE
or RECALL.
v: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
March 31, 2006
STK Control #ML0059
9
Rev 1.0
UL635H256
Test Configuration for Functional Check
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E
W
G
1.1 k
ment of all 8 output pins
VIL
DQ0
Simultaneous measure-
VIH
relevant test measurement
Input level according to the
3V
VCCX
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
VO
30 pF w
950
VSS
w: In measurement of tdis-times and ten-times the capacitance is 5 pF.
x:
Between VCC and VSS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.
Capacitancee
Conditions
VCC
VI
f
Ta
Input Capacitance
Output Capacitance
Symbol
= 3.0 V
= VSS
= 1 MHz
= 25 °C
Min.
Max.
Unit
CI
8
pF
CO
7
pF
All Pins not under test must be connected with ground by capacitors.
Ordering Code
Example
UL635H256 S2
C
45 G1
Type
Leadfree Option
blank = Standard Package
G1 = Leadfree Green Package
Package
S = SOP28 (330mil) Type 1
S2 = SOP28 (330mil) Type 2
Operating Temperature Range
C = 0 to 70 °C
K = -40 to 85 °C
Access Time
35 = 35 ns (VCC = 3.0 ... 3.6 V)
45 = 45 ns (VCC = 2.7 ... 3.6 V)
y: on special request
Device Marking (example)
Product specification
ZMD
UL635H256S2C
45
Z 0425
G1
Date of manufacture
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Leadfree Green Package
Internal Code
STK Control #ML0059
10
Rev 1.0
March 31, 2006
UL635H256
Device Operation
WRITE operation has taken place since the most
recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether or
not a WRITE operation has taken place.
The UL635H256 has two separate modes of operation:
SRAM mode and nonvolatile mode. The memory operates in SRAM mode as a standard fast static RAM.
Data is transferred in nonvolatile mode from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below VSWITCH. RECALL operations are automatically
initiated upon power up and may also occur when the
VCC rises above VSWITCH, after a low power condition.
RECALL cycles may also be initiated by a software
sequence.
During power up, an automatic RECALL takes place. At
a low power condition (power supply voltage < VSWITCH)
an internal RECALL request may be latched. As soon
as power supply voltage exceeds the sense voltage of
VSWITCH, a requested RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the UL635H256 is in a WRITE state at the end of
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 kΩ resistor should be
connected between W and power supply voltage.
SRAM READ
Software Nonvolatile STORE
The UL635H256 performs a READ cycle whenever E
and G are LOW and W is HIGH. The address specified
on pins A0 - A14 determines which of the 32768 data
bytes will be accessed. When the READ is initiated by
an address transition, the outputs will be valid after a
delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later.
The data outputs will repeatedly respond to address
changes within the tcR access time without the need for
transition on any control input pins, and will remain
valid until another address change or until E or G is
brought HIGH or W is brought LOW.
The UL635H256 software controlled STORE cycle is
initiated by executing sequential READ cycles from six
specific address locations. By relying on READ cycles
only, the UL635H256 implements nonvolatile operation
while remaining compatible with standard 32K x 8
SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is performed first, followed by a
parallel programming of all the nonvolatile elements.
Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE
initiation, it is important that no other READ or WRITE
accesses intervene in the sequence or the sequence
will be aborted.
To initiate the STORE cycle the following READ
sequence must be performed:
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
tsu(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the
entire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis (W) after W goes LOW.
Automatic STORE
The UL635H256 uses the intrinsic system capacitance
to perform an automatic STORE on power down. As
long as the decay rate from the system power supply is
smaller than 15 Vs-1 the UL635H256 will safely and
automatically STORE the SRAM data in EEPROM on
power down.
In order to prevent unneeded STORE operations, automatic STORE will be ignored unless at least one
March 31, 2006
STK Control #ML0059
11
Automatic RECALL
1.
2.
3.
4.
5.
6.
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
0E38
31C7
03E0
3C1F
303F
0FC0
(hex)
(hex)
(hex)
(hex)
(hex)
(hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE
Cycle
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the chip
will be disabled. It is important that READ cycles and
not WRITE cycles be used in the sequence, although it
is not necessary that G be LOW for the sequence to be
valid. After the tSTORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE
operation.
Rev 1.0
UL635H256
Software Nonvolatile RECALL
Hardware Protection
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ operations must be performed:
The UL635H256 offers hardware protection against
inadvertent STORE operation through VCC Sense.
When VCC < VSWITCH all software STORE operations
will be inhibited.
Low Average Active Power
1.
2.
3.
4.
5.
6.
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
Read addresses
0E38
31C7
03E0
3C1F
303F
0C63
(hex)
(hex)
(hex)
(hex)
(hex)
(hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL
Cycle
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. After
td(E)R cycle time the SRAM will once again be ready for
READ and WRITE operations.The RECALL operation
in no way alters the data in the EEPROM cells. The
nonvolatile data can be recalled an unlimited number of
times.
The UL635H256 has been designed to draw significantly less power when E is LOW (chip enabled) but
the cycle time is longer than 45 ns.
When E is HIGH the chip consumes only standby current.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
STK Control #ML0059
12
Rev 1.0
March 31, 2006
UL635H256
LIFE SUPPORT POLICY
Simtek products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the Simtek product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by Simtek for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However, Simtek
makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any
loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document
describes the type of component and shall not be considered as assured characteristics.
Simtek does not guarantee that the use of any information contained herein will not infringe upon the patent,
trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby.
This document does not in any way extent Simtek’s warranty on any product beyond that set forth in its standard
terms and conditions of sale.
Simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or
both, presented in this publication at any time and without notice.
March 31, 2006
Change record
Date/Rev
Name
Change
01.11.2001
Ivonne Steffens
format revision and release for „Memory CD 2002“
03.07.2002
Matthias Schniebel
adding 35 ns type with VCC = 3.0 ... 3.6 V
25.09.2002
Matthias Schniebel
Adding „Type 1“ to SOP28 (330mil)
09.01.2003
Matthias Schniebel
Removing 55 ns type
20.10.2003
Matthias Schniebel
Low Voltage Trigger Level VSWITCH = 2.4 ... 2.7 V (old: 2.5 ... 2.7 V)
changing max. decay rate from the system power supply to 15 Vs-1
(old: 10 Vs-1)
05.12.2003
Matthias Schniebel
ICC = 8 mA typ. at 200 ns Cycle Time
adding K-Type with 35 ns: ICC1 = 47 mA, ICC(SB)1 = 12mA
21.04.2004
Matthias Schniebel
adding „Leadfree Green Package“ to ordering information
adding „Device Marking“
7.4.2005
Stefan Günther
Page1: adding RoHS compliance and Pb- free, 106 endurance cycles
and 100a data retention,
add also S2 package (chip pack) and ordering code
31.3.2006
Troy Meester
changed to obsolete status
Simtek
Assigned Simtek Document Control Number
1.0