JT9673-AS TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic JT9673-AS LCD Display Stopwatch LSI This product is a single-chip CMOS LSI for stopwatches capable of directly driving a 7-digit LCD with four signs. Applications · Stopwatches Features · 32.768 kHz crystal oscillator · Displays hour, minute, second, and hundredths of seconds · Four-sign, 7-digit display, 1/3-duty LCD drive · 5 display modes (RESET, RUN, STOP, LAP, LAP STOP) and optional display modes (NORMAL LAP, SECTION LAP) are selectable by bonding option. · Counting by 9 hours, 59 minutes, 59 seconds, 99 hundredths of second (units: 1/100 second) · Power supply: 1.55 V-single power supply · Built-in voltage doubler circuit · Low current consumption (Isup = 3.0 µA max) Block Diagram 1 2003-02-12 JT9673-AS Pin Descriptions (44 pins) Pin Name Symbol No. of Pins Power Supply Pins VDD (2), VSS1, VSS2 4 Oscillator Pins XI, XO 2 Input Pins S1~3, SL1~3 6 Output Pin BUZZ 1 Display Pins COM1~3, SEG (22) 25 Test Pins T1~4 4 Voltage Doubler Pins FAI1, FAI2 2 Pad Layout Note 1: Be sure to connect the VDD (MAIN). 2 2003-02-12 JT9673-AS Pad Location Table (mm) Pin Name X Point Y Point Pin Name X Point Y Point SEG1 -1067 -618 SEG21 1067 618 SEG5 -1067 -455 SEG20 1067 455 SEG6 -1067 -292 SEG16 1067 292 SEG7 -1067 -129 SEG15 1067 130 SEG11 -1067 33 SEG14 1067 -33 SEG12 -1067 196 SEG10 1067 -196 SEG13 -1067 359 SEG9 1067 -359 SEG17 -1067 522 SEG8 1067 -522 SEG18 -1067 684 SEG4 1067 -684 SEG19 -1067 847 SEG3 1067 -847 COM3 -1067 1010 SEG2 1067 -1010 COM2 -618 1067 T4 618 -1067 COM1 -455 1067 T3 455 -1067 FAI1 -292 1067 T2 292 -1067 FAI2 -129 1067 T1 130 -1067 VSS2 33 1067 SL1 -33 -1067 XI 196 1067 VDD (SUB) -196 -1067 XO 359 1067 SL2 -359 -1067 VDD (MAIN) 522 1067 SL3 -522 -1067 BUZZ 684 1067 S1 -684 -1067 VSS1 847 1067 S2 -847 -1067 SEG22 1010 1067 S3 -1010 -1067 3 2003-02-12 JT9673-AS Function Specifications 1. LCD Segment Pattern COM1 COM2 COM3 COM1 COM2 COM3 SEG1 Lap Section 1 Standard 1 SEG12 4d 4g 4a SEG2 Stop 7e SEG3 7d 7g 7f SEG13 4p 4c 4b 7a SEG14 ¾ 3e 3f SEG4 7p 7c 7b SEG15 3d 3g 3a SEG5 ¾ 6e 6f SEG16 3p 3c 3b SEG6 6d 6g 6a SEG17 Standard 2 2e 2f SEG7 6p 6c 6b SEG18 2d 2g 2a SEG8 ¾ 5e 5f SEG19 2p 2c 2b SEG9 5d 5g 5a SEG20 ¾ 1e 1f SEG10 5p 5c 5b SEG21 1d 1g 1a SEG11 Section 2 4e 4f SEG22 1p 1c 1b 2. LCD Drive Waveform 4 2003-02-12 JT9673-AS 3. Display Modes 4. Display Sequence The display returns from 9 hours, 59 minutes, 59 seconds, 99 1/100 seconds, to 0 hours, 00 minutes, 00 seconds 00 and counting continues. 5. Display Example 5 2003-02-12 JT9673-AS 6. Input Setting S1, S2, S3: Normally all pulled down to the VSS1 level by IC internal pull-down resistance. S1, S2, and S3 perform their specified functions when connected to the VDD by an external switch. SL1, SL2, SL3: Normally, all pulled down to the VSS1 level by IC internal pull-down resistance. Setting the level of the pins externally allows functions to be selected T1, T2, T3, T4: Normally, all pulled up to the VDD level by IC internal pull-up resistance. Used for IC testing. 7. Type Selection Function SL1 SL2 SL3 Type 0 ¾ ¾ A Type (1/100 seconds display) 1 ¾ ¾ B Type (1/10 seconds display) ¾ 0 0 C Type ¾ 1 0 D Type ¾ 0 1 E Type ¾ 1 1 F Type See 8. Mode Sequence. Note 2: ‘0’ indicates input is OPEN or connect to VSS1. ‘¾’ indicates don’t care. 8. Mode Sequence (1) C type Starts functioning on the rising edge of S1 and S2 (2) D type (3) 6 E type 2003-02-12 JT9673-AS (4) F type STANDARD LAP mode SECTION LAP mode · S3 toggles between STANDARD LAP mode and SECTION LAP mode. · In SECTION LAP mode, when switched from RUN to LAP, the counter is immediately reset to ‘0’. · When switched from SECTION LAP mode to NORMAL LAP mode by pressing S3, the counter is not reset to ‘0’. 9. Display Column Table Display Column Mode Reset Digit Segment Dot Segment 7 6 5 4 3 2 □ □ □ □ □ (¾) Run 10 1 10 1 Hour min- min- sec- secutes ute onds ond Stop 10 1 10 1 1/10 Hour min- min- sec- secutes ute onds ond second Lap 10 1 10 1 Hour min- min- sec- secutes ute onds ond Lap Stop 10 1 10 1 Hour min- min- sec- secutes ute onds ond (¾) 1 □ (□) 1/100 second (1/10 second) 5P 4P 3P Sign 2P 1P Lap Stop Stan- Secdard tion 7P 6P ● (1) 1 (1) 1 ● (1) 1 (1) 1 ● (1) 1 (1) 1 ● (1) 1 ● (1) 1 ● (1) 1 ● (1) 1 ● ● Note 3: When 1/10 s type is selected, only the first and second column displays are different. The display is as in the parentheses ( ). Note 4: ‘●’ indicates ‘lit’. (7P always lit) Note 5: ‘●’ indicates flashing at 1 Hz. Note 6: In the F type only, ‘(1)’ flashes at 1 Hz when STANDARD LAP mode is selected. Note 7: In the F type only, ‘ 1 ’ flashes at 1 Hz when SECTION LAP mode is selected. Note 8: 1P, 2P, 3P, and 5P do not light. 7 2003-02-12 JT9673-AS 10. Chattering Prevention Function A chattering prevention circuit is provided for the S1, S2, and S3 inputs. The input waveform shown below does not cause malfunction. Tch < 31.25 ms TON, OFF > = 31.25 ms 11. Buzzer Drive Function Pressing S1 or S2 turns the buzzer drive circuit ON for around 30~60 ms. The drive frequency is 4 kHz. 12. Autoclear Circuit An autoclear circuit is incorporated for when the power supply is switched ON, at which time the counter reads “0” and RESET mode is selected. (to operate the autoclear circuit more dependably, externally attach a capacitor between T2 and VSS1.) 13. Input Circuit Setting Error The S1, S2 switch input circuit operates on the first rising edge of the input. The error for one switching is a maximum of 1/100 second. 14. Test Functions T1 T2 T3 T4 S1 S2 Function 1 1 1 1 0 0 Normal 1 0 ¾ ¾ ¾ ¾ All clear 0 fT2 ¾ ¾ ¾ ¾ Acceleration from the 256 Hz stage using fT2 ¾ ¾ 0 0 1 0 Output 100 Hz to BUZZ pin ¾ ¾ 0 0 0 1 +1 h by S2 ¾ ¾ 1 0 1 ¾ +10 mins by S1 ¾ ¾ 1 0 ¾ 1 +1 min by S2 ¾ ¾ 0 1 1 ¾ +10 s by S1 ¾ ¾ 0 1 ¾ 1 +1 s by S2 ¾ ¾ 0 0 1 1 LCD all lit, BUZZ output (H level) Note 9: When T3 = 0 or T4 = 0, the normal functions of S1 and S2 are disabled. Note 10: An ALL CLEAR sets to RESET mode (0 hours, 00 minutes, 00 seconds, 00 1/100 seconds). 15. All Clear Function When power is applied or when the supply of power is interrupted (e.g. if the battery is changed), the internal state of the IC may become unstable, even though it appears to be operating normally. For this reason it is vital to verify that the crystal oscillation circuit is oscillating normally ant stably (at 32 kHz) and then to use the system reset pin to initialize the IC (i.e. clear it) before use. Note that a clear operation using the built-in power-on clear circuit should not be used in this case. 8 2003-02-12 JT9673-AS Maximum Ratings (if no temperature stipulations, Ta = 25°C) Characteristics Symbol Rating Unit Power supply voltage (1) VSS1-VDD -3.0~0.2 V Power supply voltage (2) VSS2-VDD -4.5~0.2 V VIN1 VSS1 - 0.2~VDD + 0.2 V Input voltage (1) VIN2 VSS2 - 0.2~VDD + 0.2 V Output voltage (1) VOUT1 VSS1 - 0.2~VDD + 0.2 V Output voltage (2) VOUT2 VSS2 - 0.2~VDD + 0.2 V Operating temperature Topr -10~60 °C Storage temperature Tstg -40~125 °C Input voltage (2) Electrical Characteristics (unless otherwise stated, VDD = 0.00 V, VSS1 = -1.55 V, VSS2 = -3.00 V, CG = 20 pF, W, Fo = 32768 Hz) CD = built-in (10 pF), CIMAX = 21 kW Symbol Test Circuit Test Condition Min Typ. Max Unit ïVSS1-VDDï 3 ¾ 1.25 1.55 1.80 V ïIsupï 2 No LCD load ¾ ¾ 3.0 mA ïVSTAï 3 tSTA 10 s ¾ ¾ 1.40 V Output current (1) IOH1 4 VOH1 = -0.2 V ¾ ¾ -0.5 Segment IOL1 4 VOL1 = -2.8 V 0.5 ¾ ¾ Output current (2) IOH2 4 VOH2 = -0.2 V ¾ ¾ -4.0 Common IOL2 4 VOL2 = -2.8 V 4.0 ¾ ¾ Output current (3) IOH3 4 VSS1 = -1.25 V ¾ ¾ -100 IOL3 4 VSS2 = -2.8 V VOL3 = -0.75 V 100 ¾ ¾ Input current (1) IIH1 4 VIH1 = 0 V 1.55 ¾ 20.0 S3, SL1, SL2, SL3 IIL1 4 VIL1 = -1.55 V -0.1 ¾ ¾ Input current (2) IIH2 4 VIH2 = 0 V ¾ ¾ 0.1 T1, T3, T4 IIL2 4 VIL2 = -1.55 V ¾ -50 ¾ Input current (3) IIH3 4 VIH3 = 0 V ¾ ¾ 0.1 T2 IIL3 4 VIL3 = -1.55 V -15.5 ¾ ¾ Input current (4) IIH4 4 VIH4 = 0 V 15.5 ¾ 150 S1, S2 IIL4 4 VIL4 = -1.55 V -0.1 ¾ ¾ ïVUCOï 2 C1 = C2 = 0.1 mF, RL = 3 MW 3.0 ¾ ¾ Characteristics Operating voltage Operating current consumption Oscillation start voltage Buzzer Voltage doubler output 9 VOH3 = -0.5 V mA mA mA mA mA mA mA V 2003-02-12 JT9673-AS Test Circuit 1. Oscillation Circuit X’tal Rs = 21 kW Fo = 32.768 kHz CG = 20 pF CD = 10 pF built in 2. Measuring Isup and VUCO 3. 4. When measuring SL1, SL2, SL3, set T2 to VSS1. 10 2003-02-12 JT9673-AS Application Circuit Example Note 11: Be sure to connect the VDD (MAIN). 11 2003-02-12 JT9673-AS RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 12 2003-02-12