STK25C48 2K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM Obsolete - Not Recommend for new Designs FEATURES DESCRIPTION • Nonvolatile Storage without Battery Problems • Directly Replaces 2K x 8 Static RAM, BatteryBacked RAM or EEPROMs • 25ns, 35ns and 45ns Access Times • STORE to Nonvolatile Elements Initiated by AutoStore™ on Power Down • RECALL to SRAM Initiated by Power Restore • 10mA Typical ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to Nonvolatile Elements • 100-Year Data Retention over Full Industrial Temperature Range • Commercial and Industrial Temperatures • 24-Pin 600 PDIP Package The STK25C48 is a fast SRAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in the Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation) can take place automatically on power down using charge stored in system capacitance. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) take place automatically on restoration of power. The nvSRAM can be used in place of existing 2K x 8 SRAMs and also matches the pinout of 2K x 8 battery-backed SRAMs, EPROMs and EEPROMs, allowing direct substitution while enhancing performance. No support circuitry is required for microprocessor interfacing. PIN CONFIGURATIONS BLOCK DIAGRAM ROW DECODER QUANTUM TRAP 32 x 512 A5 A6 A7 A8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 INPUT BUFFERS A9 March 2006 STORE STATIC RAM ARRAY 32 x 512 RECALL VCC STORE/ RECALL CONTROL POWER CONTROL A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 24 - 600 PDIP PIN NAMES COLUMN I/O COLUMN DEC A0 A1 A2 A3 A4 A10 A0 - A10 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable E G Output Enable W VCC Power (+ 5V) VSS Ground G 1 Document Control # ML0005 rev 0.2 STK25C48 ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (VCC = 5.0V ± 10%) DC CHARACTERISTICS COMMERCIAL SYMBOL INDUSTRIAL PARAMETER UNITS MIN MAX MIN NOTES MAX ICC1b Average VCC Current 85 75 65 90 75 65 mA mA mA tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns ICC2c Average VCC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max Average VCC Current at tAVAV = 200ns 5V, 25°C, Typical 10 10 mA W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels ICC4c Average VCAP Current during AutoStore™ Cycle 2 2 mA ISB1d Average VCC Current (Standby, Cycling TTL Input Levels) 25 21 18 26 22 19 mA mA mA tAVAV = 25ns, E ≥ VIH tAVAV = 35ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH ISB2d VCC Standby Current (Standby, Stable CMOS Input Levels) 1.5 1.5 mA E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) IILK Input Leakage Current ±1 ±1 μA VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current ±5 ±5 μA VCC = max VIN = VSS to VCC, E or G ≥ VIH VIH Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 V All Inputs VOH Output Logic “1” Voltage V IOUT = – 4mA VOL Output Logic “0” Voltage 0.4 V IOUT = 8mA TA Operating Temperature 85 °C ICC3 b 2.4 2.4 0.4 0 70 –40 All Inputs Don’t Care Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC2 and ICC4 are the average currents required for the duration of the respective STORE cycles (tSTORE ) . Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEe SYMBOL (TA = 25°C, f = 1.0MHz) PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 8 pF ΔV = 0 to 3V COUT Output Capacitance 7 pF ΔV = 0 to 3V 5.0V 480 Ohms OUTPUT 255 Ohms 30 pF INCLUDING SCOPE AND FIXTURE Note e: These parameters are guaranteed but not tested. Figure 1: AC Output Loading March 2006 2Document Control # ML0005 rev 0.2 STK25C48 (VCC = 5.0V ± 10%) SRAM READ CYCLES #1 & #2 SYMBOLS NO. STK25C48-25 STK25C48-35 STK25C48-45 PARAMETER #1, #2 1 tELQV 2 f tAVAV g 3 tAVQV 4 tGLQV 5 tAXQX 6 tELQX UNITS Alt. g h MIN 25 tAA Address Access Time 25 35 45 ns tOE Output Enable to Data Valid 10 15 20 ns tOH Output Hold after Address Change 5 5 5 ns tLZ Chip Enable to Output Active 5 5 5 ns 25 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZh tOHZ Output Disable to Output Inactive tPA Chip Enable to Power Active tPS Chip Disable to Power Standby tEHICCLd, e 35 MAX Read Cycle Time Chip Disable to Output Inactive tELICCH MIN tRC tHZ 11 MAX Chip Enable Access Time tEHQZ 10 MIN tACS 7 e MAX 45 35 45 10 0 13 0 ns 15 0 0 10 13 0 35 ns ns 15 0 25 ns ns ns 45 ns Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured + 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledf, g 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (DATA OUT) DATA VALID SRAM READ CYCLE #2: E Controlledf 2 tAVAV ADDRESS 1 11 tELQV E tEHICCL 6 tELQX 7 tEHQZ G 9 tGHQZ 4 8 tGLQV tGLQX DQ (DATA OUT) DATA VALID 10 tELICCH ICC March 2006 ACTIVE STANDBY 3 Document Control # ML0005 rev 0.2 STK25C48 (VCC = 5.0V ± 10%) SRAM WRITE CYCLES #1 & #2 SYMBOLS STK25C48-25 NO. STK25C48-35 STK25C48-45 PARAMETER UNITS #1 #2 Alt. 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 ns 20 tWLQZh, i tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write Note i: Note j: MIN MAX MIN MAX 10 5 MIN 13 5 MAX 15 5 ns ns If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be ≥ VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledj 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 16 tDVWH DATA IN tWHDX DATA VALID 20 tWLQZ DATA OUT 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA SRAM WRITE CYCLE #2: E Controlledj 12 tAVAV ADDRESS 18 19 14 tAVEL tEHAX tELEH E 17 tAVEH 13 W tWLEH 16 15 tEHDX tDVEH DATA IN DATA OUT March 2006 DATA VALID HIGH IMPEDANCE 4Document Control # ML0005 rev 0.2 STK25C48 AutoStore™/POWER-UP RECALL (VCC = 5.0V ± 10%) SYMBOLS STK25C48 NO. PARAMETER Standard MIN 22 tRESTORE Power-up RECALL Duration 23 tSTORE STORE Cycle Duration 24 tDELAY Time Allowed to Complete SRAM Cycle 25 VSWITCH Low Voltage Trigger Level 26 VRESET Low Voltage Reset Level UNITS NOTES 550 μs k 10 ms g μs g MAX 1 4.0 4.5 V 3.6 V e Note k: tRESTORE starts from the time VCC rises above VSWITCH. AutoStore™/POWER-UP RECALL VCC 5V 25 VSWITCH 26 VRESET AutoStore™ 23 tSTORE POWER-UP RECALL 24 tDELAY 22 tRESTORE W DQ (DATA OUT) POWER-UP RECALL March 2006 BROWN OUT NO STORE DUE TO NO SRAM WRITES BROWN OUT AutoStore™ BROWN OUT AutoStore™ NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH 5 Document Control # ML0005 rev 0.2 STK25C48 DEVICE OPERATION The STK25C48 is a versatile memory chip that provides several modes of operation. The STK25C48 can operate as a standard 8K x 8 SRAM. It has an 8K x 8 Nonvolatile Elements shadow to which the SRAM information can be copied, or from which the SRAM can be updated in nonvolatile mode. NOISE CONSIDERATIONS Note that the STK25C48 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1μF connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. SRAM READ The STK25C48 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-10 determines which of the 2,048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high or W is brought low. AutoStore™ OPERATION The STK25C48 uses the intrinsic system capacitance to perform an automatic store on power down. As long as the system power supply takes at least tSTORE to decay from VSWITCH down to 3.6V, the STK25C48 will safely and automatically store the SRAM data in Nonvolatile Elements on power down. In order to prevent unneeded STORE operations, automatic STORE will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. POWER-UP RECALL During power up, or after any low-power condition (VCC < VRESET), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK25C48 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC. HARDWARE PROTECT The STK25C48 offers hardware protection against inadvertent STORE operation and SRAM WRITEs during low-voltage conditions. When VCC < VSWITCH, STORE operations and SRAM WRITEs are inhibited. SRAM WRITE LOW AVERAGE ACTIVE POWER A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. The STK25C48 draws significantly less current when it is cycled at times longer than 50ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK25C48 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the VCC level; and 7) I/O loading. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. March 2006 6Document Control # ML0005 rev 0.2 STK25C48 100 Average Active Current (mA) Average Active Current (mA) 100 80 60 40 TTL 20 80 60 TTL 40 CMOS 20 CMOS 0 0 50 100 150 Cycle Time (ns) 200 50 Figure 2: ICC (max) Reads March 2006 100 150 Cycle Time (ns) 200 Figure 3: ICC (max) Writes 7 Document Control # ML0005 rev 0.2 STK25C48 ORDERING INFORMATION STK25C48 - W F 45 I Temperature Range Blank = Commercial (0 to 70°C) I = Industrial (–40 to 85°C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Lead Finish Blank = 85%Sn/15%Pb F = 100% Sn (Matte Tin) Package W = Plastic 24-pin 600 mil DIP March 2006 8Document Control # ML0005 rev 0.2 STK25C48 Document Revision History Revision Date Summary 0.0 December 2002 Removed 20 nsec device. 0.1 September 2003 Added lead-free lead finish 0.2 March 2006 Marked as Obsolete, Not recommended for new design. March 2006 9 Document Control # ML0005 rev 0.2 STK25C48 March 2006 10Document Control # ML0005 rev 0.2