WM8718
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24 Bit Differential Stereo DAC with Volume Control
DESCRIPTION
FEATURES
The WM8718 is a high performance differential stereo DAC
designed for audio applications such as DVD, home theatre
systems and digital TV. The WM8718 supports PCM data
input word lengths from 16 to 32-bits and sampling rates up
to 192kHz. The WM8718 consists of a serial interface port,
digital interpolation filters, multi-bit sigma delta modulators
and differential stereo DAC in a small 20-lead SSOP
package or 24-lead QFN package. The WM8718 includes a
digitally controllable mute, an attenuate function and zero
flag output for each channel.
•
•
The 3-wire serial control port provides access to a wide
range of features including on-chip mute, attenuation and
phase reversal.
The WM8718 is an ideal device to interface to AC-3™,
DTS™, and MPEG audio decoders for surround sound
applications, or for use in DVD players including those
supporting DVD-A.
24 bit Stereo DAC
Fully Differential Voltage Outputs
•
Audio Performance
•
•
•
- 111dB SNR (‘A’ weighted @ 48kHz) DAC
- -100dB THD
DAC Sampling Frequency: 8kHz - 192kHz
3 Wire Serial Control Interface
Programmable Audio Data Interface Modes
- I2S, Left, Right Justified, DSP
- 16/20/24/32 bit Word Lengths
Independent Digital Volume Control on Each Channel with
127.5dB Range in 0.5dB Steps
•
•
•
•
Independent Zero Flag Outputs
3.0V - 5.5V Supply Operation
20-lead SSOP Package or 24-lead QFN Package
APPLICATIONS
•
CD, DVD, and DVD-Audio Players
•
•
Home theatre systems
Professional mixing desks
SCLK
LATCH
SDIN
BLOCK DIAGRAM
W
WM8718
ATT/
MUTE
BCKIN
LRCIN
ZEROFR
ZEROFL
CONTROL
INTERFACE
VOUTRP
SIGMA
DELTA
MODULATOR
DAC
SIGMA
DELTA
MODULATOR
DAC
VOUTRN
DIGITAL
FILTERS
AUDIO
INTERFACE
DIN
ATT/
MUTE
VOUTLP
VOUTLN
WOLFSON MICROELECTRONICS plc
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VREFN
VREFP
AGND
AVDD
MCLK
DGND
DVDD
VMID
Production Data, November 2006, Rev 4.3
Copyright ©2006 Wolfson Microelectronics plc
WM8718
Production Data
TABLE OF CONTENTS
DESCRIPTION ............................................................................................................1
FEATURES..................................................................................................................1
APPLICATIONS ..........................................................................................................1
BLOCK DIAGRAM ......................................................................................................1
TABLE OF CONTENTS ..............................................................................................2
PIN CONFIGURATION – 20 LEAD SSOP ..................................................................3
ORDERING INFORMATION – 20 LEAD SSOP..........................................................3
PIN CONFIGURATION – 24 LEAD QFN.....................................................................4
ORDERING INFORMATION – 24 LEAD QFN ............................................................4
PIN DESCRIPTION – 20 LEAD SSOP........................................................................5
PIN DESCRIPTION – 24 LEAD QFN ..........................................................................6
ABSOLUTE MAXIMUM RATINGS..............................................................................7
DC ELECTRICAL CHARACTERISTICS .....................................................................8
ELECTRICAL CHARACTERISTICS ...........................................................................8
TERMINOLOGY ................................................................................................................. 9
MASTER CLOCK TIMING .................................................................................................10
DIGITAL AUDIO INTERFACE TIMINGS ...........................................................................10
3-WIRE SERIAL CONTROL INTERFACE TIMING ...........................................................11
INTERNAL POWER ON RESET CIRCUIT ...............................................................12
DEVICE DESCRIPTION............................................................................................14
INTRODUCTION ...............................................................................................................14
CLOCKING SCHEMES .....................................................................................................14
DIGITAL AUDIO INTERFACE ...........................................................................................14
AUDIO DATA SAMPLING RATES.....................................................................................16
REGISTER MAP ...............................................................................................................18
DIGITAL FILTER CHARACTERISTICS.............................................................................24
DAC FILTER RESPONSES...............................................................................................24
DIGITAL DE-EMPHASIS CHARACTERISTICS ........................................................25
TYPICAL PERFORMANCE.......................................................................................26
APPLICATIONS INFORMATION ..............................................................................27
RECOMMENDED EXTERNAL COMPONENTS – 20 LEAD SSOP ...................................27
RECOMMENDED EXTERNAL COMPONENTS – 24 LEAD QFN .....................................28
RECOMMENDED EXTERNAL COMPONENTS VALUES .................................................28
RECOMMENDED ANALOGUE LOW PASS FILTER FOR PCM DATA FORMAT
(OPTIONAL)......................................................................................................................29
PACKAGE DIMENSIONS – 20 LEAD SSOP............................................................30
PACKAGE DIMENSIONS – 24 LEAD QFN ..............................................................31
IMPORTANT NOTICE ...............................................................................................32
ADDRESS: ........................................................................................................................32
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PIN CONFIGURATION – 20 LEAD SSOP
LRCIN
1
20
DIN
DVDD
2
19
BCKIN
DGND
3
18
MCLK
AVDD
4
17
ZEROFL
VREFP
5
16
ZEROFR
15
SCLK
WM8718
VREFN
6
AGND
7
14
SDIN
VMID
8
13
LATCH
VOUTRP
9
12
VOUTLP
VOUTRN
10
11
VOUTLN
ORDERING INFORMATION – 20 LEAD SSOP
DEVICE
TEMPERATURE
RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
WM8718SEDS
-25 to +85oC
20-lead SSOP
(Pb-free)
MSL1
260°C
WM8718SEDS/R
-25 to +85oC
20-lead SSOP
(Pb-free, tape and reel)
MSL1
260°C
Note:
Reel quantity = 2,000
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PIN CONFIGURATION – 24 LEAD QFN
ORDERING INFORMATION – 24 LEAD QFN
DEVICE
TEMPERATURE
RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
WM8718GEFL/V
-25 to +85 C
o
24-lead QFN
(Pb-free)
MSL3
260°C
WM8718GEFL/RV
-25 to +85 C
o
24-lead QFN
(Pb-free, tape and reel)
MSL3
260°C
Note:
Reel quantity = 3,500
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PIN DESCRIPTION – 20 LEAD SSOP
PIN
NAME
TYPE
1
LRCIN
Digital Input
DESCRIPTION
2
DVDD
Supply
Positive Digital Supply
3
DGND
Supply
Ground Digital Supply
4
AVDD
Supply
Positive Analogue Supply
5
VREFP
Supply
Positive DAC reference Supply
6
VREFN
Supply
Negative DAC reference Supply
7
AGND
Supply
Ground Analogue Supply
8
VMID
Analogue Output
Mid Rail Decoupling Point
9
VOUTRP
Analogue Output
Right Channel DAC Output Positive
10
VOUTRN
Analogue Output
Right Channel DAC Output Negative
11
VOUTLN
Analogue Output
Left Channel DAC Output Negative
12
VOUTLP
Analogue Output
Left Channel DAC Output Positive
13
LATCH
Digital Input P.U.
Serial Control Load Input
14
SDIN
Digital Input
Serial Control Data Input
15
SCLK
Digital Input P.D.
16
ZEROFR
Digital Output (Open drain)
Infinite ZERO Detect Flag for Right Channel
17
ZEROFL
Digital Output (Open drain)
Infinite ZERO Detect Flag for Left Channel
18
MCLK
Digital Input
Master Clock Input
19
BCLKIN
Digital Input
PCM Audio Data Bit Clock Input
20
DIN
Digital Input
PCM Serial Audio Data Input
PCM DAC Sample Rate Clock Input
Serial Control Data Input Clock
Note:
Digital input pins have Schmitt trigger input buffers. Pins marked `P.U.` or `P.D.` have an internal pull-up or pull-down resistor.
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PIN DESCRIPTION – 24 LEAD QFN
PIN
NAME
TYPE
1
DVDD
Supply
Positive Digital Supply
DESCRIPTION
2
DGND
Supply
Ground Digital Supply
3
AVDD
Supply
Positive Analogue Supply
4
VREFP
Supply
Positive DAC reference Supply
5
VREFN
Supply
Negative DAC reference Supply
6
AGND
Supply
Ground Analogue Supply
7
VMID
Analogue Output
Mid Rail Decoupling Point
8
VOUTRP
Analogue Output
Right Channel DAC Output Positive
9
VOUTRN
Analogue Output
Right Channel DAC Output Negative
10
VOUTLN
Analogue Output
Left Channel DAC Output Negative
11
VOUTLP
Analogue Output
Left Channel DAC Output Positive
12
NC
No Connect
No Connect
13
NC
No Connect
No Connect
14
LATCH
Digital Input P.U.
Serial Control Load Input
15
SDIN
Digital Input
Serial Control Data Input
16
SCLK
Digital Input P.D.
17
ZEROFR
Digital Output (Open drain)
18
NC
No Connect
19
ZEROFL
Digital Output (Open drain)
20
MCLK
Digital Input
Master Clock Input
21
BCLKIN
Digital Input
PCM Audio Data Bit Clock Input
22
DIN
Digital Input
PCM Serial Audio Data Input
23
LRCIN
Digital Input
PCM DAC Sample Rate Clock Input
24
NC
No Connect
No Connect
Serial Control Data Input Clock
Infinite ZERO Detect Flag for Right Channel
No Connect
Infinite ZERO Detect Flag for Left Channel
Note:
1. Digital input pins have Schmitt trigger input buffers. Pins marked `P.U.` or `P.D.` have an internal pull-up or pull-down
resistor.
2. It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
MIN
MAX
Digital supply voltage (DVDD)
-0.3V
+7V
Analogue supply voltage (AVDD)
-0.3V
+7V
DGND -0.3V
VDD +0.3V
CONDITION
Voltage range digital inputs
Master Clock Frequency
37MHz
Operating temperature range, TA
-25°C
+85°C
Storage temperature after soldering
-65°C
+150°C
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DC ELECTRICAL CHARACTERISTICS
PARAMETER
MAX
UNIT
Digital supply range
DVDD
3.0
5.5
V
Analogue supply range
AVDD
3.0
5.5
V
Ground
SYMBOL
TEST CONDITIONS
MIN
AGND, DGND
TYP
0
Difference DGND to AGND
-0.3
0
V
+0.3
V
Supply current
AVDD = 3.3V
0.1911
19
mA
Supply current
AVDD = 5V
DVDD = 3.3V
DVDD = 5V
0.1911
160 uA
160 uA
22
7.1
8.3
mA
mA
mA
Notes:
1. This value represents the current usage when there are no switching digital inputs, MCLK is applied and the chip is in
power down mode
2. Digital supply DVDD must never be more than 0.3V greater than AVDD.
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.8
V
Digital Logic Levels (TTL Levels)
Input LOW level
VIL
Input HIGH level
VIH
Output LOW
VOL
IOL = 1mA
Output HIGH
VOH
IOH = 1mA
DVDD – 0.3V
VMID
AVDD/2 50mV
2.0
V
AGND + 0.3V
V
V
Analogue Reference Levels
Reference voltage
Potential divider resistance
RVMID
AVDD/2
AVDD/2 +
50mV
V
8.7
kΩ
111
dB
109
dB
109
dB
105
dB
102
dB
108
dB
DAC Output (Load = 10kΩ 50pF)
SNR (Note 1,2,3)
SNR (Note 1,2,3)
SNR (Note 1,2,3)
SNR (Note 1,2,3)
SNR (Note 1,2,3)
SNR (Note 1,2,3)
THD (Note 1,2,3)
THD+N (Dynamic range, Note 2)
DAC channel separation
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A-weighted,
@ fs = 48kHz
A-weighted
@ fs = 96kHz
A-weighted
@ fs = 192kHz
A-weighted,
@ fs = 48kHz
AVDD = 3.3V
A-weighted
@ fs = 96kHz
AVDD = 3.3V
Non ‘A’ weighted @ fs
= 48kHz
1kHz, 0dBFs
105
1kHz, -60dBFs
105
-100
-80
dB
111
dB
100
dB
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Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Output Levels
Differential Output level
Load = 10kΩ, 0dBFS
Load = 10kΩ, 0dBFS,
(AVDD = 3.3V)
Gain mismatch
channel-to-channel
Minimum resistance load
Maximum capacitance load
To midrail or a.c.
coupled
To midrail or a.c.
coupled
(AVDD = 3.3V)
5V or 3.3V
Output d.c. level
2.0
1.32
VRMS
VRMS
±1
%FSR
1
kΩ
600
Ω
100
pF
(AVDDGND)/2
V
2.0
V
Power On Reset (POR)
POR threshold
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all ZEROS into the digital input, over a 20Hz to
20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a
filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification
values.
3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1.
Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full-scale output and the output with a
ZERO signal applied. (No Auto-ZERO or Automute function is employed in achieving these results).
2.
Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a
THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3.
THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4.
Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5.
Channel Separation (dB) - Also known as Cross Talk. This is a measure of the amount one channel is isolated from the
other. Normally measured by sending a full-scale signal down one channel and measuring the other.
6.
Pass-Band Ripple – Any variation of the frequency response in the pass-band region.
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MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Master Clock Timing Information
MCLK Master clock pulse width high
tMCLKH
13
ns
MCLK Master clock pulse width low
tMCLKL
13
ns
MCLK Master clock cycle time
tMCLKY
26
MCLK Duty cycle
ns
40:60
60:40
DIGITAL AUDIO INTERFACE TIMINGS
tBCH
tBCL
BCKIN
tBCY
LRCIN
tDS
tLRH
tLRSU
DIN
tDH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
tBCY
40
ns
BCKIN pulse width high
tBCH
16
ns
BCKIN pulse width low
tBCL
16
ns
LRCIN set-up time to
BCKIN rising edge
tLRSU
8
ns
LRCIN hold time from
BCKIN rising edge
tLRH
8
ns
DIN set-up time to BCKIN
rising edge
tDS
8
ns
DIN hold time from BCKIN
rising edge
tDH
8
ns
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3-WIRE SERIAL CONTROL INTERFACE TIMING
tCSL
tCSH
LATCH
tSCY
tSCH
tCSS
tSCS
tSCL
SCLK
LSB
SDIN
tDSU
tDHO
Figure 3 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to LATCH
rising edge
tSCS
40
ns
SCLK pulse cycle time
tSCY
80
ns
SCLK pulse width low
tSCL
20
ns
SCLK pulse width high
tSCH
20
ns
SDIN to SCLK set-up time
tDSU
20
ns
SCLK to SDIN hold time
tDHO
20
ns
LATCH pulse width low
tCSL
20
ns
LATCH pulse width high
tCSH
20
ns
LATCH rising to SCLK rising
tCSS
20
ns
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INTERNAL POWER ON RESET CIRCUIT
Figure 4 Internal Power On Reset Circuit Schematic
The WM8718 includes an internal Power On Reset Circuit which is used reset the digital logic into
a default state after power up.
Figure 4 shows a schematic of the internal POR circuit. The POR circuit is powered from AVDD.
The circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the
minimum threshold Vpor_off.
On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until
AVDD and DVDD and VMID are established. When AVDD, DVDD, and VMID have been
established, PORB is released high, all registers are in their default state and writes to the digital
interface may take place.
On power down, PORB is asserted low whenever DVDD or VMID drop below the minimum
threshold Vpor_off.
If AVDD is removed at any time, the internal Power On Reset circuit is powered down and PORB
will follow AVDD.
In most applications the time required for the device to release PORB high will be determined by
the charge time of the VMID node.
Figure 5 Typical Power Up Sequence Where DVDD is Powered Before AVDD
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Figure 6 Typical Power Up Sequence Where AVDD is Powered Before DVDD
Typical POR Operation (typical values, not tested)
SYMBOL
MIN
TYP
MAX
UNIT
Vpora
Vporr
Vpora_off
Vpord_off
0.5
0.5
1.0
0.6
0.7
0.7
1.4
0.8
1.0
1.1
2.0
1.0
V
V
V
V
In a real application the designer is unlikely to have control of the relative power up sequence of
AVDD and DVDD. Using the POR circuit to monitor VMID ensures a reasonable delay between
applying power to the device and Device Ready.
Figure 5 and Figure 6 show typical power up scenarios in a real system. Both AVDD and DVDD
must be established and VMID must have reached the threshold Vporr before the device is ready
and can be written to. Any writes to the device before Device Ready will be ignored.
Figure 5 shows DVDD powering up before AVDD. Figure 6 shows AVDD powering up before
DVDD. In both cases, the time from applying power to Device Ready is dominated by the charge
time of VMID.
A 10uF cap is recommended for decoupling on VMID. The charge time for VMID will dominate the
time required for the device to become ready after power is applied. The time required for VMID
to reach the threshold is a function of the VMID resistor string and the decoupling capacitor. The
Resistor string has a typical equivalent resistance of 33kohm (+/-20%). Assuming a 10uF
capacitor, the time required for VMID to reach threshold of 1V is approx 74ms.
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DEVICE DESCRIPTION
INTRODUCTION
The WM8718 is a high performance DAC designed for digital consumer audio applications. Its
range of features makes it ideally suited for use in DVD players, AV receivers and other high-end
consumer audio equipment.
WM8718 is a complete 2-channel differential stereo audio digital-to-analogue converter, including
digital interpolation filter, multi-bit sigma delta with dither, switched capacitor multi-bit stereo DAC.
The WM8718 includes an on-chip digital volume control, configurable digital audio interface and a
3 wire MPU control interface. The WM8718 has left and right zero flag output pins, allowing the
user to control external muting circuits. It is fully compatible and an ideal partner for a range of
industry standard microprocessors, controllers and DSPs.
The software control interface may be asynchronous to the audio data interface. The control data
will be re-synchronised to the audio processing internally.
Operation using a master clock of 256fs, 384fs, 512fs or 768fs is provided, selection between
clock rates being automatically controlled. Sample rates (fs) from less than 8kHz to 192kHz are
allowed, provided the appropriate master clock is input. The audio data interface supports right
justified, left justified and I2S (Philips left justified, one bit delayed) interface formats along with a
highly flexible DSP serial port interface.
The device is packaged in a small 20-lead SSOP.
CLOCKING SCHEMES
In a typical digital audio system there is one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio
system’s Master Clock. The external master system clock can be applied directly through the
MCLK input pin with no software configuration necessary for sample rate selection.
Note that on the WM8718, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In
a system where there are a number of possible sources for the reference clock, it is
recommended that the clock source with the lowest jitter be used to optimise the performance of
the DAC.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Five popular
interface formats are supported:
•
Left Justified mode
•
Right Justified mode
•
I2S mode
•
DSP Mode A
•
DSP Mode B
All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits with the
exception that 32 bit data is not supported in right justified mode. DIN and LRCIN maybe
configured to be sampled on the rising or falling edge of BCKIN.
In left justified, right justified and I2S modes, the digital audio interface receives data on the DIN
input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is
present. LRCIN is also used as a timing reference to indicate the beginning or end of the data
words. The minimum number of BCKINs per LRCIN period is 2 times the selected word length.
LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word length
BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are
met.
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The WM8718 will automatically detect when data with a LRCIN period of exactly 32 BCKINs is
sent, and select 16-bit mode - overriding any previously programmed word length. Word length
will revert to a programmed value only if a LRCIN period other than 32 BCKINs is detected.
In DSP Mode A or DSP Mode B, the data is time multiplexed onto DIN. LRCIN is used as a
frame sync signal to identify the MSB of the first word. The minimum number of BCKINs per
LRCIN period is 2 times the selected word length. Any mark to space ratio is acceptable on
LRCIN provided the rising edge is correctly positioned. (See Figure 10 and Figure 11)
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1
2
3
n-2 n-1
MSB
n
1
LSB
2
3
n-2 n-1
MSB
n
LSB
Figure 7 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left data word and low during the right data word.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1
2
3
n-2 n-1
MSB
n
1
LSB
2
3
n-2 n-1
MSB
n
LSB
Figure 8 Right Justified Mode Timing Diagram
2
I S MODE
In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN
transition. LRCIN is low during the left data word and high during the right data word.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
1 BCKIN
1 BCKIN
DIN
1
2
3
MSB
n-2 n-1
n
LSB
1
MSB
2
3
n-2 n-1
n
LSB
Figure 9 I2S Mode Timing Diagram
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Production Data
DSP MODE A
In DSP Mode A, the first bit is sampled on the BCKIN rising edge following the one that detects a
low to high transition on LRCIN. No BCKIN edges are allowed between the data words. The word
order is DIN left, DIN right.
1 BCKIN
1 BCKIN
1/fs
LRCIN
BCKIN
LEFT CHANNEL
DIN
1
2
RIGHT CHANNEL
n
n-1
MSB
1
2
n-1
NO VALID DATA
n
LSB
Input Word Length (IWL)
Figure 10 DSP Mode A Timing Diagram
DSP MODE B
In DSP Mode B, the first bit is sampled on the BCKIN rising edge, which detects a low to high
transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is
DIN left, DIN right.
1/fs
LRCIN
BCKIN
LEFT CHANNEL
DIN
1
2
MSB
RIGHT CHANNEL
n
n-1
1
2
n-1
NO VALID DATA
n
1
LSB
Input Word Length (IWL)
Figure 11 DSP Mode B Timing Diagram
AUDIO DATA SAMPLING RATES
The master clock for WM8718 can range from 128fs to 768fs where fs is the audio sampling
frequency (LRCIN), typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used
to operate the digital filters and the noise shaping circuits.
The WM8718 has a master clock detection circuit that automatically determines the relationship
between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If
there is greater than 32 clocks error, the system will default to 768fs. The master clock should be
synchronised with LRCIN, although the WM8718 is tolerant of phase differences or jitter on this
clock. See Table 1.
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SAMPLING
RATE
(LRCIN)
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
176.4kHz
192kHz
MASTER CLOCK FREQUENCY (MHz) (MCLK)
128fs
192fs
256fs
384fs
512fs
768fs
4.096
5.6448
6.144
11.2896
12.288
22.5792
24.576
6.144
8.467
9.216
16.9344
18.432
33.8688
36.864
8.192
11.2896
12.288
22.5792
24.576
Unavailable
Unavailable
12.288
16.9340
18.432
33.8688
36.864
Unavailable
Unavailable
16.384
22.5792
24.576
Unavailable
Unavailable
Unavailable
Unavailable
24.576
33.8688
36.864
Unavailable
Unavailable
Unavailable
Unavailable
Table 1 Typical Relationships Between Master Clock Frequency and Sampling Rate
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using a 3-wire (SPI-compatible) interface. In this
mode, SDIN is used for the program data, SCLK is used to clock in the program data and LATCH
is used to latch in the program data. The 3-wire interface protocol is shown in Figure 12.
LATCH
SCLK
SDIN
A6
A5
A4
A3
A2
A1
A0
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 12 3-Wire Serial Control Interface
Notes:
1. A[6:0] are Control Address Bits
2. D[8:0] are Control Data Bits
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REGISTER MAP
WM8718 uses a total of 4 program registers, which are 16-bits long. These registers are all
loaded through input pin SDIN, using the 3-wire serial control mode as shown in 9.
A6
A5
A4
A3
A2
A1
A0
D8
D7
D6
D5
D4
D3
D2
D1
D0
M0
0
0
0
0
0
0
0
UPDATEL
LAT7
LAT6
LAT5
LAT4
LAT3
LAT2
LAT1
LAT0
M1
0
0
0
0
0
0
1
UPDATER
RAT7
RAT6
RAT5
RAT4
RAT3
RAT2
RAT1
RAT0
M2
M3
0
0
0
0
0
0
0
0
0
0
1
1
0
ZCDINIT ZEROFLR
1
1
0
REV
1
1
0
0
BCP
ATC
ADDRESS
1
1
0
0
LRP
FMT[1]
PWDN DEEMPH
FMT[0]
IWL[1]
MUT
IWL[0]
DATA
Table 2 Mapping of Program Registers
Note:
1. These register bits must be written as 0 otherwise device function can not be guaranteed.
REGISTER
ADDRESS
(A3,A2,A1,A0)
BITS
0000
DACL
Attenuation
[7:0]
LAT[7:0]
8
UPDATEL
0001
DACR
Attenuation
[7:0]
RAT[7:0]
8
UPDATER
0
Attenuation data load control for right channel.
0: Store DACR in intermediate latch (no change to output)
1: Store DACR and update attenuation on both channels.
0
MUT
0
Left and Right DACs Soft Mute Control.
0: No mute
1: Mute
1
DEEMPH
0
De-emphasis Control.
0: De-emphasis off
1: De-emphasis on
2
PWDN
0
Left and Right DACs Power-down Control
0: All DACs running, output is active
1: All DACs in power saving mode, output muted
7
ZEROFLR
0
Zero Flag Pin Control.
0: Channel independent
1: AND of both channels on ZEROFL output pin
8
ZCDINIT
0
Zero Cross Detect Control.
0: Zero cross detect enabled
1: Zero cross detect disabled
[1:0]
IWL[1:0]
10
Input Word Length.
00: 16-bit mode
01: 20-bit mode
10: 24-bit mode
11: 32-bit mode(not supported in right justified mode)
0010
Mode Control
0011
Format
Control
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NAME
DEFAULT
DESCRIPTION
11111111 (0dB) Attenuation data for left channel in 0.5dB steps, see Table 5
0
Attenuation data load control for left channel.
0: Store DACL in intermediate latch (no change to output)
1: Store DACL and update attenuation on both channels.
11111111 (0dB) Attenuation data for right channel in 0.5dB steps, see Table 5
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REGISTER
ADDRESS
(A3,A2,A1,A0)
Production Data
BITS
NAME
DEFAULT
DESCRIPTION
[3:2]
FMT[1:0]
10
Audio Data Format Select.
00: right justified mode
01: left justified mode
10: I2S mode
11: DSP mode
4
LRP
0
Polarity Select for LRCIN/DSP Mode Select.
0: normal LRCIN polarity/DSP late mode
1: inverted LRCIN polarity/DSP early mode
5
ATC
0
Attenuator Control.
0: All DACs use attenuation as programmed.
1: Right channel DACs use corresponding left DAC
attenuation
6
BCP
0
BCKIN Polarity
0: normal polarity
1: inverted polarity
7
REV
0
Output Phase Reversal, see Table 10
Table 3 Register Bit Descriptions
ATTENUATION CONTROL
Each DAC channel can be attenuated digitally before being applied to the digital filter.
Attenuation is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8
Attenuation control bits. All attenuation registers are double latched allowing new values to be
pre-latched to both channels before being updated synchronously. Setting the UPDATE bit on
any attenuation write will cause all pre-latched values to be immediately applied to the DAC
channels.
REGISTER
ADDRESS
BITS
LABEL
DEFAULT
0000
Attenuation
DACL
[7:0]
LAT[7:0]
11111111 (0dB)
8
UPDATEL
0
0001
Attenuation
DACR
[7:0]
RAT[7:0]
11111111 (0dB)
8
UPDATER
0
DESCRIPTION
Attenuation data for Left Channel DACL in 0.5dB steps.
Controls simultaneous update of all Attenuation Latches
0: Store DACL in intermediate latch (no change to output)
1: Store DACL and update attenuation on all channels.
Attenuation data for Right channel DACR in 0.5dB steps.
Controls simultaneous update of all Attenuation Latches
0: Store DACR in intermediate latch (no change to output)
1: Store DACR and update attenuation on all channels.
Table 4 Attenuation Register Map
Note:
1.
The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the
relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next input
sample.
2.
Care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise if the ZCDINIT
register bit has been set, (disabled).
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DAC OUTPUT ATTENUATION
Registers DACR and DACL control the left and right channel attenuation. Table 9 shows how the
attenuation levels are selected from the 8-bit words.
DACX[7:0]
ATTENUATION LEVEL
00(hex)
01(hex)
:
:
:
FE(hex)
FF(hex)
∞dB (mute)
127.5dB
:
:
:
0.5dB
0dB
Table 5 Attenuation Control Levels
MUTE MODES
Figure 13 shows the application and release of MUTE whilst a full amplitude sinusoid is being
played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace)
begins to decay exponentially from the DC level of the last input sample. The output will decay
towards VMID with a time constant of approximately 64 input samples. When MUTE is deasserted, the output will restart almost immediately from the current input sample.
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.001
0.002
0.003
0.004
0.005
0.006
Time(s)
Figure 13 Application and Release of Soft Mute
Setting the MUT register bit will apply a 'soft' mute to the input of the digital filters:
REGISTER ADDRESS
0010
Mode Control
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BIT
LABEL
DEFAULT
0
MUT
0
DESCRIPTION
Soft Mute select
0: Normal Operation
1: Soft mute both channels
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DE-EMPHASIS MODE
Setting the DEEMPH register bit puts the digital filters into de-emphasis mode:
REGISTER ADDRESS
0010
Mode Control
BIT
LABEL
DEFAULT
1
DEEMPH
0
DESCRIPTION
De-emphasis mode select:
0: De-emphasis Off
1: De-emphasis On
POWERDOWN MODE
Setting the PWDN register bit immediately connects all outputs to VMID and selects a low power
mode. All trace of the previous input samples is removed, but all control register settings are
preserved. When PWDN is cleared again the first 16 input samples will be ignored, as the FIR
will repeat it's power-on initialisation sequence.
REGISTER ADDRESS
0010
Mode Control
BIT
LABEL
DEFAULT
2
PWDN
0
DESCRIPTION
Power Down Mode Select:
0: Normal Mode
1: Power Down Mode
ZERO FLAG OUTPUTS
The WM8718 has two zero flag outputs pins. The WM8718 asserts a low on the corresponding
zero flag pin when a sequence of more than 1024 mid-rail signal is input to the chip. The user
can use the zero flag pins to control external muting circuits if required. To simplify external
circuitry there is an option to have both zero flag output’s ANDed internally and output on both
pins.
REGISTER
ADDRESS
0010
Mode
Control
BIT
LABEL
DEFAULT
7
ZEROFLR
0
DESCRIPTION
ZERO Flag Outputs:
0: Both pins enabled.
1: AND of both channels to both pins.
ZERO CROSS DETECT
When the WM8718 receives updates to the volume levels it will, by default, wait for the signal to
pass through mid-rail for each channel before applying the update for that particular channel. This
ensures that there is minimum distortion seen on the output when the volume is changed.
REGISTER ADDRESS
0010
Mode Control
BIT
LABEL
DEFAULT
8
ZCDINIT
0
DESCRIPTION
Zero Cross Detect Control:
0: Enabled
1: Disabled
SELECTION OF LRCIN POLARITY
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCIN. If
this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 7,
Figure 8 and Figure 9. Note that if this feature is used as a means of swapping the left and right
channels, a 1 sample phase difference will be introduced.
REGISTER ADDRESS
0011
Format Control
BIT
LABEL
DEFAULT
4
LRP
0
DESCRIPTION
LRCIN Polarity (normal)
0: normal LRCIN polarity
1: inverted LRCIN polarity
Table 6 LRCIN Polarity Control
In DSP modes, the LRCIN register bit is used to select between early and late modes (see Figure
10 and Figure 11.
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REGISTER ADDRESS
0011
Format Control
BIT
LABEL
DEFAULT
4
LRP
0
DESCRIPTION
DSP Format (DSP modes)
0: Late DSP mode
1: Early DSP mode
Table 7 DSP Format Control
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that
detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the
BCKIN rising edge, which detects a low to high transition on LRCIN. No BCKIN edges are allowed
between the data words. The word order is DIN left, DIN right.
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left
and right channel DACs from the next audio input sample. No update to the attenuation registers
is required for ATC to take effect. (The right channels registry settings are preserved.)
REGISTER ADDRESS
0011
PCM Control
BIT
LABEL
DEFAULT
5
ATC
0
DESCRIPTION
Attenuator Control Mode:
0: Right channels use Right
attenuation
1: Right Channels use Left
Attenuation
Table 8 Attenuation Control Select
BCKIN POLARITY
By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change
on the falling edge. Data sources which change LRCIN and DIN on the rising edge of BCKIN can
be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the
inverse of that shown in Figure 7, Figure 8, Figure 9, Figure 10 and Figure 11
REGISTER ADDRESS
0011
PCM Control
BIT
LABEL
DEFAULT
6
BCP
0
DESCRIPTION
BCKIN
0: normal polarity
1: inverted polarity
Table 9 BCKIN Polarity Control
OUTPUT PHASE REVERSAL
The REV register bit controls the phase of the output signal. Setting the REV bit causes the
phase of the output signal to be inverted.
REGISTER ADDRESS
0011
PCM Control
BIT
LABEL
DEFAULT
7
REV
0
DESCRIPTION
Analogue Output Phase
0: Normal
1: Inverted
Table 10 Output Phase Control
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DIGITAL AUDIO INTERFACE CONTROL REGISTERS
The WM8718 has a fully featured PCM digital audio interface whose interface format is selected
via the FMT [1:0] and IWL[1:0] register bits in register M3.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0010
Format Control
1:0
IWL[1:0]
00
Interface format Select
0010
Format Control
3:2
FMT[1:0]
00
Interface format Select
Table 11 Interface Format Controls
FMT[1]
FMT[0]
IWL[1]
IWL[0]
AUDIO INTERFACE DESCRIPTION
(NOTE 1)
0
0
0
0
16 bit right justified mode
0
0
0
1
20 bit right justified mode
0
0
1
0
24 bit right justified mode
0
0
1
1
Not available
0
1
0
0
16 bit left justified mode
0
1
0
1
20 bit left justified mode
0
1
1
0
24 bit left justified mode
0
1
1
1
32 bit left justified mode
1
0
0
0
16 bit I S mode
1
0
0
1
20 bit I2S mode
1
0
1
0
24 bit I2S mode
1
0
1
1
32 bit I2S mode
1
1
0
0
16 bit DSP mode
1
1
0
1
20 bit DSP mode
1
1
1
0
24 bit DSP mode
1
1
1
1
32 bit DSP mode
2
Table 12 Audio Data Input Format
Note:
1.
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In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If
the DAC is programmed to receive 16 or 20 bit data, the WM8718 pads the unused LSBs
with ZEROS. If the DAC is programmed into 32-bit mode, the 8 LSBs are treated as zero.
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DIGITAL FILTER CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
Passband Edge
-3dB
Passband Ripple
f < 0.444fs
Stopband Attenuation
f > 0.555fs
MIN
TYP
MAX
UNIT
±0.05
dB
0.487fs
-60
dB
Table 13 Digital Filter Characteristics
DAC FILTER RESPONSES
0.2
0
0.15
-20
-40
Response (dB)
Response (dB)
0.1
-60
0.05
0
-0.05
-80
-0.1
-100
-0.15
-120
-0.2
0
0.5
1
1.5
Frequency (Fs)
2
2.5
3
Figure 14 DAC Digital Filter Frequency Response
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (Fs)
0.35
0.4
0.45
0.5
Figure 15 DAC Digital Filter Ripple – 44.1, 48 and 96kHz
– 44.1, 48 and 96kHz
0.2
0
0
-0.2
Response (dB)
Response (dB)
-20
-40
-0.4
-0.6
-60
-0.8
-80
-1
0
Figure 16
0.2
0.4
0.6
Frequency (Fs)
0.8
DAC Digital Filter Frequency Response
1
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (Fs)
0.35
0.4
0.45
0.5
Figure 17 DAC Digital Filter Ripple – 192kHz
– 192kHz
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DIGITAL DE-EMPHASIS CHARACTERISTICS
0
1
0.5
-2
Response (dB)
Response (dB)
0
-4
-6
-0.5
-1
-1.5
-2
-8
-2.5
-10
-3
0
2
4
6
8
10
Frequency (kHz)
12
14
16
Figure 18 De-Emphasis Frequency Response (32kHz)
0
2
4
6
8
10
Frequency (kHz)
12
14
16
Figure 19 De-Emphasis Error (32kHz)
0
0.4
0.3
-2
Response (dB)
Response (dB)
0.2
-4
-6
0.1
0
-0.1
-0.2
-8
-0.3
-10
-0.4
0
5
10
Frequency (kHz)
15
20
Figure 20 De-Emphasis Frequency Response (44.1kHz)
0
5
10
Frequency (kHz)
15
20
Figure 21 De-Emphasis Error (44.1kHz)
0
1
0.8
-2
0.6
Response (dB)
Response (dB)
0.4
-4
-6
0.2
0
-0.2
-0.4
-8
-0.6
-0.8
-10
-1
0
5
10
15
Frequency (kHz)
20
Figure 22 De-Emphasis Frequency Response (48kHz)
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0
5
10
15
Frequency (kHz)
20
Figure 23 De-Emphasis Error (48kHz)
PD Rev 4.3 November 2006
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Production Data
TYPICAL PERFORMANCE
-86
-88
-90
-92
-94
-96
-98
d
B
r
-100
-102
-104
A
-106
-108
-110
-112
-114
-116
-118
-120
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBV
Figure 24 THD+N versus Input Amplitude (@ 1kHz, 'A' weighted)
+0
-10
-20
-30
-40
d
B
r
-50
A
-70
-60
-80
-90
-100
-110
-120
30
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 25 THD+N versus Frequency ('A' weighted)
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Production Data
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS – 20 LEAD SSOP
Figure 26 External Components Diagram – 20 lead SSOP
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Production Data
RECOMMENDED EXTERNAL COMPONENTS – 24 LEAD QFN
Figure 27 External Components Diagram – 24 lead QFN
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
De-coupling for DVDD and AVDD
C4 and C7
10µF
C1 and C6
0.1µF
De-coupling for DVDD and AVDD
C5
0.1uF
De-coupling for VREFP positive DAC reference supply
C2
C3
C8
0.1µF
10µF
10µF
R1
33Ω
Reference de-coupling capacitors for VMID pin.
Filtering for VREFP. Omit if AVDD low noise.
Filtering for VREP. Use 0Ω if AVDD low noise.
Table 14 External Components Description
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WM8718
Production Data
RECOMMENDED ANALOGUE LOW PASS FILTER FOR PCM DATA FORMAT
(OPTIONAL)
LOUTN
R1 2K7 Ω
R2 2K7Ω
C2
Left
LOUTP
C1
220pF
680pF
R3 3K Ω
R4 2K7Ω
R5 3K Ω
-
WM8718
ROUTN
C3
R6
OP
+
C4
680pF 220pF
2K7Ω
Right
ROUTP
other
channel
Figure 28 Recommended Low Pass Filter (Optional)
Note:
1.
Additional information on suitable output filters can be found in Application Note WAN0171.
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WM8718
Production Data
PACKAGE DIMENSIONS – 20 LEAD SSOP
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
b
DM0015.C
e
20
11
E1
1
E
GAUGE
PLANE
10
Θ
D
A A2
c
A1
0.25
L
L1
-C0.10 C
Symbols
A
A1
A2
b
c
D
e
E
E1
L
L1
θ
MIN
----0.05
1.65
0.22
0.09
6.90
7.40
5.00
0.55
o
0
REF:
Dimensions
(mm)
NOM
--------1.75
0.30
----7.20
0.65 BSC
7.80
5.30
0.75
1.25 REF
o
4
SEATING PLANE
MAX
2.0
----1.85
0.38
0.25
7.50
8.20
5.60
0.95
o
8
JEDEC.95, MO -150
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8718
PACKAGE DIMENSIONS – 24 LEAD QFN
Production Data
FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.9 mm BODY, 0.50 mm LEAD PITCH
DM045.A
DETAIL 1
D
D2
19
24
1
18
EXPOSED
GROUND 6
PADDLE
A
INDEX AREA
(D/2 X E/2)
4
E2
E
SEE DETAIL 2
13
6
2X
12
7
b
e
1
bbb M C A B
2X
aaa C
aaa C
TOP VIEW
BOTTOM VIEW
DETAIL 1
DETAIL 2
A
0.08 C
45
degrees
A1
SIDE VIEW
C
Datum
0.32mm
DETAIL 2
SEATING PLANE
L
L1
5
1
ccc C
A3
EXPOSED
GROUND
PADDLE
W
Terminal
tip
e/2
e
R
T
A3
G
H
b
Exposed lead
Half etch tie bar
DETAIL 2
Symbols
A
A1
A3
b
D
D2
E
E2
e
G
H
L
L1
T
MIN
0.80
0
0.18
2.55
2.55
0.30
0.03
Dimensions (mm)
NOM
MAX
NOTE
0.90
1.00
0.02
0.05
0.20 REF
1
0.30
0.25
4.00
2.70
4.00
2.70
0.50 BSC
0.213
0.1
0.40
2.80
2
2.80
2
0.50
0.15
7
0.1
0.2
W
Tolerances of Form and Position
aaa
bbb
ccc
REF:
0.15
0.10
0.10
JEDEC, MO-220, VARIATION VGGD-2.
NOTES:
1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. FALLS WITHIN JEDEC, MO-220, VARIATION VGGD-2.
3. ALL DIMENSIONS ARE IN MILLIMETRES.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002.
5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
7. DEPENDING ON THE METHOD OF LEAD TERMINATION AT THE EDGE OF THE PACKAGE, PULL BACK (L1) MAY BE PRESENT.
8. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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31
WM8718
Production Data
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right
to make changes to its products and specifications or to discontinue any product or service without notice. Customers should
therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product
design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such
selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction
can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of
products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual
property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be
or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval,
licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third
party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not
liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this
datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that
person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon
by any person.
ADDRESS:
Wolfson Microelectronics plc
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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PD Rev 4.3 November 2006
32